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Hi all, I'm working on an FPGA implementation of an image processing algorithm. I'll be using the ML401 to do the job which has DDR memory and a VGA port to output the image directly on screen. Should I go with a microblaze solution? EDK comes with DDR and VGA controllers for this board, however I'm not at all familiar with it regarding the buses and stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the memory controller and I've also found a VGA/LCD display module on opencores.org. So both solutions seem viable to me (or do they not?), which path should I choose? Please comment. Thanks!Article: 106701
Many thanks! Syms.Article: 106702
bm wrote: > Hi everybody, > Isi it possible to connect directly FPGA ouptuts to USB line like this : > http://osainto.free.fr/USBHOST/usbDirect.pdf > (Pull downs are necessary to be able to act as USB Host.) > And then to use a dedicated IP for USB host role (some on opencores ) Which version of USB are you interested in? USB Full Speed has much less stringent requirements on the PHY than does USB v 2.0 High Speed. I have not heard of anyone doing either in an FPGA, but I don't know that it won't work for Full Speed.Article: 106703
Hi everyone, I compared the prices of two FPGAs from Digikey (http://www.digikey.com): +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. Price: 47.87$ +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. Price: 18.9$ Im relativly new to the FPGA world, but given the larger numbers of LC's and I/O pins that cyclone has, I don't understand why spartan-3 is more expensive? Is there another parameter that I am missing here? Note that I don't find these huge price differences only in Digikey. JJArticle: 106704
"fpganovice" <alecwei@gmail.com> wrote in message news:1155833480.035692.283020@b28g2000cwb.googlegroups.com... > Hi all, > > I'm working on an FPGA implementation of an image processing algorithm. > I'll be using the ML401 to do the job which has DDR memory and a VGA > port to output the image directly on screen. Should I go with a > microblaze solution? EDK comes with DDR and VGA controllers for this > board, however I'm not at all familiar with it regarding the buses and > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > memory controller and I've also found a VGA/LCD display module on > opencores.org. So both solutions seem viable to me (or do they not?), > which path should I choose? Please comment. Thanks! > If you don't need a CPU, then you don't need EDK either. If you do need a CPU, it is much easier to use EDK. However, if you decide not to use EDK you will probably have to spend more time interfacing your pieces, e.g. the opencores VGA controller probably needs a Wishbone bus... On the side note, it might be worth mentioning that some of the EDK ready-to-use cores are behind performance-wise from what is generally available, e.g. I believe MIG allows for faster DDRAM interfaces than you could achieve by using any of the EDK memory controllers. /MikhailArticle: 106705
jid...@hotmail.com wrote: > Hi everyone, > > I compared the prices of two FPGAs from Digikey > (http://www.digikey.com): > +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. > Price: 47.87$ > > +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. > Price: 18.9$ > > Im relativly new to the FPGA world, but given the larger numbers of > LC's and I/O pins that cyclone has, I don't understand why spartan-3 is > more expensive? Is there another parameter that I am missing here? Note > that I don't find these huge price differences only in Digikey. Possibly because you are comparing two very different sized parts in two very different packages. The EP1C6 is in a 240 pin QFP (read lower cost package) with about 6000 LEs. The XC3S1000 is a newer technology which should be cheaper, but you picked a BGA package (which tends to cost more than QFPs) and a *much* larger part. The XC3S1000 has 1920 CLBs with 8 LCs each or 15,360 (compared to the 17,280 claimed by the data sheet). I think the XC3S400 would be a better comparison with about 7,168 LCs. I suggest that you compare the Cyclone II and pick an equivalent part. How about the EP2C20F256C8 with 18,752 LCs in the same 256 pin BGA at $42.70...? Now it is only a bit cheaper.Article: 106706
radarman wrote:
> I agree - which is why I only produce state machines in HDL Designer
> that need to be documented, or are designed by someone else.
The quartus hdl/state machine viewer
works the other way around.
It picks state machines out of vhdl or verilog
code and can print them like this:
http://home.comcast.net/~mike_treseler/pseudo_states.pdf
-- Mike Treseler
Article: 106707Hi Mikhail, Thanks for your reply. The VGA core does use a Wishbone bus, and it has built-in Wishbone master and slave interfaces. It seems like I just need to set some registers through the slave and get access to external memory through the master. Therefore I was thinking those interfaces could connect with my FPGA hardware directly, or do I still need something to talk to the core? Thanks again. MM wrote: > "fpganovice" <alecwei@gmail.com> wrote in message > news:1155833480.035692.283020@b28g2000cwb.googlegroups.com... > > Hi all, > > > > I'm working on an FPGA implementation of an image processing algorithm. > > I'll be using the ML401 to do the job which has DDR memory and a VGA > > port to output the image directly on screen. Should I go with a > > microblaze solution? EDK comes with DDR and VGA controllers for this > > board, however I'm not at all familiar with it regarding the buses and > > stuff. If I use ISE only, I'll probably use MIG 1.5 to generate the > > memory controller and I've also found a VGA/LCD display module on > > opencores.org. So both solutions seem viable to me (or do they not?), > > which path should I choose? Please comment. Thanks! > > > > If you don't need a CPU, then you don't need EDK either. If you do need a > CPU, it is much easier to use EDK. However, if you decide not to use EDK you > will probably have to spend more time interfacing your pieces, e.g. the > opencores VGA controller probably needs a Wishbone bus... > > On the side note, it might be worth mentioning that some of the EDK > ready-to-use cores are behind performance-wise from what is generally > available, e.g. I believe MIG allows for faster DDRAM interfaces than you > could achieve by using any of the EDK memory controllers. > > > /MikhailArticle: 106708
Full Speed "rickman" <gnuarm@gmail.com> wrote in message news:1155834907.449717.107780@b28g2000cwb.googlegroups.com... > bm wrote: >> Hi everybody, >> Isi it possible to connect directly FPGA ouptuts to USB line like this : >> http://osainto.free.fr/USBHOST/usbDirect.pdf >> (Pull downs are necessary to be able to act as USB Host.) >> And then to use a dedicated IP for USB host role (some on opencores ) > > Which version of USB are you interested in? USB Full Speed has much > less stringent requirements on the PHY than does USB v 2.0 High Speed. > I have not heard of anyone doing either in an FPGA, but I don't know > that it won't work for Full Speed. >Article: 106709
bm schrieb: > Full Speed > "rickman" <gnuarm@gmail.com> wrote in message > news:1155834907.449717.107780@b28g2000cwb.googlegroups.com... > > bm wrote: > >> Hi everybody, > >> Isi it possible to connect directly FPGA ouptuts to USB line like this : > >> http://osainto.free.fr/USBHOST/usbDirect.pdf > >> (Pull downs are necessary to be able to act as USB Host.) > >> And then to use a dedicated IP for USB host role (some on opencores ) > > > > Which version of USB are you interested in? USB Full Speed has much > > less stringent requirements on the PHY than does USB v 2.0 High Speed. > > I have not heard of anyone doing either in an FPGA, but I don't know > > that it won't work for Full Speed. > > FS and LS should be no big issue. There are some folks doing LS host with 100% software in small 2USD microcontrollers! one japanese FPGA guy has some nifty usb host thing, he has developed a special 1 bit processor that he uses as USB host engine. well the purpose for him is to use USB keyboard for some gaming gadget. Antti http://xilant.comArticle: 106710
On Thu, 17 Aug 2006 11:04:44 -0500, "RCIngham" <robert.ingham@smiths-aerospace.com> wrote: >I suspect that the Xilinx core is fixed-point, and handles the data growth >that happens during a FFT in some manner described in its documentation. If >it doesn't, then don't use it. It's fixed-point (vfft32 is, anyway). It does bit growth, but you have to handle the extra bits yourself. >You could use a number representation such as Q1.15 that handles numbers >in the range -1.0 to +1.0, and do scaling at each pass of the FFT. This is actually no better than an integer representation - if you start with Q1.15, then you have to extend to Q1.18, or whatever, after the first pass, and so on. Fixed-point FFTs are pretty useless. If you've got a small dynamic range in the input, then you'll have a large dynamic range in the output. Coding a floating-point adder and multiplier is probably a lot easier than understanding the limitations of a fixed-point FFT and using it effectively. EvanArticle: 106711
The FFT core is not floatingpoint as far as I know. I can input real data strait from an AD converter (witch is fixpoint in nature). My problem is acually that I need a windowing function on top of that. I think the windowing function multiply the data from an AD converter with a variable that vary from 0 (in the beginning of the datastream) to 1 (in the middle of it) to 0 again in the end, and that ends up with a floatingpoint number. RaymondArticle: 106712
Interesting ...Any pointer ? "Antti" <Antti.Lukats@xilant.com> wrote in message news:1155837044.650337.85350@m79g2000cwm.googlegroups.com... > bm schrieb: > >> Full Speed >> "rickman" <gnuarm@gmail.com> wrote in message >> news:1155834907.449717.107780@b28g2000cwb.googlegroups.com... >> > bm wrote: >> >> Hi everybody, >> >> Isi it possible to connect directly FPGA ouptuts to USB line like this >> >> : >> >> http://osainto.free.fr/USBHOST/usbDirect.pdf >> >> (Pull downs are necessary to be able to act as USB Host.) >> >> And then to use a dedicated IP for USB host role (some on opencores ) >> > >> > Which version of USB are you interested in? USB Full Speed has much >> > less stringent requirements on the PHY than does USB v 2.0 High Speed. >> > I have not heard of anyone doing either in an FPGA, but I don't know >> > that it won't work for Full Speed. >> > > > FS and LS should be no big issue. There are some folks doing LS host > with 100% software in small 2USD microcontrollers! > > one japanese FPGA guy has some nifty usb host thing, he has developed > a special 1 bit processor that he uses as USB host engine. well the > purpose > for him is to use USB keyboard for some gaming gadget. > > Antti > http://xilant.com >Article: 106713
Raymond skrev: > The FFT core is not floatingpoint as far as I know. OBS I MENT FIXPOINT SORRY > > I can input real data strait from an AD converter (witch is fixpoint in > nature). My problem is acually that I need a windowing function on top > of that. I think the windowing function multiply the data from an AD > converter with a variable that vary from 0 (in the beginning of the > datastream) to 1 (in the middle of it) to 0 again in the end, and that > ends up with a floatingpoint number. > > RaymondArticle: 106714
Raymond wrote: > The FFT core is not floatingpoint as far as I know. > > I can input real data strait from an AD converter (witch is fixpoint in > nature). My problem is acually that I need a windowing function on top > of that. I think the windowing function multiply the data from an AD > converter with a variable that vary from 0 (in the beginning of the > datastream) to 1 (in the middle of it) to 0 again in the end, and that > ends up with a floatingpoint number. So you need a fixed-point windowing fucntion.Article: 106715
jidan1@hotmail.com wrote: > Hi everyone, > > I compared the prices of two FPGAs from Digikey > (http://www.digikey.com): > +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. > Price: 47.87$ > > +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. > Price: 18.9$ > > Im relativly new to the FPGA world, but given the larger numbers of > LC's and I/O pins that cyclone has, I don't understand why spartan-3 is > more expensive? Is there another parameter that I am missing here? Note > that I don't find these huge price differences only in Digikey. > > JJ the price difference would be mainly due to the difference in logic density. the Xilinx XC3S1000 has more LUTs (4-input Look Up Tables) than the Altera EP1C6. if price is a concern, you might consider Lattice's low cost FPGA, the LatticeEC Vendor Device LUTs 1pc. Price -------- ----------- --------- ---------- Xilinx XC3S1000 15K ~$50.00 Altera EP1C6 6K ~$19.00 Lattice LFEC6 6K ~$18.00 Lattice LFEC15 15K ~$36.00 http://www.latticesemi.com/products/fpga/index.cfm hope this helps. rgds, bart, latticeArticle: 106716
bm schrieb: > Interesting ...Any pointer ? you really learn how to goofle ! :) just enter "usb fpga ukp" as search term and there you, first hit! AnttiArticle: 106717
Antti wrote: > bm schrieb: > > > Interesting ...Any pointer ? > > you really learn how to goofle ! :) > > just enter "usb fpga ukp" as search term and there you, first hit! Was this a typo? I get a bunch of links to sites giving pricing in Brittish pounds. Maybe you were referring to this... http://www.opencores.org/projects.cgi/web/usb_phy/overviewArticle: 106718
bart wrote: > jidan1@hotmail.com wrote: > > Hi everyone, > > > > I compared the prices of two FPGAs from Digikey > > (http://www.digikey.com): > > +) Xilinx Spartan-3, XC3S1000 - 4FTG256C with LC:1920, I/O pins:173. > > Price: 47.87$ > > > > +) Altera Cyclone, EP1C6Q240C8N - ND with LC:5980, I/O pins:185. > > Price: 18.9$ > > > > Im relativly new to the FPGA world, but given the larger numbers of > > LC's and I/O pins that cyclone has, I don't understand why spartan-3 is > > more expensive? Is there another parameter that I am missing here? Note > > that I don't find these huge price differences only in Digikey. > > > > JJ > the price difference would be mainly due to the difference in logic > density. the Xilinx XC3S1000 has more LUTs (4-input Look Up Tables) > than the Altera EP1C6. if price is a concern, you might consider > Lattice's low cost FPGA, the LatticeEC > > Vendor Device LUTs 1pc. Price > -------- ----------- --------- ---------- > Xilinx XC3S1000 15K ~$50.00 > Altera EP1C6 6K ~$19.00 > Lattice LFEC6 6K ~$18.00 > Lattice LFEC15 15K ~$36.00 > > http://www.latticesemi.com/products/fpga/index.cfm > hope this helps. > rgds, > bart, lattice What about the LFE2 parts? I thought they were starting to ship now and even cheaper.Article: 106719
rickman wrote: > What about the LFE2 parts? I thought they were starting to ship now > and even cheaper. the original question referred to distributors such as Digikey, so at the 6K and 15K LUT densities, the 130nm LatticeEC is the best fit for devices that are available from Mouser and other specialized distributors off the shelf. you're right, the 90nm LatticeECP2 device is now sampling and is lower priced, however the smaller densities (6K-15KLUT) of the LatticeECP2 are not currently available through distributors such as Mouser. http://www.mouser.com/latticesemi/Article: 106720
rickman schrieb: > Antti wrote: > > bm schrieb: > > > > > Interesting ...Any pointer ? > > > > you really learn how to goofle ! :) > > > > just enter "usb fpga ukp" as search term and there you, first hit! > > Was this a typo? I get a bunch of links to sites giving pricing in > Brittish pounds. > > Maybe you were referring to this... > > http://www.opencores.org/projects.cgi/web/usb_phy/overview NO. and NO typo. google search web search from my PC with keywords "usb fpga ukp" returns as first hit the following URL (I just rechecked!) http://www.geocities.jp/kwhr0/hard/pc8001.html AnttiArticle: 106721
Well, I really had enough of this last night (with Impact crashing every 5 minutes instead of the usual every 20 minutes). Was so -><- close to trash the board and pretend it was bricked :) Somehow, I forced myself to go back to it when I got home right after work, and tried to read from flash after configuration. I got mismatches like this in few places (above: read, below: original mcs): 7485,7490c7485,7490 < :10D3A000000000000000000000000000FFFFFFFF81 < :10D3B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D < :10D3C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6D < :10D3D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5D < :10D3E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4D < :10D3F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D --- > :10D3A000000000000000000000000000000000007D > :10D3B000000000000000000000000000000000006D > :10D3C000000000000000000000000000000000005D > :10D3D000000000000000000000000000000000004D > :10D3E000000000000000000000000000000000003D > :10D3F000000000000000000000000000000000002D The error rate is something like 2-3%. The board is new*, the cable is new. Hell, even the computer I ran this from is shiny new. Everything works just fine when programming the FPGA directly. Does Anyone know what the problem is? Is xilinx flash this unreliable, or am I doing something wrong? regards - Burns * actually its really old, but totally unused. I just haven't cared enough to play with my xilinx boards. Very much thanks to a scary first encounter with ISE...Article: 106722
burn.sir@gmail.com wrote: > Well, I really had enough of this last night (with Impact crashing > every 5 minutes instead of the usual every 20 minutes). Was so -><- > close to trash the board and pretend it was bricked :) > > > Somehow, I forced myself to go back to it when I got home right after > work, and tried to read from flash after configuration. I got > mismatches like this in few places (above: read, below: original mcs): > > > 7485,7490c7485,7490 > < :10D3A000000000000000000000000000FFFFFFFF81 > < :10D3B000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D > < :10D3C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF6D > < :10D3D000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF5D > < :10D3E000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF4D > < :10D3F000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D > --- > >>:10D3A000000000000000000000000000000000007D >>:10D3B000000000000000000000000000000000006D >>:10D3C000000000000000000000000000000000005D >>:10D3D000000000000000000000000000000000004D >>:10D3E000000000000000000000000000000000003D >>:10D3F000000000000000000000000000000000002D > > > > The error rate is something like 2-3%. The board is new*, the cable is > new. Hell, even the computer I ran this from is shiny new. Everything > works just fine when programming the FPGA directly. > > Does Anyone know what the problem is? Is xilinx flash this unreliable, > or am I doing something wrong? > > > regards > - Burns > > > > * actually its really old, but totally unused. I just haven't cared > enough to play with my xilinx boards. Very much thanks to a scary first > encounter with ISE... That looks like it just stopped writing 0's ? If you read 30 times, do you get the matching 30 results ? - that checks read integrity. Can you get the Flash into a device programmer, that can read it. That gives a second verify of contents. Are these errors always at start/finish. ? I have seen other devices flash-error on preamble or post-amble timing errors. -jgArticle: 106723
Antti wrote: > rickman schrieb: > > > Antti wrote: > > > bm schrieb: > > > > > > > Interesting ...Any pointer ? > > > > > > you really learn how to goofle ! :) > > > > > > just enter "usb fpga ukp" as search term and there you, first hit! > > > > Was this a typo? I get a bunch of links to sites giving pricing in > > Brittish pounds. > > > > Maybe you were referring to this... > > > > http://www.opencores.org/projects.cgi/web/usb_phy/overview > NO. > and NO typo. > > google search web search from my PC with keywords "usb fpga ukp" > returns as first hit the following URL (I just rechecked!) > > http://www.geocities.jp/kwhr0/hard/pc8001.html Well I guess you are just special then. I get http://lists.distributed.net/pipermail/hardware/1998-October/000325.html and I would have no idea why you would use "ukp" as part of the search. Care to explain or do you prefer to remail mysterious about it? BTW, the address you posted gives me a web page in an Asian language, possibly Japanese. I am not able to read any of it.Article: 106724
Raymond, In what you are describing, it looks like you are actually doing a FIR filter in the frequency domain. So my question, why not using this FIR filter? It it far less complex than a FFT, and the result will be the same. Even if it is a complex window, you can use the Remez Exchange algo to work it out. Regards, Luc On 17 Aug 2006 11:15:59 -0700, "Raymond" <raybakk@yahoo.no> wrote: > >Raymond skrev: >> The FFT core is not floatingpoint as far as I know. >OBS I MENT FIXPOINT SORRY > >> >> I can input real data strait from an AD converter (witch is fixpoint in >> nature). My problem is acually that I need a windowing function on top >> of that. I think the windowing function multiply the data from an AD >> converter with a variable that vary from 0 (in the beginning of the >> datastream) to 1 (in the middle of it) to 0 again in the end, and that >> ends up with a floatingpoint number. >> >> Raymond
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