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"rickman" <gnuarm@gmail.com> wrote in message news:1157032693.254923.135250@h48g2000cwc.googlegroups.com... > > On a separate note, I can't believe some of the things we do here. Our > digital circuits are part of RF equipment so we are typically very > concerned with even low levels of noise in the RF region. To make sure > our boards are quiet we have an RF person review the design and board > layout. I was assisting on a design for a simple MCU board with an > attached GPS receiver. The RF guy was very concerned about various > noise sources that had burned him in the past and did a lot of what I > thought was overkill in the power distribution. I just found out that > he had the 6 layer stackup done with two ground planes and no power > plane! I suggested to the layout guy that it would be ok to flood fill > the signal layers with power plane and he said they are doing that, but > connecting to ground instead of power!!! So there is no effective > bypassing on this board above a couple hundred MHz and the freq of the > receiver is around 1.5 GHz. Do you think we will see any interference? The situation might not be so bad. When an RF engineer is interested in quiet power, there are filters between any noisy digital power planes and the power for the RF section, effectively eliminating any bypass gains achieved from the beautifully bypassed (but still RF-sensitivity compromising) power planes. There is a large variety of RF caps specifically used for in-line power decoupling that are effective *only* at the high frequencies partly because that's the only frequency of interest in the RF device. An oscillator at 1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz noise has been filtered out before hitting the effective 1.5 GHz bypassing. The truely effective board level decoupling can result in much better mixed-signal performance where discretes are connected directly to the shared power plane. True RF still seems like a much different animal to me where grounds really are king (with properly filtered and cascaded power distribution is regal as well).Article: 107701
jjlindula@hotmail.com wrote: > Hello, I'm posting this question here because I want responses from > engineers, so please don't be offended. I want to know what your > thoughts are concerning Performance Appraisals at your company, are > they beneficial, how are they conducted, and what is the best way go > give performance appraisals? > > Where I work, the manager brings you into their office, starts a series > of short questions concerning your family and other things not relating > to your job and then finally gives you a pat on the back and says, good > job. Not much is really discussed and therefore not really useful. As a general rule, the more complicated the HR form is, the less useful it is for evaluating technical people.Article: 107702
Joerg wrote: > Know what? What really bad typos indicate? Pretty clear, if someone > affords his or her resume that little attention to detail I assume it'll > be the same for a design. Can't use that. Or the person is dyslexic with a foriegn native tounge, language impaired, but with experience and genuis in design that can easily be offset by using good clerical assistant to help the designer with writing, editing, and other written language issues.Article: 107703
pomerado@hotmail.com wrote: > As a general rule, the more complicated the HR form is, the less useful > it is for evaluating technical people. By that rule, a blank page of paper is best .... I think we have a scaling problem.Article: 107704
rickman wrote: > When you read an app note and the vendor says they won't guarantee that > the part will work if you don't follow the app note, does that mean if > you follow the app note they *do* guarantee your design??? hellofa good question :)Article: 107705
fpga_toys@yahoo.com wrote: > pomerado@hotmail.com wrote: > >>As a general rule, the more complicated the HR form is, the less useful >>it is for evaluating technical people. > > > By that rule, a blank page of paper is best .... I think we have a > scaling problem. > Well, I guess they should leave the boxes for "Name" "Job grade" and "Employee number" :-) SteveArticle: 107706
In message <1157043027.125952.44340@m73g2000cwd.googlegroups.com>, dated Thu, 31 Aug 2006, fpga_toys@yahoo.com writes > >pomerado@hotmail.com wrote: >> As a general rule, the more complicated the HR form is, the less useful >> it is for evaluating technical people. > >By that rule, a blank page of paper is best .... I think we have a >scaling problem. > Yes, it's a log law; a blank sheet is minus infinity help. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107707
Steve Underwood wrote: > Well, I guess they should leave the boxes for "Name" "Job grade" and > "Employee number" :-) That would seriously hinder the personal expression in providing that information, as well as being overtly demanding. :)Article: 107708
bill.sloman@ieee.org wrote: > Joerg wrote: > >>Hello Bill, >> >> >>>>>>Glowing perfomance reviews and stock options are what companies give >>>>>>valued employees instead of raises. >>>>> >>>>>Good point, Luhan. In the big company, there is a salary schedule: how >>>>>much is getting paid to a person in this position. There is actually no >>>>>way for them to give any raise. >>>>> >>>>>Also this is how the loafers from HR are making themselves look very useful. >>> >>>>Then what is the alternative to HR, ( dont ask me, I havent had a >>>>"job" in almost 10 years), and I've never worked for a company that >>>>had a "modern" HR dept. In those days they where called " personnel" >>>>departments, much more human >>> >>>I've worked for a couple of places that were deliberately kept too >>>small - below 250 employees - to support a personnel department. The >>>managers and their secretaries had to do the necessary scut-work. It >>>seemd to work out. >>> >>>My experience of personnel departments, both as a job interviewer and >>>as a job interviewee, was that they ranged from the useless to the >>>obstructive. >>> >> >>That sounds a bit unfair. > > > It was certainly true for the sections of British and Australian > industry where I've worked. In the UK you have to learn not to judge any potential employer by their personnel department. If you don't, you'll never accept a job offer. I think UK personnel departments are a major factor in Britain's industrial decline. SteveArticle: 107709
<fpga_toys@yahoo.com> wrote in message news:1157042944.150997.294920@i42g2000cwa.googlegroups.com... > Or the person is dyslexic with a foriegn native tounge, language > impaired, but with experience and genuis in design that can easily be > offset by using good clerical assistant to help the designer with > writing, editing, and other written language issues. Presumably they'd mention that -- or anything else that would make them "unusual" -- on their resume? In general, if you know you're going to be needing "clerical" assistance in your job, presumably you'd also obtain such assistance on your resume? Joerg seems like a nice guy, I'm sure he'd give people the benefit of the doubt.Article: 107710
On Wed, 30 Aug 2006 23:07:56 +0200, martin griffith <mart_in_medina@yahoo.esXXX> wrote: >On Wed, 30 Aug 2006 13:59:17 -0700, in sci.electronics.design Eric >Jacobsen <eric.jacobsen@ieee.org> wrote: > ... >>So I've got about sixteen years of "stock option incentives" that have >>essentially cost me money. :( >> >> >>Eric Jacobsen >>Minister of Algorithms, Intel Corp. >>My opinions may not be Intel's opinions. >>http://www.ericjacobsen.org > > >wrong Algorithm maybe? > ><sorry> > > >martin ROTFL! Eric Jacobsen Minister of Algorithms, Intel Corp. My opinions may not be Intel's opinions. http://www.ericjacobsen.orgArticle: 107711
Austin Lesea wrote: > You may have to have very exotic > cooling in order not to melt down the device, at speeds like 550 MHz and > with all of the logic toggling. The Industrial temp spec is the > junction must be kept below 100C. Commercial grade must be kept below 85C. > > You could increase the clock rate till the device fails to operate > correctly, ... but in this application it would be > very difficult to know if it wasn't operating correctly! I have some experience with overclocking RAM and PC-CPUs and water cooling as well. First, overclocking hardly causes more than 20% in speed, and oft requires additional voltage in order to keep the signal integrity (rising problem). 10% more voltage + 20% more speed will cause more heat, whereby heat lowers the possible speed anyway. To run a device under these operating conditions, undercooling will have to be performed. One at least wil have to apply a water cooling system but even with the lowest temperatures, signals will fail from a certain freq on. Regarding cost, two FPGAs is the choice. :-) WC thus is only a choice, if a (group) FPGA runs under perfect timing but only has temperature problems because of a hot environment: I did not do that with FPGAs already, but with my first dual-PC-System , I was able to run two old 1200-Athlons (which used to become very hot) @1800 having only around 40degrees surface temp with both of the Athlons. They were producing more than 60Watts each.Article: 107712
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:upsehjp34.fsf@trw.com... > "Symon" <symon_brewer@hotmail.com> writes: > > > > I contend that the package impedance of modern FPGAs is such that any > > benefit that a board wide power plane's capacitance could provide to your > > design, over and above that which you can get from a small local plane and > > associated bypass capacitors, is negligible. The caps work up to a few > > hundred MHz, just about where the package stops working. Any noise on the > > supply above this frequency doesn't get to the silicon anyway. > > I'll chip in one more point (which I have not data for, but discussion > may be enlightening :-).. > > Even above the frequency at which the die won't see the noise due to > the package inductance, the noise on the planes may still cause > problems in passing EMC emissions tests, so you still have to be > careful at the top end. > > Out of interest - do you consider how your mini-planes resonate at > high frequencies? > > Cheers, > Martin > Hi Martin, As John says in his post, both the capacitance and dimensions of the 'mini-plane' is much smaller than a big plane, so its capacitance and quarter-wavelength is much smaller. This means that at the frequency at which the bypass caps and plane would potentially resonate is where the capacitors' ESR is huge. According to the Murata tool I linked in a previous post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with frequency beyond that. This ESR damps any potential resonance. Another reason why crappy Q is a good thing in this case. Cheers, Syms.Article: 107713
> There is still one thing that I donīt fully understand about Rick's > method. > The resonance of the power plane capacitance with the capacitors > inductance depends on the number and package of the capacitors ( the > capacitors inductance is related to the package). I donīt see how > changing the capacitors value (capacitive) can modify the position or > peak of that resonce. > IMHO 20 0.1uF capacitors will have the same resonance with the power > plane as 20 0.001uF capacitors (or even 10 0.01uF plus 10 0.001uF) > > So far I've been decoupling using different value capacitors because > that's the method that Xilinx recomends, but whithout seeing much logic > in the use of small value capacitors (if higher value can be used in > the same package). Now I think that Simonīs metod makes more sense. > > Regards So, the resonance is between the sum of the capacitance of the plane and the bypass cap and the inductance of the bypass cap. (The plane has very little inductance to contribute.) Using different values changes the total capacitance, I guess. The sims do show this effect, but they also show new resonances between different valued caps, but these are generally smaller than the plane resonance as the ESR of the bypass cap damps any resonance. Cheers, Syms.Article: 107714
"rickman" <gnuarm@gmail.com> wrote in message news:1157032693.254923.135250@h48g2000cwc.googlegroups.com... > > On a separate note, I can't believe some of the things we do here. Our > digital circuits are part of RF equipment so we are typically very > concerned with even low levels of noise in the RF region. To make sure > our boards are quiet we have an RF person review the design and board > layout. I was assisting on a design for a simple MCU board with an > attached GPS receiver. The RF guy was very concerned about various > noise sources that had burned him in the past and did a lot of what I > thought was overkill in the power distribution. I just found out that > he had the 6 layer stackup done with two ground planes and no power > plane! I suggested to the layout guy that it would be ok to flood fill > the signal layers with power plane and he said they are doing that, but > connecting to ground instead of power!!! So there is no effective > bypassing on this board above a couple hundred MHz and the freq of the > receiver is around 1.5 GHz. Do you think we will see any interference? > Rick, To me, it sounds as if your RF guy is doing exactly the right thing. It's what I would do. I'm interested in what coupling paths you see which could produce interference. Anyway, I'll let you into a little secret! At my workplace a few years back, an RF/Microwave guy started working. He's now moved on, but we remain good friends. I've learnt so much stuff from this guy, indeed, enough to be confident in posting and backing up my ideas and thoughts about bypass caps and PDSs on a public forum. So, why not buy your RF guy a few beers and listen to his thoughts on why he did what he did? You might even like to print out bits of this thread and ask his opinion. If nothing else, it'll be cheaper than taking a class. ;-) Anyway, be sure to report back on what happens with the board. Best regards, Syms.Article: 107715
"Daniel S." <digitalmastrmind_no_spam@hotmail.com> wrote in message news:5VpJg.60702$nJ1.973495@wagner.videotron.net... > Hi, > > Switching power supplies introduce ripple voltage on the voltage rails > they are regulating, requiring multiple LC stages for filtering which > further slows down the regulator's response time. > > Linear regulators reject this ripple (act like an active filter) but > they have finite tracking bandwidth which limits their usefulness beyond > 100kHz. Linears are a good choice when the front-end switcher operates > at lowish frequencies (<25kHz) where the linear regulator still offers > at least 40dB supply ripple rejection - some LC filtering on the LDO's > input is still necessary to remove high-frequency harmonics the LDO > cannot handle. > > Passive low-pass filters become increasingly impractical as frequencies > go down while active filters (like linears) become increasingly > effective. Because of this, precision voltage regulation is nearly > impossible to achieve with switching regulators but it is nearly trivial > and fairly inexpensive with linears. This is unlikely to change any time > soon, if ever. > > Switchers are good for noise-tolerant high-power circuits but linears > will remain necessary for low-noise low-power stuff like reference voltages. > > As for the actual topic of linear being necessary for MGTs, on top of > inherent switcher supply noise, there will be multi-tone noise from > switching inputs on input rails and heaps of other potentially nasty > stuff across the whole spectrum. Given the price of V2P and V4FX parts, > I would opt for not taking any chances and go with power -> LC -> LDO -> > C -> MGT... and read Xilinx's MGT power decoupling appnote a few times. > > > Symon wrote: > > Hi Heiner, > > I'd be interested in the response you get for this question. As linear > > regulators have a bandwidth of a 100kHz or so, I fail to see how they > > provide an advantage over a filtered switcher. > Hi Daniel, Thanks for your post, but I'm still somewhat confused. I agree that linear regulators only work well at removing noise at low frequencies, and that passive filtering is more effective at high frequencies. So, why not use a fast switcher, say switching at a few MHz, and passive filter its output. The passive filter wouldn't have a problem with "potentially nasty stuff across the whole spectrum". Are you saying that the MGTs are mostly adverse to low frequency noise? That seems somewhat strange for a multi-GHz device. BTW, I always make sure to defeat any burst modes in switcher circuits to reduce low frequency ripple. Thanks, Syms.Article: 107716
Symon wrote: > As John says in his post, both the capacitance and dimensions of the > 'mini-plane' is much smaller than a big plane, so its capacitance and > quarter-wavelength is much smaller. This means that at the frequency at > which the bypass caps and plane would potentially resonate is where the > capacitors' ESR is huge. According to the Murata tool I linked in a previous > post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with > frequency beyond that. This ESR damps any potential resonance. Another > reason why crappy Q is a good thing in this case. If the tool says the SRF is 3 GHz, I can't argue with that. But I don't believe it. The SRF for a 1 uF 0402 cap is typically below 10 MHz. Even many "low inductance" capacitors have a SRF of below 200 MHz. This is a very big discrepancy and will change your entire perspective if it is wrong. I susgest you verify this number. Is it possible that the SRF is 3 MHz? With a SRF below 10 MHz, it does not matter a lot where the parallel resonance is. There will be a wide range of frequencies between the SRF and where the plane has a low impedance that will have a very high impedance irrrespective of any resonance. Another thing, "high" ESR is good, but not so high that it interferes with the function of the capacitor. With a 1 ohm ESR it will not be a very good capacitor at lower frequencies where it is supposed to be capacitive.Article: 107717
John_H wrote: > "rickman" <gnuarm@gmail.com> wrote in message > news:1157032693.254923.135250@h48g2000cwc.googlegroups.com... > > > > On a separate note, I can't believe some of the things we do here. Our > > digital circuits are part of RF equipment so we are typically very > > concerned with even low levels of noise in the RF region. To make sure > > our boards are quiet we have an RF person review the design and board > > layout. I was assisting on a design for a simple MCU board with an > > attached GPS receiver. The RF guy was very concerned about various > > noise sources that had burned him in the past and did a lot of what I > > thought was overkill in the power distribution. I just found out that > > he had the 6 layer stackup done with two ground planes and no power > > plane! I suggested to the layout guy that it would be ok to flood fill > > the signal layers with power plane and he said they are doing that, but > > connecting to ground instead of power!!! So there is no effective > > bypassing on this board above a couple hundred MHz and the freq of the > > receiver is around 1.5 GHz. Do you think we will see any interference? > > The situation might not be so bad. When an RF engineer is interested in > quiet power, there are filters between any noisy digital power planes and > the power for the RF section, effectively eliminating any bypass gains > achieved from the beautifully bypassed (but still RF-sensitivity > compromising) power planes. Yes, he added an LDO between the switcher and the digital power because the digital power goes to the GPS module. This is a bit pointless because an LDO is only effective up to a few 10s of kHz. Then there is a ferrite bead which is not very effective until you get to high MHz. So that leaves a huge hole from about 100 kHz to maybe 100 MHz. Also the ferrite bead is only an impedance, not a cure. Noise can still couple to the load if it is not a low impedance. On the other hand a good power plane will decouple noise at the source and prevent it from reaching the ferrite filter. So good power planes are *always* a good thing for reducing noise. > There is a large variety of RF caps specifically used for in-line power > decoupling that are effective *only* at the high frequencies partly because > that's the only frequency of interest in the RF device. An oscillator at > 1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz noise > has been filtered out before hitting the effective 1.5 GHz bypassing. How do you make a capacitor less effective at low frequencies??? Wouldn't that be an inductor? > The truely effective board level decoupling can result in much better > mixed-signal performance where discretes are connected directly to the > shared power plane. True RF still seems like a much different animal to me > where grounds really are king (with properly filtered and cascaded power > distribution is regal as well). I don't know about the royal lineage. I do know that digital circuits are kept quiet with good power decoupling including low impedance across the spectrum. In this case the only way to filter 1.5 GHz in the power spectrum is with plane to plane capacitance.Article: 107718
Hi JJ, I suspect the truth of the matter is that it's hard to get this wrong. As long as you have enough capacitors with low impedance paths to the device, you're laughing. As to what is enough, one per power pin is a pretty good place to start. Use the biggest value in the smallest package you can. Some folks would apparently have you design power planes for each supply, that's three planes for your design. Kinda defeats the point of using a low-cost FPGA, save a few quid on an FPGA and then burn it on PCBs. You might consider routing the power and making sure you tie the power pins together at the device with a copper pour. Make _sure_ you don't skimp on ground planes. Also, some folks recommend a bunch of different values because of serial self resonant frequencies. In _my_ view this is bollocks, the Q of ceramic caps is so poor the effect is minimal. If the Q were better, you'd get problems with impedance peaks at the parallel resonances. As FPGA toys mentions, we've been thrashing this out in another thread. Why not have a read? It's kept me entertained for a few days! :-) Best wishes, Syms.Article: 107719
Symon wrote: > Rick, > To me, it sounds as if your RF guy is doing exactly the right thing. It's > what I would do. I'm interested in what coupling paths you see which could > produce interference. I think you should talk to the RF guy about that. He is responding to problems he had in the past that were fixed without understanding the cause. So now he is using the same bandaid to a problem that does not exist. BTW, the LDO he used in another design was to fix a noise problem in an audio circuit that obviously was due to lack of good power supply design. I see the main path for noise being the power distribution. If you keep that clean the only other path is coupling by emitted signals which are also reduced by good power decoupling. > Anyway, I'll let you into a little secret! At my workplace a few years back, > an RF/Microwave guy started working. He's now moved on, but we remain good > friends. I've learnt so much stuff from this guy, indeed, enough to be > confident in posting and backing up my ideas and thoughts about bypass caps > and PDSs on a public forum. > > So, why not buy your RF guy a few beers and listen to his thoughts on why he > did what he did? You might even like to print out bits of this thread and > ask his opinion. If nothing else, it'll be cheaper than taking a class. ;-) I had a conversation with him where I learned that his LDO in the digital power was a response to touching a hot stove. I don't have a lot of respect for that type of engineering. I also don't respect engineering that does not address problems with understanding. Rather than learn why the switching supply was making a low frequency noise he now adds LDOs to the power path for all digital circuits. That would not be so bad, but this is battery operated equipment and this has increased our power budget by over 13%. Anytime someone can show me a problem and tell me how an approach will solve the problem I am happy to listen. But adding circuits when there is no problem is not a good idea. > Anyway, be sure to report back on what happens with the board. I don't consider that to be the discriminator of what approach is correct. The digital circuitry is very small and likely not to create any major problems. But it is also likely to cause a small decrease in sensitivity that might be hard to measure without doing a performance test. I know they will not be doing any performance testing on this receiver. They will just fire it up and see if it can find the satellites in the factory. So no one will be right and no one will be wrong.... until the customer compares our units to a comercial GPS receiver and we don't hold track as well. But then it will be far too late to make changes. It would be much better to do it right the first time.Article: 107720
"rickman" <gnuarm@gmail.com> wrote: >jidan1@hotmail.com wrote: >> Hi, >> >> I want to design a development board containing Xilinx Spartan-3 >> XC3S400. My problem is regarding the number and values of bypass >> capacitors that I should use for the power supplies. >> I use 3 power supplies: VCCINT=1.2V; VCCAUX=2.5V; VCCO=3.3V. >> I took the Spartan-3 Starter Kit Board User Guide >> (http://direct.xilinx.com/bvdocs/userguides/ug130.pdf) as a refernce, >> but I fond it contradicts XAPP623 - Power Distribution System (PDS) >> Design: Using Bypass/Decoupling Capacitors >> (http://direct.xilinx.com/bvdocs/appnotes/xapp623.pdf). >> >> XAPP623 recommends for every power supply: > >...snip... > >These general recommendations are just that, general. To know how to >bypass a design first requires that you analyze your design to know how >much noise you can accept on the power plane and how large the current >transitions will be so you can calcualate a target impedance. It is >useful if you know how many outputs will be driving at what rate and >what length transmission lines. This can be used to get an idea of the >current spikes when your outputs change. These can also be analyzed >for frequency content. > >Then to design your power distribution you should provide capacitance >of various values to give the required impedance from about 1 kHz (the >high end of where the PSU is effective) to the max frequency determined >by your edge rates. I recommend that you use tantalums for the low >frequency range and several values of ceramic caps to smooth out the I can recommend the high capacity MLCC caps in 1210 size housing. Tantalums are not so reliable and can cause severe damage to the PCB when placed reverse. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 107721
"rickman" <gnuarm@gmail.com> wrote in message news:1157046974.215150.183350@m79g2000cwm.googlegroups.com... > Symon wrote: > > As John says in his post, both the capacitance and dimensions of the > > 'mini-plane' is much smaller than a big plane, so its capacitance and > > quarter-wavelength is much smaller. This means that at the frequency at > > which the bypass caps and plane would potentially resonate is where the > > capacitors' ESR is huge. According to the Murata tool I linked in a previous > > post, a 0402 X5R 1uF cap has an ESR of 1 ohm at 3GHz and rises with > > frequency beyond that. This ESR damps any potential resonance. Another > > reason why crappy Q is a good thing in this case. > > If the tool says the SRF is 3 GHz, I can't argue with that. But I > don't believe it. The SRF for a 1 uF 0402 cap is typically below 10 > MHz. Even many "low inductance" capacitors have a SRF of below 200 > MHz. This is a very big discrepancy and will change your entire > perspective if it is wrong. I susgest you verify this number. Is it > possible that the SRF is 3 MHz? > > With a SRF below 10 MHz, it does not matter a lot where the parallel > resonance is. There will be a wide range of frequencies between the > SRF and where the plane has a low impedance that will have a very high > impedance irrrespective of any resonance. > > Another thing, "high" ESR is good, but not so high that it interferes > with the function of the capacitor. With a 1 ohm ESR it will not be a > very good capacitor at lower frequencies where it is supposed to be > capacitive. > I think you've missed the point I'm trying to make. I'm trying to point out that small planes do not have a bypass resonance problem. 1) With a tiny plane, the resonance between it and the bypass caps is at a very high frequency. 2) At this frequency, the bypass caps have a high ESR. 3) This damps the resonance so much that you don't have a any problem at all. At no point did I say that a 1uF cap had a SRF of 3GHz. (BTW, you're quite correct that it's at about 10MHz) I did mention its ESR at 3GHz to give an example of how the ESR increases with frequency. The frequency we are talking about is the resonant frequency between the plane and the bypass caps. HTH, Syms.Article: 107722
"yy" <yy7d6@yahoo.com.ph> wrote in message news:1157037993.495350.96860@b28g2000cwb.googlegroups.com... > Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with > a SBC (without backplane), the Spec says that IDSEL for the first slot > be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this > mean that i don't need to have an I/O assigned for IDSEL in my FPGA? > and refer to AD32 for IDSEL during configuration transaction? > > BTW, i use Xilinx Spartan 3 fpga. > Thanks. I don't believe AD32 is a specific requirement, just a suggestion. If your FPGA is embedded on the PCI bus and not interfaces to a slot that has a slot IDSEL assigned, then yes, you can hard-wire the IDSEL of your PCI core to the selected AD line either inside your device or through a resister external to the device. It won't matter to your embedded system which approach you use.Article: 107723
"rickman" <gnuarm@gmail.com> wrote in message news:1157047421.453687.256230@e3g2000cwe.googlegroups.com... > John_H wrote: >> "rickman" <gnuarm@gmail.com> wrote in message >> news:1157032693.254923.135250@h48g2000cwc.googlegroups.com... <snip> >> There is a large variety of RF caps specifically used for in-line power >> decoupling that are effective *only* at the high frequencies partly >> because >> that's the only frequency of interest in the RF device. An oscillator at >> 1.5 GHz cares little about what's happening at 200 MHz if that 200 MHz >> noise >> has been filtered out before hitting the effective 1.5 GHz bypassing. > > How do you make a capacitor less effective at low frequencies??? > Wouldn't that be an inductor? All capacitors are less effective at lower frequencies. They don't do much to your kHz signals whereas an inductor can be a dead short at the lower frequencies. It's just that if you use a 10 pf RF capacitor with appropriate multi-GHz leads for stripline design, you won't do a whole lot at 100 MHz but where the circuit is used - the GHz realm - this low-value capacitor can provide excellent RF bypass. >> The truely effective board level decoupling can result in much better >> mixed-signal performance where discretes are connected directly to the >> shared power plane. True RF still seems like a much different animal to >> me >> where grounds really are king (with properly filtered and cascaded power >> distribution is regal as well). > > I don't know about the royal lineage. I do know that digital circuits > are kept quiet with good power decoupling including low impedance > across the spectrum. In this case the only way to filter 1.5 GHz in > the power spectrum is with plane to plane capacitance. Digital circuits are clocked, extremely wideband devices. RF is typically narrowband. Also, the power supplies are typically filtered in stages on the receive side such that the highest level output (IF amplifier out, perhaps) is closest to the "main" rails while the next stage down is filtered from that filtered rail. This goes down until you're at the Low Nois Amplifier attaches to the antenna where the power has passed through several filter stages. If everything was connected to one power/ground sandwich, the circuit would be losing its lunch. No sensitivity at all. About the only way to filter 1.5 GHz for a digital circuit - extremely wideband by nature - is with distributed plane capacitance. I still suggest that RF is a different beast where power planes are no help.Article: 107724
rickman wrote: > I don't want to criticize anyone else's technique since I can't say for > sure what will work and what won't. But analyzing a design on paper > can give you a false sense of security until you simulate it or test > it. Rather than state an opinion, try it! This discussion has gotten so interesting, I think try it is the only thing left. I'd front the few hundred dollars, and some layout time, to take 2-3 designs and lay them out with the Xilinx guidelines, Rick's guidelines, and Symon's Guidelines and do a bake off if somebody would provide the parts. Say 3 pieces of a 6 layer 0.063 FR4 panel that is 16" x 22", would allow for 2 projects that are 7" x 8", or 3 projects that are 5" X 7". Should be fun :)
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