Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
MM wrote:
> What's the advantage of the coding style you demonstrated in this example
> with procedures instead of direct assignments in the process?
Since the template is always the same,
I can write synth code quickly and it
often works the first time.
The template separates the tasks of
initialization, update, and output wiring.
The procedure "update_regs" becomes a distilled
functional description without any
wires or boilerplate spoiling the view.
I can simulate simple variable updates
in my head because the description uses
present values only. There are no signals.
-- Mike Treseler
Article: 106576homoalteraiensis wrote: > Impossible in replaying to the newsthread "ModelSim Designer", I'd like > to place my quastion here: > > Is the a free tool to draw state machine with and handle signals in an > graphical environment? > > I agree to the former article where it has been said, that most design > engineers might not use HDl-Designer, but I found it very convenient > for keep the overwiev in design with a large amonunt of signal > interactions. Xilinx ISE comes with StateCad, which produces truly awful to read HDL, but otherwise works. Since the tool produces straight VHDL/Verilog, you could probably take the output and port it to another target, though the license may prohibit that now that Xilinx owns it.Article: 106577
Austin Lesea wrote: > Nico, > > You posted: > > " > datasheets lack important information on how the IOB are grouped > together and the clock distribution limits resulting from that > grouping > " > > Could you be more specific? What is it that you found to be missing? > Which part? Which package? What 'important information'? We spend > quite a bit of time on the IO specifications, I would like to understand > better what you felt is missing. > > Thank you, > > Austin Well, as a user of these parts, I'll give you a few :) [Relates to all packages I have ever used] 1. What is the maximum ICC of a particular Vcco? This relates directly to block I/O Pd. 2. What *is* the maximum power dissipation of a particular I/O block? I/O blocks are at the edge; as such they have their own power / heat issues. Knowing what the maximums are would help. You could spec max temp, provided you **thoroughly** specified the I/O block so I could calculate it based on speed, incidentally. 3. What is the thermal distribution profile? There is core, and there is I/O. Each has their own effect on the die, but it may well be important to me to know that profile (it has been in the past). 4. What is the thermal profile of the Clock managers? When things get fast, they also get hot. I need to know the power dissipation of a DCM based on inputs and outputs. I am sure others will drop their comments in :) Cheers PeteSArticle: 106578
Not exactly legal vhdl, but close. I don't think you can have a sensitivity list and a wait statement in the same process. Remove the sensitivity list and you're good to go, with the correct declarations. Andy Frank Buss wrote: > Kolja Sulimma wrote: > > > Erik Verhagen wrote: > >> Does anyone knows where I can find an example of an IIR filter in VHDL ? It is incredible, I can't find one on google... > > You should learn how to use Google: > > http://www.google.com/search?q=iir+filetype%3Avhd > > > process(clk) > > begin > > wait until rising_edge(clk); > > output <= (output + input)/2; > > end process; > > Is this synthesizable? > > -- > Frank Buss, fb@frank-buss.de > http://www.frank-buss.de, http://www.it4-systems.deArticle: 106579
PeteS, let me give you a few answers: PeteS wrote: > 1. What is the maximum ICC of a particular Vcco? This relates directly > to block I/O Pd. i suppose you mean the maximum allowed Icc, an absolute max specification. > > 2. What *is* the maximum power dissipation of a particular I/O block? > I/O blocks are at the edge; In Virtex-4 and all future Virtex parts, the I/O is no longer at the periphery > as such they have their own power / heat > issues. Knowing what the maximums are would help. You could spec max > temp, provided you **thoroughly** specified the I/O block so I could > calculate it based on speed, speed, strength, voltage, output loading, dc and capacitive.... > > 3. What is the thermal distribution profile? There is core, and there > is I/O. Each has their own effect on the die, but it may well be > important to me to know that profile (it has been in the past). I personally think that this is a secondary effect, given the thermal properties of silicon. Just my opinion. > > 4. What is the thermal profile of the Clock managers? When things get > fast, they also get hot. I need to know the power dissipation of a DCM > based on inputs and outputs. Same as above. > > I am sure others will drop their comments in :) They are welcome. But let's keep the tone civilized. Peter AlfkeArticle: 106580
So is Xilinx working on another budget-line FPGA? Or are they intending that small V5 chips replace the Spartan line altogether? What's their next budget chip with the new LUT structure and when can I look for it? According to Xilinx's website, the Spartan-3E line is for gate-centric uses and goes up to 1.2M gates. Yeah. Huge. I just finished a project that uses 4.5M gates (so says the MRP) on each of eight 2v6000 chips. It's only using 1/3 the block RAM and none of the MUL blocks on any chip. It only accesses DRAM from one chip. I want that project on cheap hardware. What chips would you recommend for this? By cheap I mean $40/chip, not $2000/chip.Article: 106581
On 2006-08-15, Brannon <brannonking@yahoo.com> wrote: > I just finished a project that uses 4.5M gates (so says the MRP) on > each of eight 2v6000 chips. It's only using 1/3 the block RAM Maybe that's the problem. Can you move any of your storage into block ram and do serial processing? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 106582
Gabor wrote: > Otherwise when > (notice I didn't say "if") your .ise project file becomes unusable > you need to start fresh. I know I'm not the first to complain about having binary project files, so I'm not sure why Xilinx won't *listen* and change it. Not only do you have the above-mentioned problem, but it also means you can't track changes using an external revision control system. And that's a pretty serious problem! At least with Quartus, the entire project configuration is captured in two human-readable text files. And when you're working with multiple configurations of the same project during development, it's a god-send that you can simply diff the project files! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 106583
Ask, and ye shall ... See below, Austin -snip- > 1. What is the maximum ICC of a particular Vcco? This relates directly > to block I/O Pd. What standard? What load? Perhaps you do not have a signal integrity simultion tool? Or Hspice? Since it is YOUR problem, all we can do is provide with the tools to answer it. We provide the IBIS and spice models you need to do this. > 2. What *is* the maximum power dissipation of a particular I/O block? > I/O blocks are at the edge; as such they have their own power / heat > issues. Knowing what the maximums are would help. You could spec max > temp, provided you **thoroughly** specified the I/O block so I could > calculate it based on speed, incidentally. What standard? What load? See answer above. By the way, some devices have IOBs in the interior (all V4 and V5). > 3. What is the thermal distribution profile? There is core, and there > is I/O. Each has their own effect on the die, but it may well be > important to me to know that profile (it has been in the past). Are you concerned about thermal gradient? Don't be: we do that engineering so you do not have to. Worry about maximum power dissipation and Tj. There are estimation tools, and finally, better tools to figure power (XPower) but it requires you to have good simulation vectors (just like you would if you had the same ASIC estimation requirement). > 4. What is the thermal profile of the Clock managers? When things get > fast, they also get hot. I need to know the power dissipation of a DCM > based on inputs and outputs. Nope. You do not. We do the hard part, so you do not have to. If you feel like designing ASICs, go get a job doing that. I am not stopping you. If you want to design FPGAs, submit a resume (we are hiring).Article: 106584
Brannon wrote: > So is Xilinx working on another budget-line FPGA? Or are they intending > that small V5 chips replace the Spartan line altogether? What's their > next budget chip with the new LUT structure and when can I look for it? > > According to Xilinx's website, the Spartan-3E line is for gate-centric > uses and goes up to 1.2M gates. Yeah. Huge. > > I just finished a project that uses 4.5M gates (so says the MRP) on > each of eight 2v6000 chips. It's only using 1/3 the block RAM and none > of the MUL blocks on any chip. It only accesses DRAM from one chip. I > want that project on cheap hardware. What chips would you recommend for > this? By cheap I mean $40/chip, not $2000/chip. Howdy Brannon, What is your target production date? Next week (need to use S3 or V4) or early next year (in which case, you can consider *some* V5's)? I assume that since you are considering V5, you don't have any restrictions on your power rail(s), and they can be made to be relatively clean. Life-span of the product and number of devices needed per year would probably also figure into how much it makes sense to stay in standard FPGA vs. an easy path approach. Lastly, "4.5M gates" doesn't mean much. Is that 55k LUTS? My WAG is that your least expensive alternative is probably an XC3S4000. Good luck, MarcArticle: 106585
Here is a shot at it, See below, Austin -snip- > So is Xilinx working on another budget-line FPGA? Yes. Always. It is "our business." Or are they intending > that small V5 chips replace the Spartan line altogether? No. We sorted that out, the Virtex line is no longer interested in "small" parts. What's their > next budget chip with the new LUT structure and when can I look for it? I can't tell you something like that! One thing you can always count on: Moore's Law. Is 65nm smaller and cheaper? Yes. And 45nm, yes again. And so on. > According to Xilinx's website, the Spartan-3E line is for gate-centric > uses and goes up to 1.2M gates. Yeah. Huge. For some, yes, others not. It is all about marketing. Sell to the ones who have the money. Cost of mask set, etc. How many did you want? > I just finished a project that uses 4.5M gates (so says the MRP) on > each of eight 2v6000 chips. It's only using 1/3 the block RAM and none > of the MUL blocks on any chip. It only accesses DRAM from one chip. I > want that project on cheap hardware. Congratulations on your accomplishment... What chips would you recommend for > this? By cheap I mean $40/chip, not $2000/chip. Well, four 2V6000s is now proabably replaced by 5VLX220. That doesn't include any intelligent re-targeting to structures that are better suited (ie more compact) or design changes to fit it into a smaller device. 5VLX220 will not be "introduced" until later (just keep watch on the announcements). As for less than $40 (for a LX220), well, that doesn't seem likely, even at 65nm. Maybe next time? From the Virtex 1000, to the Spartan 3S1000, the price to the user has diminshed by more than two decades (for the same, or more, logic).Article: 106586
Brannon wrote: > So is Xilinx working on another budget-line FPGA? Or are they intending > that small V5 chips replace the Spartan line altogether? What's their > next budget chip with the new LUT structure and when can I look for it? > > According to Xilinx's website, the Spartan-3E line is for gate-centric > uses and goes up to 1.2M gates. Yeah. Huge. > > I just finished a project that uses 4.5M gates (so says the MRP) on > each of eight 2v6000 chips. It's only using 1/3 the block RAM and none > of the MUL blocks on any chip. It only accesses DRAM from one chip. I > want that project on cheap hardware. What chips would you recommend for > this? By cheap I mean $40/chip, not $2000/chip. Since you do not use MULs and only little BRAM, the V4LX series would make sense - more logic, much fewer specialized (BRAM/DSP) resources and less expensive than their V2 equivalents... but nowhere near $40/chip though. Unless there are specific reasons why you need the 3E, the plain '3' go up to ~5M gates but even that still costs way more than $40/chip: I checked out prices on avnet, XC3S5000-4FG1156C = $390 each.Article: 106587
hi seems like you problems would be solved if only LED manufactures made surface mount LET. = Light Emitting Transistor not impossible, an would only draw a base current much less than collectoer current. would be three pin and more complex production, but would save on possible buffers. the output dive on the fpga is limited by current heating, which is not that high in the off or on states, but high capacitance led would dissipate large Watts in output of fpga. second factor is resistive loss in bond wires, have to be of a certain size to fit so many on the chip. maybe vcc drops on chip due to heat and cannot switch as fast reliably, so try a lower speed operation? pulse the led output at 20% mark to 80% space as you will not notice too much above 100Hz and save power too. use high efficiency led, as i understand they are less than 10% efficient anyhow. wire half the other way with 0 = on instead of 1 = on to distribute power drain between + and - rails. cheers http://indi.joox.net OFSIC in design, at documentation interface stage. then we shall move onto code.Article: 106588
i am in the market for employment. london area, min 500 uk pound per wk. pro rata 40 hrs. parttime prefered, about 20hrs per wk. can only telework if get full time internet, and rented place. c.v. e.g. http://indi.joox.net cheersArticle: 106589
dear all...
i m trying to write c cource code for my SPI connection .
i m done creating cpu architecture in Apex board 20K200 . The problem
is there is no examples for SPI source code provided by altera site.
can anyone give me some help with the source code...
output: 1) through the SPI to shift register with 7-segment
2) produce 0-9 at the 7-segment
Article: 106590Siva Velusamy wrote: > Jeff Cunningham wrote: > >> Has anyone out there had success instantiating chipscope cores in XPS? >> I have a V4FX design that builds with no problem. Then I instantiated >> chipscope_opb_iba and chipscope_icon. Now when I build I get the >> following error: >> >> ERROR:NgdBuild:455 - logical net 'net_gnd0' has multiple driver(s): >> pin G on block XST_GND with type GND >> pin O on block >> chipscope_opb_iba_0/chipscope_opb_iba_0/i_cs_coregen_chipscope_ >> opb_iba_0/cs_coregen_chipscope_opb_iba_0/i_no_d/u_ila/u_dout >> with type LUT3 >> WARNING:NgdBuild:452 - logical net 'chipscope_icon_0/control0<3> has >> not driver >> >> I am new to xps as well as chipscope, so it is probably a newbie >> error. I couldn't find anything in the answers database or usenet >> archive. >> >> revs: >> ise: 8.1.03i >> xps: 8.1.02i >> cs: 8.1.03i >> >> Someone in another thread mentioned "wiring up" the chipscope_icon >> core. How does one do that? All I could figure out how to do was go to >> system assembly bus interface view and connect chipscope_opb_iba to >> the OPB. > > > If you've connected everything properly, the MHS snippet would look > something like this: > > BEGIN chipscope_opb_iba > PARAMETER INSTANCE = chipscope_opb_iba_0 > PARAMETER HW_VER = 1.01.a > PARAMETER C_NUM_DATA_SAMPLES = 1024 > BUS_INTERFACE MON_OPB = mb_opb > PORT chipscope_icon_control = chipscope_opb_iba_0_icon_control > PORT OPB_Clk = sys_clk_s > END > > BEGIN chipscope_icon > PARAMETER INSTANCE = chipscope_icon_0 > PARAMETER HW_VER = 1.01.a > PARAMETER C_NUM_CONTROL_PORTS = 1 > PORT control0 = chipscope_opb_iba_0_icon_control > END > > /Siva Thanks, Siva. I made those changes, and now it builds. Generally speaking, does the user edit the MHS file directly to wire up their system? I've looked at the Platform Specification Format Reference Manual but I'm not clear about what I have to do myself vs. what XPS does automatically. For instance, when I import a peripheral core I made, XPS creates the MPD file. Then I instantiate it with XPS and it puts my peripheral in the MHS file, but the non-bus ports are not shown. Then I guess I should go in and manually edit the MHS peripheral to wire up the external ports. Is that the general idea? -JeffArticle: 106591
In article <1155406545.571316.49480@m79g2000cwm.googlegroups.com>, Antti <Antti.Lukats@xilant.com> wrote: Thanks to Frank Buss, I took another run at Wishbone, and it seems understandable now. > 2) dont even dream of having Or1K uclinux ready system to fit s3e-500 What are people's favorite Wishbone processors on Opencores? Something lightweight (say 16 bits and filling no more than a quarter of the FPGA), but preferably with gcc support. > 3) you can experiment with MicroBlaze uclinux on s3e starterkit board > see link below it has full details and refernece designs and uclinux > images for the microblaze-uclinux for the s3e startkit I have pragmatic reasons for preferring free-as-in-speech and free-as-in-beer code for now. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 106592
> > I just finished a project that uses 4.5M gates (so says the MRP) on > > each of eight 2v6000 chips. It's only using 1/3 the block RAM > > Maybe that's the problem. Can you move any of your storage into block > ram and do serial processing? This project is to outrun serial processors, which it does by doing lots in parallel. It is not doing much in the way of storage. Think software acceleration, not ASIC prototyping.Article: 106593
> What is your target production date? Next week (need to use S3 or V4) > or early next year (in which case, you can consider *some* V5's)? I > assume that since you are considering V5, you don't have any > restrictions on your power rail(s), and they can be made to be > relatively clean. Life-span of the product and number of devices > needed per year would probably also figure into how much it makes sense > to stay in standard FPGA vs. an easy path approach. The boards with 2v6000 chips are already in production. I was thinking of this as a next-gen version of the hardware for somewheres about 8 months from now. > Lastly, "4.5M gates" doesn't mean much. Is that 55k LUTS? It uses 49k LUTS and the same number of FFs. > My WAG is that your least expensive alternative is probably an > XC3S4000. I probably need the 5000, and they are not as cheap as I'd like though significantly cheaper than 2v6000.Article: 106594
> Unless there are specific reasons why you need the 3E, the plain '3' go > up to ~5M gates but even that still costs way more than $40/chip: I > checked out prices on avnet, XC3S5000-4FG1156C = $390 each. The series 3 are .13 micron, true? Is that why they're (debateably) expensive?Article: 106595
Hi Eveyone,
The specifications goes something like this :
The device core asserts reset to the device peripherals asynchronously
and releases (deasserts) the reset synchronously after 4 clock periods
there are two possible implementations for the above spec which one is
better :
signal reset_reg : std_logic_vector(3 downto 0);
p_reset_reg : process(clk,reset_async)
begin
if (reset_async = '0') then
-- on async reset assertion reset the registers
reset_reg <= (others => '0');
elsif (clk'event and clk = '1') then
reset_reg(0) <= '1';
reset_shift_reg : for i in (reset_reg'LOW to reset_reg'HIGH -1) loop
reset_reg(i+1) <= reset_reg(i);
end loop reset_shift_reg;
end if ;
end process p_reset_reg;
-- implementation 1 direct assignment of register value to reset_out
reset_out <= reset_reg(3);
-- implementation 2 assignment of decoded value of the register
-- bank to the reset out only when all the four registers attain
-- '1' then release reset to the device
reset_out <= reset_reg(0) and reset_reg(1) and reset_reg(2) and
reset_reg(3);
"I think the second implementation reduces the problem of metastability
at the reset_out as it is less probable that ll the four flops go
metastable at the same time"
Is the above statement (" I think ... time") valid
awaiting your replies
Article: 106596> I probably need the 5000, and they are not as cheap as I'd like though > significantly cheaper than 2v6000. Well, after looking at the charts again, maybe a 3s4000 would do it. Even the 2000 model is reasonably large. Unfortunately, the Webpack tool doesn't support any of those larger Spartan 3 chips. I had been hoping to find a chip solution that would allow product customers to customize their gateware using Webpack (because it's free for them).Article: 106597
Brannon wrote: >> I probably need the 5000, and they are not as cheap as I'd like though >> significantly cheaper than 2v6000. > > Well, after looking at the charts again, maybe a 3s4000 would do it. > Even the 2000 model is reasonably large. Unfortunately, the Webpack > tool doesn't support any of those larger Spartan 3 chips. I had been > hoping to find a chip solution that would allow product customers to > customize their gateware using Webpack (because it's free for them). Altera's Cyclone II family is fully supported by free tools and the largest (EP2C70) is about 68k LUT, much more than the 3S5000. I don't know how the pricing compare though. TommyArticle: 106598
Jeff Cunningham wrote: > > > Thanks, Siva. I made those changes, and now it builds. Generally > speaking, does the user edit the MHS file directly to wire up their > system? I've looked at the Platform Specification Format Reference > Manual but I'm not clear about what I have to do myself vs. what XPS > does automatically. For instance, when I import a peripheral core I > made, XPS creates the MPD file. Then I instantiate it with XPS and it > puts my peripheral in the MHS file, but the non-bus ports are not shown. > Then I guess I should go in and manually edit the MHS peripheral to wire > up the external ports. Is that the general idea? > > -Jeff Hi Jeff - The answer is that it is upto you. Some people prefer using the GUI, some prefer hand editing the MHS. That said, we are making constant improvements to simplify these sorts of things from the GUI itself. For instance, the upcoming version of EDK (8.2) makes adding Chipscope extremely easy. All you have to do is say you want Chipscope ila/iba and it is instantiated correctly in the MHS. As far as custom peripherals go, if I remember correctly, the GUI only "instantiates" the core. You'd have to go to the ports view and manually make the required ports visible and then connect them appropriately. There are steps being taken to make this easier, but unfortunately it is tedious as of now. -SivaArticle: 106599
Hi -
I don't speak VHDL, so let's see if I've got this right:
You want to create an active-LOW reset signal that is asserted
asynchronously (presumably right after the part configures) and
deasserts synchronous to some clock.
To do this, you created a 4-bit shift register, all of whose bits are
reset LOW by some global asynchronous reset. The D input of the shift
register input is HIGH; when the asynch reset is deasserted, each
successive clock cycle propagates the HIGH to the next stage.
You've proposed two ways of obtaining your active-LOW,
asynch-assert-synch-deassert reset from this shift register:
1) use the Q output of the last shift register FF
or
2) AND the Q outputs of each of the 4 shift register FFs.
You claim that (2) reduces the odds of a metastable propagating to the
reset signal.
I disagree: (2) is no better than (1). Here's why.
Immediately after the deassertion of the asynch reset, only one of the
four shift register FFs can go metastable, namely the first one.
That's the only flip-flop in which the next desired state, HIGH, is
different from the current LOW state; the other 3 FFs have a LOW on
their D inputs. Metastability arises from trying to change a FF's
state with insufficient energy; if there's no possibility of a state
change, there's no metastability. You will not see all four FFs, or
even three or two, go metastable at once.
If the first FF goes metastable, that metastable state could propagate
to the second FF the next clock cycle, but if there's plenty of
settling time between the first and second FFs, the odds are low (I'm
going to skip the issue of just how low). And the odds of propagating
to the third FF are even lower, and so on. Unless you're running this
reset circuit at a very high clock speed or haven't guaranteed lots of
slack between stages, using the output of the fourth FF as a reset
should be fine.
ANDing the four FF outputs buys you nothing. If, against all odds,
the metastable manages to propagate to the output of the last FF,
ANDing that Q with three HIGH signals does nothing to stop the
metastable from propagating through the AND gate. And if the
metastable doesn't make it to the last FF, the AND gate is again
superfluous.
Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com
On 15 Aug 2006 21:24:18 -0700, "arant" <arant.agrawal@gmail.com>
wrote:
>Hi Eveyone,
>
>The specifications goes something like this :
>
>The device core asserts reset to the device peripherals asynchronously
>and releases (deasserts) the reset synchronously after 4 clock periods
>
>there are two possible implementations for the above spec which one is
>better :
>
>signal reset_reg : std_logic_vector(3 downto 0);
>
>p_reset_reg : process(clk,reset_async)
>begin
>if (reset_async = '0') then
> -- on async reset assertion reset the registers
> reset_reg <= (others => '0');
>
>elsif (clk'event and clk = '1') then
>
>reset_reg(0) <= '1';
>
>reset_shift_reg : for i in (reset_reg'LOW to reset_reg'HIGH -1) loop
>reset_reg(i+1) <= reset_reg(i);
>end loop reset_shift_reg;
>
>end if ;
>end process p_reset_reg;
>
>-- implementation 1 direct assignment of register value to reset_out
>
>reset_out <= reset_reg(3);
>
>-- implementation 2 assignment of decoded value of the register
>-- bank to the reset out only when all the four registers attain
>-- '1' then release reset to the device
>
>reset_out <= reset_reg(0) and reset_reg(1) and reset_reg(2) and
>reset_reg(3);
>
>"I think the second implementation reduces the problem of metastability
>at the reset_out as it is less probable that ll the four flops go
>metastable at the same time"
>
>Is the above statement (" I think ... time") valid
>
>awaiting your replies
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z