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frka wrote: > Hi > > I'm making a design in a FPGA for a colour STN LCD. > The display is up and running in the 8 basic colours , RGB. > We would like to achieve 4096 colours by modulating the 3 primary > colour bits over 16 frames (and then use 256 of them). > The display seems to flicker when we tries to LPM modulate. > > > Have any one tried this or have any ideas how to make "gray" scales on > the LCD. > > Best regards, > > Fredrik I've seen a few of these problems and I'll pass on a bit of what I learned. Firstly, are you modulating fast enough. ie is the frame rate high enough. In you case, since you are modulating over 16 frames you'd want a frame rate greater than 320 frames per second. You'll definately see a flicker if it is slower than that. I'm not sure how you are implementing you LPM, but if there is a regular pattern to the pulses, you do occasionally see a flicker. Hmm... this is hard for me to explain, to get a smoother effect from this, you would need to spread the energy more randomly accross the 16 frames. If you need anything clarified, feel free to ask again. So good luck, lycka til!(hope I've spelt that right) Skywings.Article: 109451
Phil Hays wrote: > Make sure that the FFs can fit into the IOB. For Virtex, for example, > the clock and reset are common between the FFs in the IOB. If the input > FF is on clock_foo and the output FF is on clock_blah, then both FFs can > not fit into an IOB. If a reset is generated to the FFs, it must be the > same reset signal for all FFs that are reset, or again the FFs can not be > in the same IOB. Thank you Phil, I wasn't aware about the reset restriction. All registers share the same clock but they didn't have the same reset. I made modifications and now the out and oe registers have no reset at all and the in register has a reset that is connected as clock enable (so not really a reset). Basicaly the SR line of the IOB is unused. Well unfortunately the out and oe registers are still not in the IOB... Could the issue be due to the fact that I'm synthesizing the submodule separately from the top level? PatrickArticle: 109452
"mjackson" <fbs.consulting@gmail.com> schrieb im Newsbeitrag news:1159312624.332238.251680@k70g2000cwa.googlegroups.com... > Hello all, > > Forgive me in advance for the long plea for help. > > Would anyone be kind enough to troubleshoot my implementation of the > EDK 8.1i flow for my production board? > > I have implemented a good deal of my project firmware on the Spartan 3 > evaluation board with great success. However, upon receipt of my 3E > based prototype hardware, I have had nothing but problems successfully > porting my design from evalution hardware to prototype hardware. > > NOTE: On occasion, the firmware will operate as expected on the > prototype board ruling out (hopefully) any board level issues. > > My issues seem to be more related to the EDK flow itself or perhaps my > lack of understanding of aforementioned EDK flow. > > ## Physical Differences ## > The only differences between the prototype hardware and the evaluation > platform wrt the FPGA are as follows: > > (1) 500E vs. 200 > (2) 100MHz LVDS clock vs. 50 MHz > > I have inserted the differential-to-single-ended buffers as per the > Xilinx app note regarding differntial clocks. Use DCM to get clock below 100MHz you should be able to run at some 75MHz or maye 83Mhz but hardly at 100MHz of course the UART baud settings have to match, but I think since 8.2 EDK is able to verify and warn if uart baud is wrong also note that 8.2 may get better timing, but still hardly 100MHz sysclock for S3e AnttiArticle: 109453
Mr Peter, I didnt like your reply: First, all my ideas are interesting since i am related to the field of software enginnering and i ignore the field where you come from! Second, i didnt understand the impolite word "ass-backwards" that you used and i wish that you keep those rude words for yourself and your culture! Third and most importantly, my statements are not arrogant at all! Your reply to me seems that you want to revenge from someone and this is not acceptable! Hope you be more lineant and understanding when replying to people, otherwise your replies are not interesting and will be rejected! Thanks! Peter Alfke wrote: > We may have to teach Mr Solo some basic facts: > First you must have an interesting idea or some valuable specific > knowledge. > Then, and only then, do you start writing an article. > He seems to have this ass-backwards. > Beyond that it might also be wise not to insult this newsgroup with > arrogant statements about the lust for capitalization. > Peter Alfke > ============= > Todd Fleming wrote: > > This gives a whole new meaning to the term "partial reconfiguration" > > > > Todd > > > > jacko wrote: > > > how about single inline fpga which use veroboard spacing, and can be > > > broken off at one pin intervals. > > > > > > place 4 pins in prigrammer for power, clk, and program data, and then > > > break off to length specified by fpga compilier. > > > > > > > > > available in 1m strips maybe. > > > > > > > > > needs comparator for analog input, and as much logic in 1 pin segment > > > as possible. > > > > > > > > > flash on board prefered, with some 4 cycle dram too, for compactness. > > > > > > > > > is this the kind of thing u meant??Article: 109454
Austin Lesea schreef: > Karl, > > Does that mean you will not use Virtex 5? > > Austin Hi Austin, If I was an engineer and would like to know about the how and what, an registration requirement, would make me think twice, yes. Kind regards, Karl.Article: 109455
Hi James,
james7uw@yahoo.ca writes:
<snip>
> The only other thing that I think helped was making my design
> synchronous by registering all data in clocked registers.
That's always a good idea.
> One thing I clued into is that you can't, at least in Xilinx, set a
> signal in two or more different processes, because that results in
> multiple sourcing and unknown ('X') output.
You can't do that physically on-chip for most (all?) "modern" FPGAs.
If two drivers drives different values onto one wire, they will
conflict. 'X' is the simulator's way of telling you that.
However, if all but one of the processes is driving a 'Z', most
synthesisers will create you a bunch of multiplexers such that the one
process that is driving a non-Z value at any time will "win" and the
signal will then take on that value within the FPGA, just like in
simulation.
I usually try and avoid doing this as you can end up with lots of
extra logic that you didn't expect, and debugging what's going on on
chip if more than one process does drive a non-Z value can be a bit of
a pain!
>Also, if something like the following is written,
> which is the correct way to write a register:
>
> MY_PROC : process (clk, rst) is
> begin
> if (rst = '0') then
> a <= '1';
> elsif (clk'event and (clk = '1')) then
> if (b = '0') then
> a <= '1';
> else
> a <= '0';
> end if;
> end if;
> end process MY_PROC;
>
> Whatever is put in for "rst" will be the reset, and if you try to put
> other signals, that you use for something else elsewhere, in the place
> of "rst" in the above, Xilinx will connect them to your input port's
> reset signal and create all sorts of mess.
>
I'm not sure what you mean by this, if you ask for other signals to be
connected to the rst input of the flipflop, then the tools will surely
do as you ask. The fact that this reset is asynchronous may then
cause you grief. If you want to reset a register during "runtime"
rather than just as an initalisation stage, you're much better off
using a synchronous reset:
MY_PROC : process (clk, arst) is
begin
if (arst = '0') then -- async reset
a <= '1';
elsif (clk'event and (clk = '1')) then
if srst = '1' then -- sync reset
a <= '1';
else
-- the rest of the code
end if;
end process MY_PROC;
If you look back over this groups discussions, you'll find lots more
details on the potential pitfalls of asynchronous resets as well...
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 109456Hello, I am considering to use Spartan 3 devices on our new board. Xilinx recommends XCF04S and XCF08P devices for configuration of a Spartan 3 1000. Does anybody know other and cheaper configuration solutions for this FPGA? thanks and best regards, DolphinArticle: 109457
Xilinx webshop related again I am ready to immediatly order ML501, but unfortunatly Xilinx website has only documentation and reference design, and no product code, neither it is available in Xilinx online shop, and search at Avnet yields at zero results also. surprisingly it is listed as orderable here http://hitechglobal.com/catalog/product_info.php? products_id=136&osCsid=f67b9795ed80136c7aef4e96006bca95 at price 1195USD I wonder why isnt ML501 orderable from Xilinx or Avnet, or if it is how to place an order e.g. I need at least a product code - I would really really rather order from Xilinx online shop or Avnet then from somewhere else. AnttiArticle: 109458
Dolphin schrieb: > Hello, > > I am considering to use Spartan 3 devices on our new board. Xilinx > recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > 1000. Does anybody know other and cheaper configuration solutions for > this FPGA? > > thanks and best regards, > Dolphin 6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash connect SPI DO to DIN, CCLK to SPI CLK, and let the micro to shift in read instruction and release prog_b then, s3 will configure in master serial mode. anttiArticle: 109459
>Hey Dave, >Can you be more specific in your advice please? It boils down to one thing.. Speed! ;) Catch is that no fpga manufactor is willing publish specifications. I guess it could be reverse engineered with some effort however. One quick route is to use "meta fpga" in which you implement a fpga ontop of an physical fpga.Article: 109460
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message news:mdjjh29ufai6ikj1045j31vrh9h9726onm@4ax.com... > On 27 Sep 2006 01:46:33 +0200, "Symon" <symon_brewer@hotmail.com> > wrote: > >>i THINK IT SHOULD BE A möBIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED LIKE >>A >>möBIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE YOU TO >>UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. >>hth< YOURS 7TC< sYMSX > > I have already patented this idea, whatever it is. Please refer to > Pat. 23764598, "Eine Kleine Bottle/Nachtmusik." > > Royalty payments are of course welcome. > > Bob Perlman > Cambrian Design Works > Mr. Bob, I didnt like your patent: to me seems that you want to revenge from someone. On examining it, although it seems that you know the expression of letters when addressing in the behavioral life, i noticed that your patent only is covering the clockwise twisted Möbius strip and this is not acceptable! I have now patented the anti-clockwise phenotype (Pat. 89546732) and i ignore the field where you come from! My idea will dominate the culture south of the equator. Hope you be more chiral and understanding when patenting your non-orientable ideas, otherwise your inventions are not interesting and will be rejected! may you tell me how can i post my cv online? Thanks!Article: 109461
Patrick Dubois wrote: > Hello, > > I know that this has been discussed here a few times but I still can't > find a definitive answer so here we go again... > > What is the best way (with Xilinx flow) to ensure that registers are > packed into IOB? In my case I want three registers to be packed into > the IOB for a bidirectionnal signal (in, out and oe). > > The registers in question are buried in a vhdl module two hierchical > levels down. This module is synthesized separately into a ngc file (as > most of my other modules) to create an "incremental" flow. I'm not > using xst own incremental flow however (i.e. I'm not using a xcf file > with -incremental_synthesis flags). > > To make matters a little more difficult, I would really like to keep > the hierarchy as it makes it much easier to debug with Chipscope. > > I read quite a bit about the issue and the standard tricks seem to be: > 1- Use the IOB = "true" constraint in the HDL code for the registers > 2- Use the flag -iob true for xst (redundant with #1) > 3- Use -pr b at the map stage > 4- Duplicate the oe registers and use equivalent_register_removal = > "NO" to prevent xst from optimizing them away > 5- Make sure that the fanout of output registers and fanin of input > registers is 1. > 6- Run map with the option -ignore_keep_hierarchy to flatten the > design. > 7- From Xilinx WP231: When using hierarchy: "Place all I/O components > including any instantiated I/O buffers, registers, DDR circuitry, > SerDes, or delay elements on the top-level of the design. If it is not > possible to place them on the top-level, ensure that they are all > contained within a single hierarchy." > > Now I followed the above tricks except #7. For the moment I'd be happy > even if I don't keep hierarchy. The best I could acheive so far is that > the input registers are in the IOB. The out and oe registers however > are not. > > Now maybe if I followed trick #7, I could make it work but it seems > very ugly to me. I don't want logic on the top level that is related to > a sub module two levels down. Furthermore, using the flag > ignore_keep_hierarchy at the map stage should produce the same result, > shouldn't it? > > Any suggestions? > Your #7 may be the magic key. From the "Virtex4 Synthesis & Simulation Design Guide": > Resources that can be shared should be on the same level of hierarchy. If these resources are > not on the same level of hierarchy, the synthesis tool cannot determine if these resources > should be shared. In some sense, IOB packing is a kind of resource sharing. So the packer probably won't work across hierarchy boundaries.Article: 109462
Peter Alfke schrieb: > You can order Virtex-5 devices from your distributor now, and he will > offer short delivery times. [...] > Peter Alfke, who has been working on and with these parts for over a > year. It doesnt help much if Xilinx is ready for Virtex-5 it matter if the customers are. I have Virtex-5 on the desk already for over weeks, yes shipped by Avnet as normal order and I am looking to buy ML501 board NOW but 1) ML501 doesnt seem to be available from Xilinx or Avnet? 2) Virtex-5 MicroBlaze was supposed to be supported in EDK 8.2 SP2 targetted mid Aug - now looking at Xilinx website the EDK SP2 release date is slipped to mid Oct. mid Oct it may again be slipped to Mid Aug? The reference designs for ML501 are downloadable, but ASFAIK they requires EDK 8.2 SP2 what is not available, so even it may be possible to obtain V5 silicon NOW there support for Virtex-5 just isnt there for the Xilinx customers. And for us who are not Xilinx employees it really doesnt matter how long Xilinx personell has had fun with latest silicon - until both the silicon AND tools are available there is no supprort. So no matter how ready we may be for Virtex-5, and belive me some of us really are - we are not really able todo any real work until tools support is also made available by Xilinx. Antti http://www.microfpga.com FPGA programming without FPGA vendor tools!Article: 109463
<james7uw@yahoo.ca> wrote in message
news:1159314632.757657.275580@i42g2000cwa.googlegroups.com...
> Link to entire thread
> http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/6d594b2ab04beb4b/e39055a323c18cd6#e39055a323c18cd6
>
> Now my post-map sim. is giving me correct results.
Glad to hear that it's working now.
> It is odd that
> improper timing would cause byte mixup like that, but I can certainly
> contemplate types of interconnections that might behave that way.
As with timing problems on a real board, the results you see with a timing
problem using post-tool models are usually 'odd'. It's completely
deterministic (unlike a real board) but it seems odd because of the mapping
from your source into an actual implementation. That mapping, while
producing something that is functionally identical, is generally not what
you would expect. But it works and that mapping is what the tool is
supposed to be good at doing so don't lose sleep over it.
> The
> only other thing that I think helped was making my design synchronous
> by registering all data in clocked registers. One thing I clued into is
> that you can't, at least in Xilinx, set a signal in two or more
> different processes, because that results in multiple sourcing and
> unknown ('X') output.
You can't in any logic (not just Xilinx) have more than one process driving
a signal. Just like on a board two outputs driving the same signal which
can't be done unless the design is such that all but one process is setting
the signal to 'Z'. Obviously this can be useful for data busses (which
would explicitly set the output to 'Z' except when being read from) but for
most other signals this is not the case.
One trick to catching this bug earlier (instead of having to debug to find
that the reason for the 'X' is two processes driving) is to use the type
std_ulogic (and std_ulogic_vector) instead of std_logic and std_ulogic for
all signals except for those that truly do require multiple drivers. What
you'll find if you make this conversion is that the compiler will flag this
as an error for you right up front even before you get into simulation
(assuming that these two processes are in the same entity and physically in
the same file). If the two processes are in totally different entites and
are in separate source files the compiler won't complain when compiling
either file but the moment you invoke the simulator it will complain about
net 'xyz' being driven in more than one place and will generally point you
to the two places....one of which must be wrong. Much easier to fix that
way then having to debug down to why a signal is 'X'. Try it out.
Most people (myself included) grew up using std_logic because that is what
was taught and the switch to something else on something so basic can be
difficult to 'unlearn' but it is worth it. It's also not a big leap. The
type std_logic is actually derived from std_ulogic, they have all the same
values and everything. The only difference is that a std_logic signal is
allowed to have multiple drivers, std_ulogic is not (which is why the
compiler can flag these as errors). The other way to catch the problem is
to allow the synthesis tool to run all the way through. At 'some' point
every tool is going to complain about two drivers on a net where the drivers
are not tri-stated.
> Also, if something like the following is written,
> which is the correct way to write a register:
>
> MY_PROC : process (clk, rst) is
> begin
> if (rst = '0') then
> a <= '1';
> elsif (clk'event and (clk = '1')) then
> if (b = '0') then
> a <= '1';
> else
> a <= '0';
> end if;
> end if;
> end process MY_PROC;
>
> Whatever is put in for "rst" will be the reset, and if you try to put
> other signals, that you use for something else elsewhere, in the place
> of "rst" in the above, Xilinx will connect them to your input port's
> reset signal and create all sorts of mess.
You have to be very careful about using async resets inside an FPGA. I'm
assuming that what you meant by additional signals is something along the
lines of
MY_PROC : process (clk, rst, xx, yy, zz) is
begin
if ((rst or xx or yy or zz) = '0') then
a <= '1';
elsif (clk'event and (clk = '1')) then
.....
The problem you'll find is that when the term 'rst or xx or yy or zz' gets
computed it can glitch because inside an FPGA remember all logic gets
implemented as lookup tables and pass transistors and you can't count on the
output of such an implementation to not have a glitch. That glitch however
will now propogate through your design and reset either all or some
(depending on how big and long the glitch) of the flip flops in your design.
If you use async resets do not deviate from the typical template and
furthermore you need to insure that the 'rst or xx or yy or zz' is the
output of a flip flop (which will not glitch) and also meets timing
requirements. Google or search on this group to find more on resets.
The other safer way is simply do not use the async reset at all and just use
synchronous resets. It will likely make life much easier and there is
almost never any difference in resource usage or anything. The template
then becomes
MY_PROC : process (clk) is
begin
if rising_edge(clk) then -- Using the 'rising_edge' function is much more
descriptive then clk'event and (clk = '1'))
if ((rst or xx or yy or zz) = '0') then
a <= '1';
else
....
KJ
Article: 109464hi i have a quick question: do i have to use lwip_init() for raw_api mode as well or do i have to call all the mem_init() etc. seperatly? when using the raw mode and calling all the init functions as in the xilinx example a call to sys_new_thread() wont start the new thread and it looks likte the function doesn't do anything. could somebody help me out here please? thanks urbanArticle: 109465
Mr. Aoun,
*************
Alexandre Aoun
Computer Engineering Student
Mathaf Adlieh street - Beirut, Lebanon
Born 1983
*************
if you have anything to do with FPGA's or digital design you are
welcome, but you need to know your place
it seems that you've been caught on the wrong foot here, so you have the
chance to back off, read and learn, otherwise you'll become a clown in
this newsgroup.
at the end of the day it's your choice.
Aurash
PS, and please stop imitating Yoda from Star Wars when you post
messages, Syms is at least one order of magnitude better than you ;-)
solo wrote:
>Mr Peter,
>
>I didnt like your reply:
>
>First, all my ideas are interesting since i am related to the field of
>software enginnering and i ignore the field where you come from!
>
>Second, i didnt understand the impolite word "ass-backwards" that you
>used and i wish that you keep those rude words for yourself and your
>culture!
>
>Third and most importantly, my statements are not arrogant at all! Your
>reply to me seems that you want to revenge from someone and this is not
>acceptable!
>
>Hope you be more lineant and understanding when replying to people,
>otherwise your replies are not interesting and will be rejected!
>
>Thanks!
>
>Peter Alfke wrote:
>
>
>>We may have to teach Mr Solo some basic facts:
>>First you must have an interesting idea or some valuable specific
>>knowledge.
>>Then, and only then, do you start writing an article.
>>He seems to have this ass-backwards.
>>Beyond that it might also be wise not to insult this newsgroup with
>>arrogant statements about the lust for capitalization.
>>Peter Alfke
>>=============
>>Todd Fleming wrote:
>>
>>
>>>This gives a whole new meaning to the term "partial reconfiguration"
>>>
>>>Todd
>>>
>>>jacko wrote:
>>>
>>>
>>>>how about single inline fpga which use veroboard spacing, and can be
>>>>broken off at one pin intervals.
>>>>
>>>>place 4 pins in prigrammer for power, clk, and program data, and then
>>>>break off to length specified by fpga compilier.
>>>>
>>>>
>>>>available in 1m strips maybe.
>>>>
>>>>
>>>>needs comparator for analog input, and as much logic in 1 pin segment
>>>>as possible.
>>>>
>>>>
>>>>flash on board prefered, with some 4 cycle dram too, for compactness.
>>>>
>>>>
>>>>is this the kind of thing u meant??
>>>>
>>>>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 109466I have a problem in initiating a PLB _IPIF back to back transactions. I have integrated my IP backend with PLB-IPIF. My IP is User master while initiating transaction and then completes the transaction as slave, on IPIF side. Once I am done with Write transaction initiated on PLB bus from IP Master interface(through IPIF) and after receiving last_ack, I am initiating another write transaction, but its fails to respond! The status after 1st write transaction is that Bus2IP_BE shows 80h and Bus2IP_CE shows IP master chp enable asserted. What does it mean? I found nothing related to this in PLB_IPIF_V2_01.pdf Can anybody help me out in understanding the disconnects?Article: 109467
On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: >Dolphin schrieb: > >> Hello, >> >> I am considering to use Spartan 3 devices on our new board. Xilinx >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 >> 1000. Does anybody know other and cheaper configuration solutions for >> this FPGA? >> >> thanks and best regards, >> Dolphin >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash or 9536XL CPLD if you need more speed, not much more expensiveArticle: 109468
Mike Harrison schrieb: >>>I am considering to use Spartan 3 devices on our new board. Xilinx >>6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > or 9536XL CPLD if you need more speed, not much more expensive Or simply use Spartan3E, which can directly interface to cheap SPI Flash? Regards FalkArticle: 109469
Mike Harrison schrieb: > On 27 Sep 2006 02:03:55 -0700, "Antti" <Antti.Lukats@xilant.com> wrote: > > >Dolphin schrieb: > > > >> Hello, > >> > >> I am considering to use Spartan 3 devices on our new board. Xilinx > >> recommends XCF04S and XCF08P devices for configuration of a Spartan 3 > >> 1000. Does anybody know other and cheaper configuration solutions for > >> this FPGA? > >> > >> thanks and best regards, > >> Dolphin > >6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > or 9536XL CPLD if you need more speed, not much more expensive the speed of the micro is ir-relevant, the FPGA generates the CCLK! thats the beaty, cheapest smallest micro is enough, you only pushin the read command, and let the FPGA todo the rest. the bitstream can embedded CCLK frequency to swithc to higher configuration clock. XC9536 are cheap too, but even in smallest package they are rather large compared to tiny micros in QFN 11 or SOT package AnttiArticle: 109470
Falk Brunner schrieb: > Mike Harrison schrieb: > >>>I am considering to use Spartan 3 devices on our new board. Xilinx > > >>6 (or 8 pin) micro (costs 0.60 USD?) + SPI flash > > > > or 9536XL CPLD if you need more speed, not much more expensive > > Or simply use Spartan3E, which can directly interface to cheap SPI Flash? > > Regards > Falk well the OP wanted S3 so thats not an option, sure S3E, S3A, V5 all support direct SPI config AnttiArticle: 109471
Dang! I knew I should have patented the process of patenting subsets of mathematics! Todd A: Complaining about bottom-up posting in a bottom-up post! Q: What is worse than complaining about bottom-up posting? Symon wrote: > "Bob Perlman" <bobsrefusebin@hotmail.com> wrote in message > news:mdjjh29ufai6ikj1045j31vrh9h9726onm@4ax.com... > > On 27 Sep 2006 01:46:33 +0200, "Symon" <symon_brewer@hotmail.com> > > wrote: > > > >>i THINK IT SHOULD BE A m=F6BIUS STRIP fpga. sPECIFICALLY, A fpga SHAPED= LIKE > >>A > >>m=F6BIUS STRIP. tO BE PRECISE, A TWO DIMENSIONAL kLEIN BOTTLE. i URGE Y= OU TO > >>UPDATE YOUR UNDERSTANDING OF MY CLEAR AND ACCCURATE ADVICE. > >>hth< YOURS 7TC< sYMSX > > > > I have already patented this idea, whatever it is. Please refer to > > Pat. 23764598, "Eine Kleine Bottle/Nachtmusik." > > > > Royalty payments are of course welcome. > > > > Bob Perlman > > Cambrian Design Works > > > Mr. Bob, > > I didnt like your patent: to me seems that you want to revenge from someo= ne. > > On examining it, although it seems that you know the expression of letters > when addressing in the behavioral life, i noticed that your patent only is > covering the clockwise twisted M=F6bius strip and this is not acceptable!= I > have now patented the anti-clockwise phenotype (Pat. 89546732) and i igno= re > the field where you come from! My idea will dominate the culture south of > the equator. > > Hope you be more chiral and understanding when patenting your non-orienta= ble > ideas, otherwise your inventions are not interesting and will be rejected! >=20 > may you tell me how can i post my cv online? >=20 > Thanks!Article: 109472
Antti schrieb: > well the OP wanted S3 so thats not an option, Is it? Says who? I did not hear anything from the OP that prevents the use of a S3E. There are many ways to skin a cat. ;-) Regardas FalkArticle: 109473
solo, I've tried to be tolerant of your excess. I appreciate the fact that you don't cross-post to other newsgroups but beyond that you come across as very annoying, like a bee at a picnic. All your ideas are amazing. To you. Others ideas are not so interesting. To you. Open your mind and your eyes to the people and ideas in this newsgroup and try to "play well with others" while you're here. Think of how you would interact sitting at a table with several engineers. When you lose the respect of those who would otherwise be willing to contribute to your knowledge and help nurture your ideas, you lose. You lost my respect almost immediately when you insisted that you can do whatever the heck you want with all-caps. You chose to continue what you were doing even though it was pointed out that it appeared offensive to others. It went downhill from there. Please, be aware of how your communications might be misperceived by the professionals on this newsgroup. There is more to be gained from and more of this world than you and your ideas. But feel free to learn nothing since continuing on that path will offer very little knowledge from the others who could otherwise add to it. - John_H oh, and - Thanks! solo wrote: > Mr Peter, > > I didnt like your reply: > > First, all my ideas are interesting since i am related to the field of > software enginnering and i ignore the field where you come from! > > Second, i didnt understand the impolite word "ass-backwards" that you > used and i wish that you keep those rude words for yourself and your > culture! > > Third and most importantly, my statements are not arrogant at all! Your > reply to me seems that you want to revenge from someone and this is not > acceptable! > > Hope you be more lineant and understanding when replying to people, > otherwise your replies are not interesting and will be rejected! > > Thanks!Article: 109474
Hi I'm need to implement a simplex linear programming solution in an FPGA/VHDL. The object is to take blocks of data samplse from an ADC and solve a linear cost + linear constraints classical Lin-Prog for each block. my focus of interest is in ultimately doing this in an FPGA/ASIC - not in a processor or group of processors. If you have looked into this before, please let me know what you think! Thanks
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