Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Alessandro wrote: > > I saw this board a couple of weeks ago. Maybe a good choice now that I know > that sdram is simpler to drive than the ddr. That kind of sdram, > furthermore, can be accessed a static ram (slow: 70ns). The whole point of the SDRAM is that it takes a while to set up a read/write operation, but then a word is transfered on every clock. Perfect for a video controller when you want to read the whole line at once. > > Do you think that the typical random access of an 8 bit microprocessor could > take advantage of the "sdram mode" over the 70ns "static ram mode"? I mean, > an average-design sdram controller could get more out of that chip than 70ns > in random rd/wr? The controllers making SDRAM look like SRAM are very inefficient. They take 5-7 clocks for every word read/written. If you read consecutive words, it goes very much faster. I don't quite understand the point in making a ZX Spectrum operate at a high speed - you can't play the games and it's not exactly a perfect platform for doing anything serious enough to require high speed, but this is beyond the point. You can still use BRAM as cache. I suspect with a couple of 16K such blocks most programs will never have a cache miss :) -Alex.Article: 134976
weg22@drexel.edu writes: > Hi all, > > I'm developing a video processing application using a digitial video > camera and a FPGA. In an ideal world, I would interface the camera > directly to the FPGA via an IEEE 1394 interface. I'd still like to > extract the video from the camera using 1394 but I'm trying to avoid > spending the time to develop the IEEE 1394 software interface for the > FPGA. Why 1394? Do you have a specific camera in mind? If not, you could look at Camera Link - that uses standard nat semi deserialisers to present a simple parallel data stream to the FPGA, or the deserialisation can be done in the FPGA fabric. Downside - the cables are a bit on the large and cumbersome side... > > I know TI makes a chipset that converts 1394 to PCI-Express, but I > don't think that will work for an embedded system. I was wondering if > there was some IC out there that converted the IEEE 1394 protocol into > something I already have software for (e.g. USB, EIA 485, etc.)? I > know I'm losing speed, but I can live with that. > Last time I looked to do a firewire camera interface the only embedded chips I could find had vast MOQs :( Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 134977
"Alessandro" <apoppi@email.it> wrote in message news:ga47np$am5$1@aioe.org... > MikeWhy wrote: > >> Also take a look at Digilent's Nexys2 >> http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable. >> $100 USD. Sounds like a good match except the FG320 package, 16 MB >> SDRAM, and Xilinx platform flash. VGA output is 8-bit color only. > > I saw this board a couple of weeks ago. Maybe a good choice now that I > know that sdram is simpler to drive than the ddr. That kind of sdram, > furthermore, can be accessed a static ram (slow: 70ns). > > Do you think that the typical random access of an 8 bit microprocessor > could take advantage of the "sdram mode" over the 70ns "static ram mode"? > I mean, an average-design sdram controller could get more out of that chip > than 70ns in random rd/wr? Actually, I wasn't aware of that; thought it was DDR for some reason. CL3 SDR at 80 MHz does seem a bit challenged, maybe not even viable. I see they publish a Verilog simulation model. Might be interesting to see what speed you can get out of the processor. Do what you can with caching and bursts. Some stalling seems inevitable with any memory architecture. Instruction and data on the same bus, 43 MHz, same cycle r/w? Would be challenging even for DDR2 at 133 MHz, I think. I think I saw 10ns 1Mx8 TSSOP SRAM not very long ago for < $20. A quick look through DigiKey should answer that pretty quickly.Article: 134978
On Sep 8, 6:01=A0pm, Andy <jonesa...@comcast.net> wrote:
> Yes I was looking at Cnt3.
>
> I just tried cnt3 with 24 bits, max =3D 135, using up-counters, with
> both (count + 1 > max) and (count > Max - 1) comparisons, Synplify Pro
> recognized the upper bits as always zero and pruned them. Utilization
> identical to before (8 bits) in both cases.
>
Modifying 'Cnt3' to have 24 bits (code posted below as 'Cnt4'),
Quartus also was able to produce 8 bit counter resource usage, zeroing
out the upper 16 bits. This in spite of the fact that when it chewed
on 'Cnt2' (which simply used 'unsigned' instead of 'natural') with the
same parameters it used up 24 bit counter resources.
Synplify 9.4 targetting a Xilinx V5 was able to catch that the upper
bits are zero for both 'Cnt2' and 'Cnt4' but not for 'Cnt1' (same as
Quartus).
Again, the results confirm my earlier statements:
- Using 'greater than' is better or at least no worse than using
'equals' for setting the roll over point of a counter (Cnt1 results
were always the worst of the bunch).
- Reachability analysis can
* Easily be fooled (Cnt1 again)
* Can be tool dependent (Cnt2 Quartus vs. Cnt2 Synplify).
* Can be depenent on the data representation (Cnt2 Quartus vs. Cnt4
Quartus).
Results for the various runs posted below for everyone's amusement.
Kevin Jennings
------------------------------------------------
-- Targetting a Cyclone II, using Quartus 8.0 Cnt1 synthesizes to:
-- Params Logic elements
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 12
-- Bits=3D24, Max=3D135 33
-- Bits=3D24, Max=3D2**23+135 34
--
-- Targetting a Virtex 5, using Synplify 9.4 Cnt1 synthesizes to:
-- Params LUTs
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 11
-- Bits=3D24, Max=3D135 30
-- Bits=3D24, Max=3D2**23+135 31
------------------------------------------------
------------------------------------------------
-- Targetting a Cyclone II, Cnt2 synthesizes to:
-- Params Logic elements
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 11
-- Bits=3D24, Max=3D135 32
-- Bits=3D24, Max=3D2**23+135 32
--
-- Targetting a Virtex 5, using Synplify 9.4 Cnt2 synthesizes to:
-- Params LUTs
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 10
-- Bits=3D24, Max=3D135 10
-- Bits=3D24, Max=3D2**23+135 5 (+1 DSP48)
------------------------------------------------
------------------------------------------------
-- Targetting a Cyclone II, Cnt3 synthesizes to:
-- Params Logic elements
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Max=3D135 11
-- Max=3D2**23+135 32
--
-- Targetting a Virtex 5, using Synplify 9.4 Cnt3 synthesizes to:
-- Params LUTs
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Max=3D135 10
-- Max=3D2**23+135 5 (+1 DSP48)
------------------------------------------------
------------------------------------------------
-- Targetting a Cyclone II, Cnt4 synthesizes to:
-- Params Logic elements
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 11
-- Bits=3D24, Max=3D135 11
-- Bits=3D24, Max=3D2**23+135 32
--
-- Targetting a Virtex 5, using Synplify 9.4 Cnt1 synthesizes to:
-- Params LUTs
-- =3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D
-- Bits=3D8, Max=3D135 10
-- Bits=3D24, Max=3D135 10
-- Bits=3D24, Max=3D2**23+135 5 (+1 DSP48)
------------------------------------------------
-- Start of Cnt4 code
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Cnt4 is
generic(
Bits: positive :=3D 24;
Max: positive :=3D 2**23+135);
port(
clk: in std_logic;
count: out natural range 0 to 2**Bits - 1);
end Cnt4;
architecture RTL of Cnt4 is
signal count_int: natural range 0 to Max :=3D 0;
begin
process(clk)
begin
if rising_edge(clk) then
if (count_int > (Max - 1)) then
count_int <=3D 0;
else
count_int <=3D count_int + 1;
end if;
end if;
end process;
count <=3D count_int;
end RTL;
-- End of Cnt4 code
Article: 134979On Sep 8, 9:01=A0pm, bgon...@gmail.com wrote: > Hi all, > I=92ve been looking through the Xilinx documentation on RPMs and can > place individual FFs in my Spartan-3 design without any problems but > I=92m having trouble getting Verilog busses to place properly. Here is a > section of my code: > > reg [7:0] =A0 =A0 =A0 count_a; > reg [7:0] =A0 =A0 =A0 count_b; > > // synthesis attribute rloc of count_a[0] is X0Y2; > // synthesis attribute rloc of count_a[1] is X0Y2; > // synthesis attribute rloc of count_a[2] is X0Y3; > // synthesis attribute rloc of count_a[3] is X0Y3; > // synthesis attribute rloc of count_a[4] is X0Y4; > // synthesis attribute rloc of count_a[5] is X0Y4; > // synthesis attribute rloc of count_a[6] is X0Y5; > // synthesis attribute rloc of count_a[7] is X0Y5; > > // synthesis attribute rloc of count_b[0] is X2Y2; > // synthesis attribute rloc of count_b[1] is X2Y2; > // synthesis attribute rloc of count_b[2] is X2Y3; > // synthesis attribute rloc of count_b[3] is X2Y3; > // synthesis attribute rloc of count_b[4] is X2Y4; > // synthesis attribute rloc of count_b[5] is X2Y4; > // synthesis attribute rloc of count_b[6] is X2Y5; > // synthesis attribute rloc of count_b[7] is X2Y5; > > However, when I go to the FPGA Editor, the attributes seem to be > ignored. count_a is lined up correctly, but count_b is completely > scattered randomly over multiple columns. I believe the first set of > RPMs aren=92t even working because count_a will still line up correctly > when I remove the first 8 constraints. > > I=92m wondering if there is anything wrong with the way I am setting up > my RPMs. Does anyone have any ideas? > > Thanks, > Brian In the FPGA editor check to see if the names of the bus elements have changed from your original source name. IIRC the standard bus delimiter used in XST is <> rather than [] as in Verilog. While adding these RLOC constraints in your UCF file would issue an error if the name does not match, those constraints in the Verilog source would simply be ignored if they don't match an instance name.Article: 134980
On Sep 8, 2:50=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Sep 8, 9:44 am, John_H <newsgr...@johnhandwork.com> wrote: > > > > > On Sep 6, 11:06 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > I just spent two hours looking for a package drawing. =A0Still haven'= t > > > found the one I'm looking for. > > > > I did find UG112. =A0On page 117 it has a link for the package > > > drawings. =A0That link is dead. =A0It does have a valid link to the > > > Virtex4 package drawings. =A0Not the ones I was looking for. > > > > I found 'mentor_pcb.pdf'. =A0It says "Go towww.xilinx.comandclick > > > Documentation to find the user guide for your device." =A0The user > > > guides do NOT have package drawings. > > > > I found "AR #11956 - Packaging - Where can I find Xilinx packaging > > > information and package drawings?" - the 1st answer links to (the > > > useless) UG112. =A0The 2nd (last) link is dead. > > > > I went to "Doc Type" -> "Package Specifications". =A0Under "Design > > > Files" all I can find is the "IPC-1752 Form". =A0While a "Material > > > Composition Declaration" is important, it is not what I need to make = a > > > PCB footprint. > > > > Just for fun, I went to a competitors web site. =A0Three clicks from = the > > > home page (Literature -> Packaging -> Device Package) I found "DS- > > > PKG-15.1", which has the footprint data for -all- of their packages i= n > > > one convienent PDF. > > > Does the website show you what you need now? > > I went to Xilinx.com, hit the "Documentation" link at the top of the > > page, selected the Doc Type tab, expanded the Package Specifications > > item and found 33 links catagorized into 5 sections. =A0The "See all > > Package Specifications" link at the top of this expanded section > > provides a very long list of packages. > > > Were these links not there on Saturday? > > > - John_H > > I couldn't find them on Saturday. =A0I remember seeing the IPC-1752 > Forms, but do -not- remember seeing the links for package drawings. > > On Saturday when I did a site-search for 'CP132', I got 2 hits. =A0Today > I got 80. > > The link in UG112 is still dead though. =A0(Comment to Xilinx: =A0Killing > off links that are printed in published documentation is a bad thing.) > > But thanks to you-all, I have found the data I need. =A0(Comment to > Gabor: =A0It was the PDF's that I was looking for.) Yeah, well you're not the only one having trouble finding the package specs. Most sane people would assume that the package drawings would either be included in the part data sheets, or at least linked to the product page (the one with links to all the data sheets and user guides). It seems non-intuitive that after you have found the product documents for everything else in one place on the website, you would have to again navigate from the top level under "documents" to find another portion of the necessary data. Just my 2 cents, GaborArticle: 134981
1394 is a sophisticated bus and as far as I know there are no ICs available that would bridge it to any other serial bus. You need a physical layer and a link layer chips to build a 1394 interface. There are combined chips, but they are probably not what you want. All of the combined chips I know of are so called host controllers designed to go into a PC or similar and for that reason they exploit a PCI or PCIe bus. They conform to OHCI spec, which hides from the software most of the 1394 complexities and allows for software interface standartization. For embedded applications there are a few 1394 LLCs (Link Layer Controllers), which connect through a bus such as e.g. ColdFire. So, it would be easy to connect it to a FPGA. However, remember that you will need to implement a CPU of some sort in the FPGA to support the LLC functionality and most importantly that you will need to write/port/debug quite a bit of non-trivial low level software. LLC can be also implemented in a FPGA, but there are no free cores available AFAIK. /Mikhail <weg22@drexel.edu> wrote in message news:05d731b4-14b0-490d-bc16-51cdedf13c5a@k36g2000pri.googlegroups.com... > Hi all, > > I'm developing a video processing application using a digitial video > camera and a FPGA. In an ideal world, I would interface the camera > directly to the FPGA via an IEEE 1394 interface. I'd still like to > extract the video from the camera using 1394 but I'm trying to avoid > spending the time to develop the IEEE 1394 software interface for the > FPGA. > > I know TI makes a chipset that converts 1394 to PCI-Express, but I > don't think that will work for an embedded system. I was wondering if > there was some IC out there that converted the IEEE 1394 protocol into > something I already have software for (e.g. USB, EIA 485, etc.)? I > know I'm losing speed, but I can live with that. > > Thanks in advance, > weg22Article: 134982
On Sep 9, 9:36=A0am, Gabor <ga...@alacron.com> wrote: > On Sep 8, 2:50=A0pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > On Sep 8, 9:44 am, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Sep 6, 11:06 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > I just spent two hours looking for a package drawing. =A0Still have= n't > > > > found the one I'm looking for. > > > > > I did find UG112. =A0On page 117 it has a link for the package > > > > drawings. =A0That link is dead. =A0It does have a valid link to the > > > > Virtex4 package drawings. =A0Not the ones I was looking for. > > > > > I found 'mentor_pcb.pdf'. =A0It says "Go towww.xilinx.comandclick > > > > Documentation to find the user guide for your device." =A0The user > > > > guides do NOT have package drawings. > > > > > I found "AR #11956 - Packaging - Where can I find Xilinx packaging > > > > information and package drawings?" - the 1st answer links to (the > > > > useless) UG112. =A0The 2nd (last) link is dead. > > > > > I went to "Doc Type" -> "Package Specifications". =A0Under "Design > > > > Files" all I can find is the "IPC-1752 Form". =A0While a "Material > > > > Composition Declaration" is important, it is not what I need to mak= e a > > > > PCB footprint. > > > > > Just for fun, I went to a competitors web site. =A0Three clicks fro= m the > > > > home page (Literature -> Packaging -> Device Package) I found "DS- > > > > PKG-15.1", which has the footprint data for -all- of their packages= in > > > > one convienent PDF. > > > > Does the website show you what you need now? > > > I went to Xilinx.com, hit the "Documentation" link at the top of the > > > page, selected the Doc Type tab, expanded the Package Specifications > > > item and found 33 links catagorized into 5 sections. =A0The "See all > > > Package Specifications" link at the top of this expanded section > > > provides a very long list of packages. > > > > Were these links not there on Saturday? > > > > - John_H > > > I couldn't find them on Saturday. =A0I remember seeing the IPC-1752 > > Forms, but do -not- remember seeing the links for package drawings. > > > On Saturday when I did a site-search for 'CP132', I got 2 hits. =A0Toda= y > > I got 80. > > > The link in UG112 is still dead though. =A0(Comment to Xilinx: =A0Killi= ng > > off links that are printed in published documentation is a bad thing.) > > > But thanks to you-all, I have found the data I need. =A0(Comment to > > Gabor: =A0It was the PDF's that I was looking for.) > > Yeah, well you're not the only one having trouble finding the > package specs. =A0Most sane people would assume that the > package drawings would either be included in the part data > sheets, or at least linked to the product page (the one with > links to all the data sheets and user guides). =A0It seems > non-intuitive that after you have found the product documents > for everything else in one place on the website, you would > have to again navigate from the top level under "documents" > to find another portion of the necessary data. > > Just my 2 cents, > Gabor This is a problem at many company's web sites. Some of the Asian sites are just incredibly arcane. I have even seen some passive manufacturer's web sites that don't have data sheets, they provide separate documents for different types of data on their parts. So you might have to download a PDF, a couple of GIFs and some other files to get a complete data sheet! Then there are the sites that just plain hide their products from you unless you already know what you want and have a part number... Xilinx may make their package data sheets and others hard to find, but they are not the *worst* of this category. RickArticle: 134983
On Sep 9, 6:36=A0am, Gabor <ga...@alacron.com> wrote: > On Sep 8, 2:50=A0pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > > > On Sep 8, 9:44 am, John_H <newsgr...@johnhandwork.com> wrote: > > > > On Sep 6, 11:06 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > I just spent two hours looking for a package drawing. =A0Still have= n't > > > > found the one I'm looking for. > > > > > I did find UG112. =A0On page 117 it has a link for the package > > > > drawings. =A0That link is dead. =A0It does have a valid link to the > > > > Virtex4 package drawings. =A0Not the ones I was looking for. > > > > > I found 'mentor_pcb.pdf'. =A0It says "Go towww.xilinx.comandclick > > > > Documentation to find the user guide for your device." =A0The user > > > > guides do NOT have package drawings. > > > > > I found "AR #11956 - Packaging - Where can I find Xilinx packaging > > > > information and package drawings?" - the 1st answer links to (the > > > > useless) UG112. =A0The 2nd (last) link is dead. > > > > > I went to "Doc Type" -> "Package Specifications". =A0Under "Design > > > > Files" all I can find is the "IPC-1752 Form". =A0While a "Material > > > > Composition Declaration" is important, it is not what I need to mak= e a > > > > PCB footprint. > > > > > Just for fun, I went to a competitors web site. =A0Three clicks fro= m the > > > > home page (Literature -> Packaging -> Device Package) I found "DS- > > > > PKG-15.1", which has the footprint data for -all- of their packages= in > > > > one convienent PDF. > > > > Does the website show you what you need now? > > > I went to Xilinx.com, hit the "Documentation" link at the top of the > > > page, selected the Doc Type tab, expanded the Package Specifications > > > item and found 33 links catagorized into 5 sections. =A0The "See all > > > Package Specifications" link at the top of this expanded section > > > provides a very long list of packages. > > > > Were these links not there on Saturday? > > > > - John_H > > > I couldn't find them on Saturday. =A0I remember seeing the IPC-1752 > > Forms, but do -not- remember seeing the links for package drawings. > > > On Saturday when I did a site-search for 'CP132', I got 2 hits. =A0Toda= y > > I got 80. > > > The link in UG112 is still dead though. =A0(Comment to Xilinx: =A0Killi= ng > > off links that are printed in published documentation is a bad thing.) > > > But thanks to you-all, I have found the data I need. =A0(Comment to > > Gabor: =A0It was the PDF's that I was looking for.) > > Yeah, well you're not the only one having trouble finding the > package specs. =A0Most sane people would assume that the > package drawings would either be included in the part data > sheets, or at least linked to the product page (the one with > links to all the data sheets and user guides). =A0It seems > non-intuitive that after you have found the product documents > for everything else in one place on the website, you would > have to again navigate from the top level under "documents" > to find another portion of the necessary data. > > Just my 2 cents, > Gabor- Hide quoted text - > > - Show quoted text - What items should be included on every part data sheet for sane people? BSDL files IBIS models Package drawings PROM information Thermal information Reliability data Process guidelinesArticle: 134984
Simply move the assignment of doa and dob outside of the ena/enb
qualification. See below.
always @ (posedge clk)
begin
if (ena)
begin
if (wea)
mem[addra] <= dia;
end
doa <= mem[addra];
end
always @ (posedge clk)
begin
if (enb)
begin
if (web)
mem[addrb] <= dib;
end
dob <= mem[addrb];
end
Article: 134985The FPGA editor does list each element with the <> instead of the []. I had wondered about that myself and tried using the other symbols (i.e. count_a<0>) but with no success. Has anyone been successful doing RPM with busses and have an example of the correct syntax? BrianArticle: 134986
On Sep 6, 9:53=A0pm, LittleAlex <alex.lo...@email.com> wrote: > On Sep 6, 9:12=A0am, Paul Urbanus <urbpub...@hotmail.com> wrote: > > > > > Is there any reason I shouldn't compile the altera synthesis attributes > > into my modelsim altera library. > > > Urb > > No. =A0Just do it. The altera_syn_attributes package is included in the ModelSim AE precompiled libraries starting with version 8.0, so you should no longer have to compile the package manually when you upgrade to the latest release.Article: 134987
On Sep 9, 12:18=A0pm, dand2k <d...@oz.net> wrote: > Simply move the assignment of doa and dob outside of the ena/enb > qualification. See below. > > always @ (posedge clk) > =A0begin > =A0 if (ena) > =A0 begin > =A0 =A0if (wea) > =A0 =A0 mem[addra] <=3D dia; > =A0 end > =A0 doa <=3D mem[addra]; > =A0end > > always @ (posedge clk) > =A0begin > =A0 if (enb) > =A0 begin > =A0 =A0if (web) > =A0 =A0 mem[addrb] <=3D dib; > =A0 =A0end > =A0 dob <=3D mem[addrb]; > =A0end Why is the RAM split into two processes? Wouldn't it be more correct to use one process since it is all using the same clock? Otherwise you have a problem with simulation when both processes write to the same location in RAM. I don't know what the real hardware does in that case, but by using separate processes, you are leaving it up to the whims of the simulator to decide which happens first and last. If you put them in the same process the condition can be trapped and handled. RickArticle: 134988
james wrote: > Add $20 tothe base price and you get a XC3S1200 instead of the XC3S500 > onthe NEXYS 2 board. Then you will have more than enough room for a > dual port SDRAM controller. I would still believe that the ZX would > fit well into the XC3S500 with a dualport SDRAM controller. I took a look at the micron psdram's datasheet; I suppose a dualport sdram controller is a piece of logic that translates an asynchronous access (microprocessor side) to a synchronous one (ram side). You're not talking about using the blockram as a dualport cache, are you? Ciao!Article: 134989
Alex Freed wrote: > The whole point of the SDRAM is that it takes a while to set up > a read/write operation, but then a word is transfered on every clock. > Perfect for a video controller when you want to read the whole line > at once. I see. > I don't quite understand the point in making a ZX Spectrum operate at > a high speed - you can't play the games and it's not exactly a perfect > platform for doing anything serious enough to require high speed, > but this is beyond the point. You can still use BRAM as cache. I > suspect with a couple of 16K such blocks most programs will never > have a cache miss :) :-) Now I've got the point. If I could have 64KB of bram, then the problem would be solved at least for "normal" use. Unfortunately this amount is only available on the 1600K gates chip. The reason for having a 21MHz zx-spectrum is, for example, ResiDOS which runs pretty fine on my cpld-based version of the clone, now being ported to fpga. Anyway, yes... maybe I can slow it down a little. The other point was having not to deal with some complex and/or critical technology (and difficult packages) so that an hobbyst could assemble it's own machine, so a PQ208 and a static ram seemed nice. Ciao! AlessandroArticle: 134990
MikeWhy wrote: > Actually, I wasn't aware of that; thought it was DDR for some reason. > CL3 SDR at 80 MHz does seem a bit challenged, maybe not even viable. > I see they publish a Verilog simulation model. Might be interesting > to see what speed you can get out of the processor. Do what you can > with caching and bursts. Some stalling seems inevitable with any > memory architecture. ...but I see there is a 'busy' line which could be fed to the micro and halt it sometimes (if not too frequent). It seems it could happen in case of refresh and access collision (from the psdram installed on the nexys2 datasheet). > Instruction and data on the same bus, 43 MHz, same cycle r/w? Would be > challenging even for DDR2 at 133 MHz, I think. Not so tight. On the current version of the T80 code, only the opcode fetch needs a pretty fast response from memory. Having to accomodate both the memory access and memory refresh cycles (Z80 does that), mreq and rd or wr only lasts for one T-state (one clock cycle). I think there is a way to disable the memory refresh cycle (which is simply a waste of time) but this will require some bugfix to the core itself (in the first version I downloaded from opencores, there is a bug which turns it into a super-Z80 with one cycle memory and I/O access and there is no way to slow it down). One of the project maintainers provided the solution already used on www.fpgaarcade.com for the pacman project (an alternate wrapper). Now timings are ok, except for the opcode fetch which on a real Z80 takes almost 2,5T-states in place of 1. Take a look at this waveforms, captured on real hardware (my xilinx 3E evaboard) while the processor of the zx-badaloc (T80) was performing an OUT ($FE),A with A = 7 (from the zx-spectrum rom, power-on initialization, border color setup): http://www.zxbada.bbk.org/out_fe-07.gif Clock speed here is 3,5MHz (as on original sinclair hardware). Due to lack of pins on the hirose connector, address bus is only two bits wide and there is no input databus to the processor (only output is shown) but it's enough to understand what's going on. Between markers A and B you can see the OUT instruction opcode fetch, which takes 4T-states (as original Z80). The difference is that mreq and rd are active for just one T-state in place of 2,5. At 21Mhz, this means that the memory should place valid data within about 35/40ns. The reminder of the cycle is the refresh cycle. Then, the operand for the out instruction is read from the next memory location, showing a standard memory read access (markers B and C). This should (and does) take 3 T-states. Mreq and rd are active for 2T-states, so far easier for the memory to comply. Markers C and D show the instruction execution. Since A holds 07, this value is placed on the output databus while iorq + wr goes active. It should be noted the advantage of having separate input and output databuses: data is held on the OUT databus after instruction completion, giving the device enough time to recognize the deactivation of iorq+wr, while the next instruction is being fetched from the IN side of the databus. Here I suppose there is a little bug in T80, since an I/O access should last 4 T-states in place of the three shown here, as Z80 places an extra wait state. > I think I saw 10ns 1Mx8 TSSOP SRAM not very long ago for < $20. A > quick look through DigiKey should answer that pretty quickly. I think I may go on both sides. I think I will find a PQ208 board and add a static ram, but I'd also like to experiment with the psdram on the nexys2. I will probably be seeking for both. Ciao! AlessandroArticle: 134991
thutt wrote: > All the I/O is actually constrained, but I have not done anything with > timing yet. I guess I'll try to check out information about timing. > Thanks for the info. Hopefully this will pan out. I totally agree with what Sean said. I recently ran into *exactly* the same type of problem, on a project based on the "small" 100K gates 3E fpga. Just assigning a signal or not to an output spare pin for debug purposes had the power to make the entire design totally inusable. The SPI port communicating to an external device used to crash within a few seconds after power-on. I've been instructed to add a "timing constraint" and now is seems (it seems!) that the design is more stable and changing that assignment no longer affects reliability. This is what I've added: NET clk_pin TNM_NET = clk_ref_grp; TIMESPEC TS01 = PERIOD : clk_ref_grp : 20.00 : PRIORITY 1; # 50.00 MHz This was for the main 50MHz clock. "clk_pin" is the name of the net where the 50MHz osc is attached. This did not bring any improvement. But when I added another constraint, to the signal output from DCM (75MHz) then the problem disappeared: NET clk_pll TNM_NET = clk_ref_grp_pll; TIMESPEC TS01 = PERIOD : clk_ref_grp_pll : 12.00 : PRIORITY 1; # 75.00 MHz I also added this: TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns; TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns; because it was included on a xilinx 3E-board example. I don't know if is useful or not. Ciao! Alessandro > > thuttArticle: 134992
Hello everyone. I try to implement an image processing in Virtex5. But What I have now is ISE7.1i. I think that it's not working for Virtex5. So is there anyone who can tell me what version of ISE is ok with Virtex5 Thank you for reading.Article: 134993
Alessandro wrote: > > :-) Now I've got the point. If I could have 64KB of bram, then the problem > would be solved at least for "normal" use. Unfortunately this amount is only > available on the 1600K gates chip. The reason for having a 21MHz zx-spectrum > is, for example, ResiDOS which runs pretty fine on my cpld-based version of > the clone, now being ported to fpga. Let's see. The real Spectrum (used to) run at 3.5 MHz CPU clock, so one cycle is ~286 ns. Z80 never uses 2 consecutive clocks for data access, so SOME memory could operate at full speed. Now the memory shared with video had to use wait states. Actually as I recall the clock "stopped" for a while. Anyway many programs tried to put code that needed fast execution into the non-contended area. You want to use 21 MHz clock. 47 ns. Considering at least 2 cycles for a CPU access, 70 ns PSDRAM should work fine. Use BRAM for video memory- you only need 32K. I have my own FPGA based Spectrum clone, that's why this info is relatively fresh in my memory. See http://mirrow.com/FPGApple/revisited.html Full source is there too. Built for Altera DE1 board, but all portable Verilog. > > Anyway, yes... maybe I can slow it down a little. The other point was having > not to deal with some complex and/or critical technology (and difficult > packages) so that an hobbyst could assemble it's own machine, so a PQ208 and > a static ram seemed nice. I'm kind of a professional, but I'd rather not try to solder PQ208 chips. Last time I tried an 80 pin 0.5 mm pitch one I failed miserably. Obviously other people have better skills at this, but IMHO for the majority using an inexpensive off-the-shelf board would be a huge benefit. > > Ciao! > Alessandro > >Article: 134994
Hi I am using a pci core(generated from coregen, with version v4.3) in my design. Till now i was succesfully implementing in ISE9.1i. I started to migrate my design to ISE10.1i and I am receiving IDELAYCTRL locking problems (Xilinx changed locking approach in ISE10.1i). Here's one solution they are pointing to.. http://www.xilinx.com/support/answers/30966.htm The error is as below.. ---------------------------------- ERROR:Place:1064 - The delay controller "PCI_CORE/XPCI_IDC0" has been locked with the following location constraint:COMP "PCI_CORE/XPCI_IDC0" LOCATE = SITE "IDELAYCTRL_X0Y2" LEVEL 1 However, none of the delay elements calibrated by this controller are being used. The delay controller should be removed from the design. Please correct your design and rerun. For more details, please search the Xilinx Answers Database at http://www.xilinx.com/support/answers/index.htm. ----------------------------------- As the errors says "none of the delay elements calibrated by this controller are being used" -- I don't understand this. I use synplify and checked the synthesized netlist(rtl view and technology view) and I see IODELAY blocks instantiated. Any help is appreciated. Thanks PabloArticle: 134995
I believe you need ISE 10.x JTW "KJ" <lkjrsy@gmail.com> wrote in message news:f73e6e31-f0fe-4136-9651-fa2af6e1b75d@b2g2000prf.googlegroups.com... > Hello everyone. > > I try to implement an image processing in Virtex5. But What I have now > is ISE7.1i. > I think that it's not working for Virtex5. So is there anyone who can > tell me what version of ISE is ok with Virtex5 > > Thank you for reading.Article: 134996
"Alessandro" <apoppi@email.it> writes: > thutt wrote: > > > All the I/O is actually constrained, but I have not done anything with > > timing yet. I guess I'll try to check out information about timing. > > Thanks for the info. Hopefully this will pan out. > > I totally agree with what Sean said. > > I recently ran into *exactly* the same type of problem, on a project based > on the "small" 100K gates 3E fpga. > > Just assigning a signal or not to an output spare pin for debug purposes had > the power to make the entire design totally inusable. The SPI port > communicating to an external device used to crash within a few seconds after > power-on. > > I've been instructed to add a "timing constraint" and now is seems (it > seems!) that the design is more stable and changing that assignment no > longer affects reliability. This is what I've added: > > NET clk_pin TNM_NET = clk_ref_grp; > TIMESPEC TS01 = PERIOD : clk_ref_grp : 20.00 : PRIORITY 1; # 50.00 MHz It turned out that my problem was due to my own stupidity in trying to delay a clock signal; I do a bit of work before I want the CPU 'turned on', so I was delaying the clock signal to the CPU until a state machine reached a certain state. Bad idea. (Hey, I'm a software person learning hardware....) I should've just used the system clock and added an 'enable' to the CPU. In fact, that's what I did and that timeing error went away. I'm quite curious about your timing constraint information. I spent time on the weekend trying to find out how to do that, but the Xilinx docs, IMHO, are just as bad as their software -- and I couldn't find anything useful. Where did you find this information about 'NET clk_pin'? To what do you add it? In the VHDL? In the user constraints? I try to avoid using ISE as much as possible, so please tell me what document you found this information in, and then I think I can extrapolate to how to control the command line programs (which I drive from a Makefile). > > This was for the main 50MHz clock. "clk_pin" is the name of the net where > the 50MHz osc is attached. This did not bring any improvement. But when I > added another constraint, to the signal output from DCM (75MHz) then the > problem disappeared: 75MHz? On a Spartan 3E board? What pin is that? Do you have the UCF name? <snip> thuttArticle: 134997
thutt wrote: > All the I/O is actually constrained, but I have not done anything with > timing yet. I guess I'll try to check out information about timing. > Thanks for the info. Hopefully this will pan out. If you have not created timing constraints and checked that they are met with the static timing analysis tools, then the design can be broken in all possible ways. Getting the timing correct is usually a big task of the design, might be much bigger than coding the design. And the timing closure phase usually requires loops back to the RTL and code changes to meet the timing. Timing is the biggest difference to software in HW, timing phase is the phase where SW guys notice that everything that you code can not be realized in HW in a sane way. --KimArticle: 134998
Hi all.... Can Soft microprocessor like microblaze, nios replace DSP processors...? Or is there any soft DSP processor...? ThanksArticle: 134999
Hi Pablo, Im no expert but I think you may confuse the IODELAY and IDELAYCTRL. IODEALY are located in each IOB and can be used to delay in or out signals. The IDELAYCTRLis another block that calibrates the IODELAYs in its IO bank. At least that is how I understand it. The error message you get says that there are no IODELAYs instantiated in the region/IObank where the IDELAYCTRL is LOC'ed. HTH
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z