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On Sep 7, 4:07=A0am, Bob Smith <use...@linuxtoys.org> wrote: > LittleAlex wrote: > > I went to "Doc Type" -> "Package Specifications". =A0Under "Design > > Files" all I can find is the "IPC-1752 Form". =A0While a "Material > > Composition Declaration" is important, it is not what I need to make a > > PCB footprint. > > It has been awhile but I found something on .... > > http://www.xilinx.com/support/documentation/package_specifications.htm > > While there are a huge number of links, the packages > seem to be sorted from largest to smallest. > > hope this helps > Bob Smith I don't think Xilinx offers CAD-ready footprints. You need to use the .pdf documentation to create your own if your CAD supplier doesn't have the package in its libraries. By the way, when I view that page I see packages in alphanumeric order starting with BF and ending in VQG packages. There was a time when all of the packages were in a single .pdf document, but I guess that got too big, and most people only use a fraction of the package types. Regards, GaborArticle: 134951
On Sep 8, 8:00=A0am, michael...@gmx.de (Michael Dreschmann) wrote: > Hi! > > I'm doing a layout for an xc4vfx20 Virtex4. In the pinout datasheet on > page 249 (figure 3-7) there are some pins described as "no connect". > May I connect them to anyting or mustn't I connect them? In the first > case I could use them to route signals to pads more in the center of > the BGA. > > Thanks, > =A0Michael If you go down 1 page, you'll see these pins are connected on the fx40. So you could use the pads to route through, but then if you ever needed to use a larger part you would have some undesired connections (possibly) on these pads. Generally for Xilinx parts, non-connects are in fact not connected to the die. They are also normally only on pins that would be I/O's (general purpose or RocketIO depending on the family) for a larger part in the same package. All power and ground pins are usually connected to the package for even the smallest parts. Normally I would not do what you are suggesting, although you can still buy a little bit of routing room by not adding the dogbone break-out to the unused pads. If you know you'll never need a larger part, or if so are willing to re-spin the board layout, I don't see a problem with it, though.Article: 134952
Hi all, I'm developing a video processing application using a digitial video camera and a FPGA. In an ideal world, I would interface the camera directly to the FPGA via an IEEE 1394 interface. I'd still like to extract the video from the camera using 1394 but I'm trying to avoid spending the time to develop the IEEE 1394 software interface for the FPGA. I know TI makes a chipset that converts 1394 to PCI-Express, but I don't think that will work for an embedded system. I was wondering if there was some IC out there that converted the IEEE 1394 protocol into something I already have software for (e.g. USB, EIA 485, etc.)? I know I'm losing speed, but I can live with that. Thanks in advance, weg22Article: 134953
On Sep 8, 7:14=A0am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Sun, 7 Sep 2008 23:10:31 -0700 (PDT), knight <krshe...@gmail.com> > wrote: > > >hi > > >Can anyone tell me how can i multiply two signed numbers in FPGA. > >How the logic is really implemented.. > >ie., if i multiply two signed numbers are they multiplying the > >positive number and the 2's complement (if the number is negative) > >directly ..? > >Or are they really changing the negative number to positive and do > >normal multiplication and appends the sign accordingly..? > >And is the positive number, and its 2's complement form same always...? > > If they are small enough, i.e. < 18*18 bits, or 18*25 bits in Virtex-5) > for most FPGAs you just use the * operator and expect the tools to use > the in-built multipliers. > > For more details, read the documentation on these multiplier or DSP48 > blocks. > > For larger operators, this works well enough as long as you don't need > the highest achevable speeds (maybe this is fixed in ISE 10?). > > But if you are "rolling your own" multiplier (perhaps to get a properly > pipelined 32*32 multiplier for speed, using the internal components) the > easiest way is to convert to unsigned numbers, and handle the sign bits > separately. I wouldn't agree with that last suggestion. This takes extra logic in the data path to complement the numbers, both on input and output. The Booths algorithm can multiply signed inputs and works as well as unsigned multiplies. RickArticle: 134954
On Sep 8, 7:35=A0am, Jon Beniston <j...@beniston.com> wrote: > On 8 Sep, 07:10, knight <krshe...@gmail.com> wrote: > > > hi > > > Can anyone tell me how can i multiply two signed numbers in FPGA. > > How the logic is really implemented.. > > ie., if i multiply two signed numbers are they multiplying the > > positive number and the 2's complement (if the number is negative) > > directly ..? > > Or are they really changing the negative number to positive and do > > normal multiplication and appends the sign accordingly..? > > And is the positive number, and its 2's complement form same always...? > > How many bits of the result do you need? If you only need the same > number of output bits as input, I don't think it matters whether the > numbers are signed or unsigned. > > Jon Well. . . Most people want the most significant portion of the result, even if they only need the same number of bits output as input. So although the low 8 bits of 8 x 8 signed multiply and 8 x 8 unsigned multiply are the same, the high 8 bits are certainly not the same. For example if you have hex FF (255 unsigned or -1 signed) the output of the unsigned multiplier will be hex FE01, while the output of the signed multiplier will be 0001. Regards, GaborArticle: 134955
> Most people want the most significant portion of the result, even if > they only need the same number of bits output as input. I'm not sure I agree with that. Maybe if you're doing fractional arithmetic, but not for integer. >=A0So although the > low 8 bits of 8 x 8 signed multiply and 8 x 8 unsigned multiply are > the > same, the high 8 bits are certainly not the same. =A0For example if you > have hex FF (255 unsigned or -1 signed) the output of the unsigned > multiplier will be hex FE01, while the output of the signed multiplier > will be 0001. True - what I said is only valid if you're only interested in the lower bits. So just make sure you first sign extend to the number of bits you want if you take this approach. JonArticle: 134956
Alessandro <apoppi@email.it> wrote: >16K rom image from spi flash address $10000 (1MB offset). If a spectrum 16K >rom was programmed there, then you had a VGA-PS/2 keyboard 16K spectrum :-) No connector for microdrive and the ZX printer? :-) Did you not think it is more nice to have a ZX in a box like this: http://www.rose-bopla.com/Prod_Pgs/BAB/Prod_02_Alubos.htm PS2 Connector and sdcard slot on front, and VGA on back? OlafArticle: 134957
Hi, found this thread http://forums.xilinx.com/xlnx/board/message?board.id=XLNXBRD&message.id=786 but it still doesn't install the usb drivers on my Vista installation with all of the latest updates. I get this error when I try to install. http://i112.photobucket.com/albums/n179/laserbeak43/jtag.jpgArticle: 134958
Hi, Anyone actually implemented or seen Altera's Serial Lite protocol implemented on a Xilinx FPGA? Anyone familiar with Serial Lite (and Xilinx) see any fundamental stmbling blocks? TIA!Article: 134959
On Sep 6, 11:06=A0pm, LittleAlex <alex.lo...@email.com> wrote: > I just spent two hours looking for a package drawing. =A0Still haven't > found the one I'm looking for. > > I did find UG112. =A0On page 117 it has a link for the package > drawings. =A0That link is dead. =A0It does have a valid link to the > Virtex4 package drawings. =A0Not the ones I was looking for. > > I found 'mentor_pcb.pdf'. =A0It says "Go towww.xilinx.comand click > Documentation to find the user guide for your device." =A0The user > guides do NOT have package drawings. > > I found "AR #11956 - Packaging - Where can I find Xilinx packaging > information and package drawings?" - the 1st answer links to (the > useless) UG112. =A0The 2nd (last) link is dead. > > I went to "Doc Type" -> "Package Specifications". =A0Under "Design > Files" all I can find is the "IPC-1752 Form". =A0While a "Material > Composition Declaration" is important, it is not what I need to make a > PCB footprint. > > Just for fun, I went to a competitors web site. =A0Three clicks from the > home page (Literature -> Packaging -> Device Package) I found "DS- > PKG-15.1", which has the footprint data for -all- of their packages in > one convienent PDF. Does the website show you what you need now? I went to Xilinx.com, hit the "Documentation" link at the top of the page, selected the Doc Type tab, expanded the Package Specifications item and found 33 links catagorized into 5 sections. The "See all Package Specifications" link at the top of this expanded section provides a very long list of packages. Were these links not there on Saturday? - John_HArticle: 134960
"woko" <wkopp@gmx.net> wrote in message news:4d1085f3-8c9d-4f56-8966-976446092be8@x41g2000hsb.googlegroups.com... > Hi FPGA specialist, > > we are would like to know if it is currently possible to implement > high speed LVDS receiver or transmitter in FPGAs. > > Our next gerneration PCB board would have about 12 LVDS receiver > (SN65LV1224B) , 6 LVDS transmitter (SN65LV1023A) and an FPGA > onboard. > Please note that the LV1224 and LV1023 transmit thair LVDS in a single > differential line, there is no LVDS clock pair necessary. The clock > speed would be 48Mhz which would lead to a LVDS bandwidth of 576Mbs > (12bit transmitting). > It would save us money and FPGA IOs if we could get the serialization > and deserialization in the FPGA. > > I could find application notes about LVDS in a cyclone3, but I don't > think that reception works without a clock pair. > > Is anybody out there which as experience with this kind of LVDS in a > FPGA? > We would be obliged for some practical hits... > > > Curious about your answers, > Wolfgang Kopp > Hi Wolfgang, Data recovery without a clock is easy at 48Mbps. STW for XAPP224. HTH., Syms.Article: 134961
On Sep 8, 9:44 am, John_H <newsgr...@johnhandwork.com> wrote: > On Sep 6, 11:06 pm, LittleAlex <alex.lo...@email.com> wrote: > > > > > I just spent two hours looking for a package drawing. Still haven't > > found the one I'm looking for. > > > I did find UG112. On page 117 it has a link for the package > > drawings. That link is dead. It does have a valid link to the > > Virtex4 package drawings. Not the ones I was looking for. > > > I found 'mentor_pcb.pdf'. It says "Go towww.xilinx.comandclick > > Documentation to find the user guide for your device." The user > > guides do NOT have package drawings. > > > I found "AR #11956 - Packaging - Where can I find Xilinx packaging > > information and package drawings?" - the 1st answer links to (the > > useless) UG112. The 2nd (last) link is dead. > > > I went to "Doc Type" -> "Package Specifications". Under "Design > > Files" all I can find is the "IPC-1752 Form". While a "Material > > Composition Declaration" is important, it is not what I need to make a > > PCB footprint. > > > Just for fun, I went to a competitors web site. Three clicks from the > > home page (Literature -> Packaging -> Device Package) I found "DS- > > PKG-15.1", which has the footprint data for -all- of their packages in > > one convienent PDF. > > Does the website show you what you need now? > I went to Xilinx.com, hit the "Documentation" link at the top of the > page, selected the Doc Type tab, expanded the Package Specifications > item and found 33 links catagorized into 5 sections. The "See all > Package Specifications" link at the top of this expanded section > provides a very long list of packages. > > Were these links not there on Saturday? > > - John_H I couldn't find them on Saturday. I remember seeing the IPC-1752 Forms, but do -not- remember seeing the links for package drawings. On Saturday when I did a site-search for 'CP132', I got 2 hits. Today I got 80. The link in UG112 is still dead though. (Comment to Xilinx: Killing off links that are printed in published documentation is a bad thing.) But thanks to you-all, I have found the data I need. (Comment to Gabor: It was the PDF's that I was looking for.)Article: 134962
Thanks for posting the code. I did some investigations with your code myself, and reached some conclusions: Synplify Pro analyzes the difference between what the next count would have been (Max + 1) and the reload count (0). It only includes logic to switch between the bits that are different, in this case bits 3 and 7, leaving the rest of the bits alone. This means the terminal count could have more to do with optimal results than the chosen comparison. Just to play around, I changed the comparison to (count + 1 > Max) to share the increment logic, and it reduced the LUT (V4) usage from 12 to 11, but with a slightly slower implementation. I ran all tests with a clock constraint of 100 MHz, with all results indicating fmax of around 300 +/- 30 MHz, so these were resource optimized, not timing optimized implementations. I also tried one of my favorite tricks (converting to a down counter, and comparing count - 1 < 0), and it actually did worse with 13 luts, but all were one or two input luts. From a routability/congestion POV, it may or may not be better. Food for thought... BTW, I'm not sure your test to include extra unused bits was valid. It looked to me like you were actually implementing a 24 bit counter that counted from 0 to 2**23+135, not from 2**23 to 2**23+135. AndyArticle: 134963
Jochen <JFrensch@harmanbecker.com> wrote: >On 4 Sep., 18:06, n...@puntnl.niks (Nico Coesel) wrote: >> Jochen <JFren...@harmanbecker.com> wrote: >> >We had an issue with a "ground bounce" (Spartan3 design) in the bank >> >containing the PCI-interface, which 'triggered' the asynchonous reset >> >of the PCI-core... >> >> >Do you use async resets ? >> >> Yes. The design uses async resets. But it doesn't seem to affect the >> PCI core. The problem is always in the part with the statemachines. >> > >well - let's have a look at > http://forums.xilinx.com/xlnx/blog/article?message.uid=12856 > >esp. chapter "Unreliable Sporadic Behaviour!" Interesting reading material. Thanks. Meanwhile I removed all async resets from the design. I'm still waiting for the test results though. The silly thing is that the Xilinx PCI core examples the design is based upon are full of async resets. >P.S. > Ken really knows, what he is talking about !!! No doubt about that! -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 134964
On Sep 8, 2:59=A0pm, Andy <jonesa...@comcast.net> wrote: > > BTW, I'm not sure your test to include extra unused bits was valid. It > looked to me like you were actually implementing a 24 bit counter that > counted from 0 to 2**23+135, not from 2**23 to 2**23+135. > Maybe you're looking at the 'Cnt3' implementation. For 'Cnt1' and 'Cnt2' I posted results for "Bits=3D24, Max=3D135" where the counter counts from 0 to 135 but does so within an output signal that is 24 bits wide. If you have that situation, then ideally, one would hope to only be chewing up the resources that it would take to implement an 8 bit counter not the resources to implement a full 24 bit counter (which was the "Bits=3D24, Max=3D2**23+135" scenario). What I was demonstrating is that such hope is likely going to end in disappointment, you'll likely get the resources needed for the 24 bit counter. One should verify first with a test case like the one I provided to see if your chosen synthesis tool does recognize that the upper 16 bits are always going to be 0 and reduce the logic as such. Of course nobody intentionally puts more bits into a counter than are really needed, and some tools might optimize it all the way down to the minimum, but there are some who like to think that synthesis tools automatically perform extensive reachability analysis and will spot such things, this was just a simple example to throw a bit of water on that unsupported optimism. For 'Cnt3' I didn't synthesize this scenario. Kevin JenningsArticle: 134965
knight <krsheshu@gmail.com> writes: > Can anyone tell me how can i multiply two signed numbers in FPGA. > How the logic is really implemented.. There are many possible methods; one of the simplest but not necessarily the highest performance is a Baugh-Wooley multiplier. Google turns up some references, but for a good explanation you'd have to find a book on digital arithmetic.Article: 134966
Thank you Sir. I checked on the oscilloscope and now it is working as expected. I was missing that signal (dac_clr). Also, I was declaring the '12-bit unsigned data' of the 'frame' as 'std_logic_vector' instead of 'unsigned'. Thank you again, m m ____________________________ On Aug 23, 6:47=A0pm, Frank Buss <f...@frank-buss.de> wrote: > > I have implemented a simple test for the Spartan 3E starter kit board, > which has the same DAC: > > http://www.frank-buss.de/SignalGenerator/ > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.deArticle: 134967
Olaf Kaluza wrote: >> 16K rom image from spi flash address $10000 (1MB offset). If a >> spectrum 16K rom was programmed there, then you had a VGA-PS/2 >> keyboard 16K spectrum :-) > > No connector for microdrive and the ZX printer? :-) :-) The microdrive requires a dedicated controller, but the zx-printer could be driven by just adding an edge connector and bringing Z80 signal there. Btw, I've also designed a simple interface for real machines (I mean zx-spectrum) which gives sd-card, IF1 (rs-232 and network), kempston joystick, flasorom and ram capabilities. www.zxbada.bbk.org/zxmmcp and the simpler www.zxbada.bbk.org/zxmmc > Did you not think it is more nice to have a ZX in a box like this: > > http://www.rose-bopla.com/Prod_Pgs/BAB/Prod_02_Alubos.htm I'll keep it in mind :-) Ciao! AlessandroArticle: 134968
Yes I was looking at Cnt3. I just tried cnt3 with 24 bits, max = 135, using up-counters, with both (count + 1 > max) and (count > Max - 1) comparisons, Synplify Pro recognized the upper bits as always zero and pruned them. Utilization identical to before (8 bits) in both cases. However when I reworked it to a down counter, with (count - 1 < 0) comparison, SP did not remove the upper bits. AndyArticle: 134969
MikeWhy wrote: > There's this: http://www.knjn.com/board_Xylo.html. Seems way > overpriced at $300 USD. Yes, it's interesting but overpriced, imho. > Also take a look at Digilent's Nexys2 > http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable. > $100 USD. Sounds like a good match except the FG320 package, 16 MB > SDRAM, and Xilinx platform flash. VGA output is 8-bit color only. I saw this board a couple of weeks ago. Maybe a good choice now that I know that sdram is simpler to drive than the ddr. That kind of sdram, furthermore, can be accessed a static ram (slow: 70ns). Do you think that the typical random access of an 8 bit microprocessor could take advantage of the "sdram mode" over the 70ns "static ram mode"? I mean, an average-design sdram controller could get more out of that chip than 70ns in random rd/wr? > Why not go straight for your own protoboard instead? Can't you just > simulate the SRAM if you're concerned about timing? It was just to save time and to make it easier for those interested in building one, by providing a source for ready hardware. Ciao! AlessandroArticle: 134970
Frank Buss wrote: > Use non-DDR SDRAMs in your design. I'm not sure, but I think there is > no lower limit for the clock and you can implement your own SDRAM > controller, which is easy, if you don't need the highest performance > with burst-access, caching etc. Ok, I think I see your point. It looks like worth of spending some time seeking for info about sdram world, if it's really easier than ddr. I think I'll download an sdram datasheet (for example the psdram installed on the nexys2 board) to see if I could afford it and if the speed is comparable to that of a static ram chip. I think 15 or maybe even 20ns of "equivalent static ram" could be enough, if I can handle properly the T80 signals in order to maximize the available time for the memory to respond. 10ns would be really perfect but I don't think it's possible. Thanks to everybody! AlessandroArticle: 134971
On Aug 8, 8:52=A0pm, Bryan <bryan.fletc...@avnet.com> wrote: > You could use a board that has a 2x6 or two 1x6 Digilent PMOD > connections and then use the Digilent SD PMODhttp://www.digilentinc.com/P= roducts/Detail.cfm?Prod=3DPMOD-SD&Nav1=3DProd.... > > Some candidates include: > =A0- Avnet Spartan-3A 400A Eval board (www.em.avnet.com/spartan3a-evl) > =A0- Xilinx Spartan-3A DSP 1800A Starter (www.xilinx.com/s3adspstarter) > =A0- Xilinx Spartan-3A 700A Starter (www.xilinx.com/s3astarter) > > Bryan Digilent's SD card plugs into Digilent's Nexys2 board. http://www.digilentinc.com/Products/Detail.cfm?Prod=3DNEXYS2&Nav1=3DProduct= s&Nav2=3DProgrammable Not bad at $99.Article: 134972
On Sun, 7 Sep 2008 23:24:22 +0200, "Alessandro" <apoppi@email.it> wrote: |I've also found this interesting board |http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS2&Nav1=Products&Nav2=Programmable |with 16MB of "cellular ram", or psdram, which can be accessed like an |asynchronous chip (self refresh is internally provided) but, unfortunately, |it's speed is 70ns in async mode. | |------------ Add $20 tothe base price and you get a XC3S1200 instead of the XC3S500 onthe NEXYS 2 board. Then you will have more than enough room for a dual port SDRAM controller. I would still believe that the ZX would fit well into the XC3S500 with a dualport SDRAM controller. jamesArticle: 134973
On Mon, 8 Sep 2008 06:40:38 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On Sep 8, 7:14 am, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> But if you are "rolling your own" multiplier (perhaps to get a properly >> pipelined 32*32 multiplier for speed, using the internal components) the >> easiest way is to convert to unsigned numbers, and handle the sign bits >> separately. > >I wouldn't agree with that last suggestion. This takes extra logic in >the data path to complement the numbers, both on input and output. >The Booths algorithm can multiply signed inputs and works as well as >unsigned multiplies. Good point. My approach probably isn't the optimal solution in terms of gate count, if space is tight. Can you really use Booths algorithm for decomposing a large signed multiplication into 18*18 blocks? I have only seen it used at the level of individual additions/subtractions. I haven't really considered using it over the built-in mults/DSP48s. If that works, it would certainly be a better approach. - BrianArticle: 134974
Hi all, I=92ve been looking through the Xilinx documentation on RPMs and can place individual FFs in my Spartan-3 design without any problems but I=92m having trouble getting Verilog busses to place properly. Here is a section of my code: reg [7:0] count_a; reg [7:0] count_b; // synthesis attribute rloc of count_a[0] is X0Y2; // synthesis attribute rloc of count_a[1] is X0Y2; // synthesis attribute rloc of count_a[2] is X0Y3; // synthesis attribute rloc of count_a[3] is X0Y3; // synthesis attribute rloc of count_a[4] is X0Y4; // synthesis attribute rloc of count_a[5] is X0Y4; // synthesis attribute rloc of count_a[6] is X0Y5; // synthesis attribute rloc of count_a[7] is X0Y5; // synthesis attribute rloc of count_b[0] is X2Y2; // synthesis attribute rloc of count_b[1] is X2Y2; // synthesis attribute rloc of count_b[2] is X2Y3; // synthesis attribute rloc of count_b[3] is X2Y3; // synthesis attribute rloc of count_b[4] is X2Y4; // synthesis attribute rloc of count_b[5] is X2Y4; // synthesis attribute rloc of count_b[6] is X2Y5; // synthesis attribute rloc of count_b[7] is X2Y5; However, when I go to the FPGA Editor, the attributes seem to be ignored. count_a is lined up correctly, but count_b is completely scattered randomly over multiple columns. I believe the first set of RPMs aren=92t even working because count_a will still line up correctly when I remove the first 8 constraints. I=92m wondering if there is anything wrong with the way I am setting up my RPMs. Does anyone have any ideas? Thanks, Brian
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