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On 14 Aug 2005 19:21:08 -0700, ScreamingFPGA@yahoo.com wrote: >Hello All, > I'm three days into this configuration problem, >so I think it's time to consult the experts. >Problem's like this usually seem trivial in >retrospect, but I've usually been looking in >the wrong places... > > Briefly, INIT line goes low one CCLK pulse after >DONE line goes high. Configuration loads and runs, >but INIT line low indicates a CRC error. The signals >look quite reasonable on a scope. > > Specifics: > On a new prototype board I'm trying to congigure >a Spartan-3 3s1000-5fg456 using a 3.3V IO micro- >controller driving the fpga's config lines. Dedicated >config lines have serial resistor (100 ohm), as >per recommendation for 3.3V tolerant config. > > I'm using slave-serial mode to write config file, >which is stored on the micro's flash memory. I've >used the same micro and method successfully in other >products (but using Spartan-2). > > I send all data frames ( FFFFFFFF , AA995566 , >... 20000000 ) start to end of file. > > I'm not sure exactly _where_ the DONE line should >go high. It would seem that it should go high at some >point after the last 32-bit configuration frame, but >in fact DONE transitions on the 7th CCLK pulse of the >(N-4)th configuration frame. XAPP452 shows this as being >[CMD Write Packet Data(DESYNC)] frame. The INIT line >goes low on the 8th CCLK pulse, Fpga operation commences >on the 9th CCLK pulse. > > All design tweaks (resistor value changes) and clock/ >data timing tweaks result in the same behavior. I would >have thought that the CRC error would have prevented >startup of the fpga (CRC is _not_ disabled in bitgen), but >I guess this is not the case... > > If the DONE line _is_ going high early, I suppose this >would mean that extra CCLK transitions were seen by >the FPGA, pointing perhaps towards signal integrity >issues, but this would puzzle me, as under different >circumstances, the transitions happen at the same >points. > > The bit file is being generated by ISE6.2.02. > > Sorry, this post is longwinded, I'm hoping that someone >in the group has encountered a similar situation and can >perhaps point me in the right direction. > > Thanks in advance... > >Scott@sdeviation.com You might try banging some extra dummy bits; sometimes that helps. JohnArticle: 88301
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:430011f2@clear.net.nz... > GPE wrote: >> "austin" <austin@xilinx.com> wrote in message >> news:1124032605.076143.24740@g14g2000cwa.googlegroups.com... >> >>>Ed, >>> >>>I am not providing you with an excuse, just letting you know what the >>>reality is. We test, and we test a lot. But, with new products, and >>>new features, we can't be perfect, and we provide the fixes on a very >>>timely basis (usually every bug found is fixed in the next service >>>pack, or sooner by a tactical patch). >>> >>>Austin > <snip> >> >> Another example - I have an older design written in Abel (OK - it was >> written long, long ago). Recently I modified the code to change the >> revision number within the CPLD. Compiled it with version 7.1... it >> gives no errors and appears to compile just fine. Download it to the >> part and nada.... nothing works. I look at the JEDEC file and it's half >> blank. > > Did you check the created files, to see if the fitter, or front end tools, > dropped the ball ? Never did see what happened. Once I got it to compile with 6.1 - I just left it at that. While doing the initial compiles - I looked thru the log files cursively - never did see anything odd with them. NEver went into any detail, though. > >> Strange as the compiler didn't give any errors. Compiled the old, >> unmodified code with 7.1 - same results. Compiled both old and new with >> version 6.1 and it all works just fine. > > ABEL is like assembler - there are still some designs where it is be > best tool. Did you send Xilinx this example, so they can fix it ? Probably should have. It was weird that it gave no errors yet wouldn't compile right. > > >> But, hey, to tell the truth - there really isn't a whole lot to complain >> about regarding Xilinx sotware now that I've tried Atmel's Prochip >> Designer. Phew! Brings back memories of the old XACT days with DOS!!! >> >> Suggestion.... >> I use lots of Xilinx Vertex and XC9500xl parts. Hey, these are good >> parts. But due to selection, for one of my projects, I often have to go >> with Atmel. They have the ATF150x series CPLD's which are DIRT cheap, >> operate from 5 volts and come in a PLCC package. Closest thing would be >> the Xilinx XC9500 series but they cost far, far more. I can easily fit >> the design in an ATF1504 which costs about $5. To get the same design to >> compile within a Xilinx part - I had to keep bumping it up in density >> until I got to the XC95288... and these cost many times the $5 price. > > With over 6x the MC's, the price delta is not suprising. > The ATF15xx series are usually ~2x, and in rare cases, up to 3x, more > efficent so I'm surprised you need to go to 288MC in the 9500 to get a > fit. Sounds more like a tool issue - did you show that to Xilinx ? I believe it wasn't really a macrocell count issue in this case but rather a routing issue. Can't remember details at this time - I'll rerun it since I now have design done.. > > >> It would be real nice if Xilinx would also supply CPLD's with this >> increased density, operate from 5 volts, be much cheaper like the Atmel >> parts and be in a large PLCC (MUST be socketable) package. Heck, I can >> forgo the 5V with an LDO but still MUST retain 5V I/O interface like the >> XC9500XL's. > > Lattice ispMACH4000 series show 5V I/O tolerance, but no PLCC. > PLCC packages ( esp the smaller ones ) are usefull, but the trend > is to TQFP and MLF, so socketing is going to get harder.... > Yeah, I saw those. It's the PLCC that gets me. Gotta be socketable and I don't have access to SMD equipment for this type of effort. > I can understand killing PLCC68 and PLCC84, but PLCC44 is still usefull. I hope they keep the larger PLCC's especially the 84! The PLCC44 isn't very usefull due to the large number of pins used for power and JTAG. Only end up with roughly 30 usefull pins when done. > > Their new MachXO is Spec'd to 4.25V max. > > >> You know what would be real neat -- if somebody were to come up with a >> generic 5 volt, 40-PIN DIP CPLD in a high enough density to emulate a >> 6502 or 6800 processor or the myriad of support parts that are no longer >> available. Ohhhh.... I'd give an arm and a leg for a cheap and reliable >> source of this type of part! > > The volumes for this might kill it as a product - I have seen BGA packages > put onto DIP40 headers, which could solve your problem ? > Oh, I dunno if demand will be real small - but probably not big enough for the incredibly huge volumes everybody wants, though. There's still a lot of demand out there for some of the old stuff. Have you seen what the prices for the good old 6821 PIA's have done in the past year or so since the last mfr (ST) discontinued them? And, just in the past two years, 6800 CPU's have gone from ~$2 each to $6 each for NOS ones. Rockwell RIOT's have gone from $1.89 each to $6.50 each in the same amount of time. I imagine this will escalate qutie quickly. Unfortunately, them adapters are usually extremely expensive and often more than the IC itself. That tends to be another issue. And having to attach the BGA -- that's another issue. I have two jobs -- #1 -- the real one which produces plenty of high density boards with SMD, etc. #2 -- the hobby which sells parts/assemblies to a rather limited audience. It's this hobby job that requires no SMD for several reasons - first being I don't own SMD equipment at work. Second being that my customers frown... no make that loudly curse - at SMD components. Just for the heck of it - I redesigned one my high demand boards to use a single Spartan-3 to perform the task of a 6502 plus three 6532's and a bunch of glue logic. It fit and worked beautifully. These Spartan's are cheap considering I would only need one. Problem is - I have no way to install a PQFP-208 (or could ahve been a PQFP-240) on my board. These boards are used in relatively harsh environment and gotta be - MUST be user replaceable with no custom tools. I'd love to see an inexpensive way to do this! Anybody have any ideas? -- Ed > -jg >Article: 88302
GPE wrote: > "Jim Granville" <no.spam@designtools.co.nz> wrote in message > news:430011f2@clear.net.nz... > >>GPE wrote: >>>Another example - I have an older design written in Abel (OK - it was >>>written long, long ago). Recently I modified the code to change the >>>revision number within the CPLD. Compiled it with version 7.1... it >>>gives no errors and appears to compile just fine. Download it to the >>>part and nada.... nothing works. I look at the JEDEC file and it's half >>>blank. >> >>Did you check the created files, to see if the fitter, or front end tools, >>dropped the ball ? > > > Never did see what happened. Once I got it to compile with 6.1 - I just > left it at that. > While doing the initial compiles - I looked thru the log files cursively - > never did see anything odd with them. NEver went into any detail, though. > >>>Strange as the compiler didn't give any errors. Compiled the old, >>>unmodified code with 7.1 - same results. Compiled both old and new with >>>version 6.1 and it all works just fine. >> >>ABEL is like assembler - there are still some designs where it is be >>best tool. Did you send Xilinx this example, so they can fix it ? > > > Probably should have. It was weird that it gave no errors yet wouldn't > compile right. Wierd yes, rare no.... <snip> > Just for the heck of it - I redesigned one my high demand boards to use a > single Spartan-3 to perform the task of a 6502 plus three 6532's and a bunch > of glue logic. It fit and worked beautifully. These Spartan's are cheap > considering I would only need one. Problem is - I have no way to install a > PQFP-208 (or could ahve been a PQFP-240) on my board. These boards are used > in relatively harsh environment and gotta be - MUST be user replaceable with > no custom tools. I'd love to see an inexpensive way to do this! Anybody > have any ideas? The cheapest way to get this, is to piggy-back on someone elses volume ? - ideal here would be Pentium PGA ZIFF sockets. Many pins at low costs. [ Pentiums are actually modules, with caps included ] Design the FPGA onto a carrier PCB, add caps, and reflow them at your work. -jgArticle: 88303
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:430035d1$1@clear.net.nz... > GPE wrote: >> "Jim Granville" <no.spam@designtools.co.nz> wrote in message >> news:430011f2@clear.net.nz... >> >>>GPE wrote: >>>>Another example - I have an older design written in Abel (OK - it was >>>>written long, long ago). Recently I modified the code to change the >>>>revision number within the CPLD. Compiled it with version 7.1... it >>>>gives no errors and appears to compile just fine. Download it to the >>>>part and nada.... nothing works. I look at the JEDEC file and it's half >>>>blank. >>> >>>Did you check the created files, to see if the fitter, or front end >>>tools, dropped the ball ? >> >> >> Never did see what happened. Once I got it to compile with 6.1 - I just >> left it at that. >> While doing the initial compiles - I looked thru the log files >> cursively - never did see anything odd with them. NEver went into any >> detail, though. >> >>>>Strange as the compiler didn't give any errors. Compiled the old, >>>>unmodified code with 7.1 - same results. Compiled both old and new with >>>>version 6.1 and it all works just fine. >>> >>>ABEL is like assembler - there are still some designs where it is be >>>best tool. Did you send Xilinx this example, so they can fix it ? >> >> >> Probably should have. It was weird that it gave no errors yet wouldn't >> compile right. > > Wierd yes, rare no.... > > > <snip> >> Just for the heck of it - I redesigned one my high demand boards to use a >> single Spartan-3 to perform the task of a 6502 plus three 6532's and a >> bunch of glue logic. It fit and worked beautifully. These Spartan's are >> cheap considering I would only need one. Problem is - I have no way to >> install a PQFP-208 (or could ahve been a PQFP-240) on my board. These >> boards are used in relatively harsh environment and gotta be - MUST be >> user replaceable with no custom tools. I'd love to see an inexpensive >> way to do this! Anybody have any ideas? > > The cheapest way to get this, is to piggy-back on someone elses volume ? > - ideal here would be Pentium PGA ZIFF sockets. Many pins at low costs. > [ Pentiums are actually modules, with caps included ] > > Design the FPGA onto a carrier PCB, add caps, and reflow them at your > work. Would be my first choice... but we now contract out the assembly.... -- Ed > > -jg > >Article: 88304
What is the initialization of refmemdata that is before the first rising edge of clk ? Rgds Andr=E9Article: 88305
GPE wrote: > I hope they keep the larger PLCC's especially the 84! > The PLCC44 isn't very usefull due to the large number of pins used for power > and JTAG. Only end up with roughly 30 usefull pins when done. In their latest data, with the move to lead-free, Atmel are dropping the PLCC68, and the PLCC84 is restricted to only non "L" and industrial grade. -jgArticle: 88306
Andrew Greensted wrote: > Dear all, > > I'm having some problems installing Xilinx ISE on a Gentoo system. Well, I've managed to get ISE to install. But then getting it to run seems to be a problem. I've created a page with install instructions. It can be found here: http://www.bioinspired.com/users/ajg112/electronics/xilinx.shtml Hopefully I'll soon be able to add a 'How to run' section!! Any ideas would be REALLY appreciated. AndyArticle: 88307
Hallo, I have made a small opb peripheral with registers support. Into a state machine I connect slv_reg0 to an external signal that is temporary latched. When that signal wil not be latched I should disconnect it from slv_reg0 and slv_reg0 should latch data until I reconnect it to the external signal. How could I realize it? I have read about the vhl command "disconnect", but if I use it I receive the following error message: unexpected DISCONNECT Many Thanks MarcoArticle: 88308
Hi group I'm trying to infer an 18-bit rom to be put in a block RAM. I'm using a case statement and a clocked address as described by Xilinx. My ROM is 1024 words, so I was thinking that this could be done using only one BRAM, but the ISE 7.1 webpack creates two BRAMs in this case. Isn't it possible to fit more than 16 bits of ROM into a single BRAM ? I can fit 18 bits of RAM so why not ROM ? -- BrianArticle: 88309
pinod01@sympatico.ca wrote: > To all, > > I'm trying to create a test bench where an array data type of > "std_logic_vector" is read within a for loop and then stored to a file. > The problem I'm facing is that the array accesses the starting index > of 0 twice and doesn't capture the last element of the array as it > should. That is the line stated below as: "refmemdata <= mem_arr(k)" > returns the value of the signal at k = 0 twice eventhough the value of > k in the second iteration of the loop is k = 1. Why? Any help would > be grateful. > > Section of VHDL code for above problem: > ====================================== > > -- Signal Declaration > signal refmemdata :std_logic_vector(2 downto 0); > type mem_vec_arr is array (0 to 4) of std_logic_vector(2 downto 0); > constant mem_arr: mem_vec_arr :=(0 => "000",1 => "001",2 => "010", 3 => > "011", 4 => "100"); > > file data_vector_file: text open write_mode is > "D:\written_data_file.txt"; > > -- Array accessing and file storage > stimulus: process() > variable data_file_line: line; > begin > for k in 0 to 4 loop > wait until (clk'event) and (clk = '1'); > refmemdata <= mem_arr(k); > write(data_file_line, to_bitvector(refmemdata)); > writeline(data_vector_file,data_file_line); > > end loop; > > end process; Answer Andre's question, and also learn about delta delays and assignment scheduling. -aArticle: 88310
Alex wrote: > Hi guys. > > Implementing asynchronous delays in my design via a chain of buffer > elements > (I know it's a bad practise, but I need few ns delays) I faced the > problem with > removing them from the design, as Xilinx synthesiser removes these > elements from > the design, although the OPTIMIZE option is off. > > So I'd like to ask if anyone can tell me where I missed something, and > also if someone > already implemented small delays via internal FPGA units (not RC > chains)which elements > may provide the biggest delay (in order to save space). Why do you need an async delay? -aArticle: 88311
Fpga_Designer wrote: > Hello all, > > I am currently using xilinx modular design flow to develop a simple > design. The top level design has an inout port for communicating data > between an external memory and fpga. I have implemented the necessary > control logic for this port in one of the modules and port mapped the > port of the module to the top level inout port. After having done this > when I run (ngdbuild -modular initial top.edd) with all the modules > instantiated (black boxes only) I receive the following error > "ERROR:NgdBuild:456 - logical net '***' has both active and tristate > drivers". > > Can anyone suggest what needs to be done in this regard. Did you simulate your design? The error is clear -- you have two drivers on the same net. A simulation would have shown this. -aArticle: 88312
QRaheeL wrote: > An intesresting problem occured when I used "more than three" signals > in always block sens list. > > XST (ISE 6.1i) reported the following error: > > ERROR:Xst:1468 - dummy.v line 25: Unexpected event in always block > sensitivity list. > > Same code is successfully compiled & simulated in MOdelSim5.7SE. > > What kind of problem is this ? > Related to parser/editor/etc ?? > > //-------- C O D E - C O D E --------/// > > module dummy(x); > output x; > assign x = 1'b0; > > reg a,b,c,d; > reg z; > > initial > begin > a=0; b=0; c=0; d=0; z=0; > #100 $stop; > end > > always #10 a=~a; > always #15 b=~b; > always #20 c=~c; > always #5 d=~d; > > always @(posedge a or posedge b or posedge c or posedge d ) begin > if(a) z=~z; > else if(b)z=~z; > else if(c) z=~z; > else if(d) z=~z; > end > endmodule What flip-flop has four clocks? -aArticle: 88313
bret.wade@gmail.com wrote: > Hi Antti, > > You would have had your solution a day earlier if you'd put a little > more effort into the Answers search. Something like "7.1i add external > pin" works for this case. You can't always depend on your posting being > read by the person who wrote the Answer Record. > > There is another FPGA Editor issue that you may run into: > http://www.xilinx.com/xlnx/xil _ans_display.jsp?getPagePath=21667 I've opened a handful of web cases where the response was, "In Answer Record 655321, you'll find your answer ..." Which is all well and good, but I still find it tough to hit on the magic search incantation that will lead me to the pot of gold at the end of the rainbow. -aArticle: 88314
311f037@gmail.com wrote: > Hey! > > SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF > file to load into this as thats the only thing I seem to be able to > import into the 4.2v > > So what do I need to do? somehow find a compiler? or a simulator? will > these output and EDIF from my VHDL? Both Mentor Precision Synthesis and Synplify compile with EDIF as the result. -aArticle: 88315
Unfortunately, we cannot move to the Hotlink II chip. The PCB layout has settled and we cannot spend the time nor the money to change the layout again to accomodate the new chip. So, I am back to square one. Anyone out there have a VHDL model for CY7B923/933? Thanks ErnieArticle: 88316
Hi, Did you remember to put in sychronizers between clock domains? Perhaps Alex is correct...an explanation of the system architecture would be helpful. Cheers ErnieArticle: 88317
ernie wrote:
> So, I am back to square one. Anyone out there have a VHDL model for
> CY7B923/933?
It wouldn't be hard to write one if you have a data sheet.
It's just a shifter/encoder/line driver.
Why do you need to simulate the interface chip?
-- Mike Treseler
Article: 88318Look up the "keep" and "save" attributes. Can't remember which does what (been too long since I played games like you are doing), but if you want the logic there that you put in, and do not want it optimized out. Austin Alex wrote: > Well it is fully asynchronous design - sort of concept-proof, > more in demonstration purposes. I know FPGA is not the proper platform > for it at all, however everything is working fine, apart that problem. > > So can anyone help with the problem when the synthesiser optimize the > design by throwing buffer elements away? > > >Article: 88319
Hello, last year there was a post concerning Altera abandoning AHDL in their new tools, such as Quartus. The post also said that you couldn't use AHDL with SOPC Builder or DSP Builder. If this is true, it seems to be a big constraint for the designer; then again, I have yet to use SOPC or DSP Builder. How then do you write custom logic, do you have to write everything in .vhdl or .verilog? I have a few co-workers who used DSP Builder, but couldn't get to work correctly, it required purchasing more software from Altera. They dropped DSP Builder and went back to AHDL coding. Is AHDL a thing of the past? Is a better approach SOPC and DSP Builder? If so, then I better start reading more about these tools. Any comments on AHDL, Altera, SOPC Builder, or DSP Building, please share them. thanks, joeArticle: 88320
Thanks it helped! Maybe if you have some experience you can suggest how maximise delay, using minimum hardware. I can gues that to use most of the slice hardware something like a chain LUT->mux->FF, but is it possible to implement two of chains within one slice (Spartan3) via manual placing; or maybe there are some other ways? The design is internal so I can't play with IOB's and external logic. Thanks > Look up the "keep" and "save" attributes. > > Can't remember which does what (been too long since I played games like > you are doing), but if you want the logic there that you put in, and do > not want it optimized out. > > Austin > > > Alex wrote: > >> Well it is fully asynchronous design - sort of concept-proof, >> more in demonstration purposes. I know FPGA is not the proper platform >> for it at all, however everything is working fine, apart that problem. >> So can anyone help with the problem when the synthesiser optimize the >> design by throwing buffer elements away? >> -- AlexArticle: 88321
Your code produces a delta between assigning refmemdata and write. Note
that signal assignments only update the signal drivers, which update
the signal value at the next cycle.
You can insert a wait for 0 ns; statement to let the signal settle:
...
-- Array accessing and file storage
stimulus: process()
variable data_file_line: line;
begin
for k in 0 to 4 loop
wait until (clk'event) and (clk = '1');
refmemdata <= mem_arr(k);
WAIT FOR 0 ns; -- let refmemdata settle
write(data_file_line, to_bitvector(refmemdata));
writeline(data_vector_file,dat a_file_line);
end loop;
end process;
or you can use a local variable, the preferred solution here:
stimulus: process()
variable data_file_line: line;
VARIABLE refmemdata :std_logic_vector(2 downto 0);
begin
for k in 0 to 4 loop
wait until (clk'event) and (clk = '1');
refmemdata := mem_arr(k); -- USE := instead of <= here
write(data_file_line, to_bitvector(refmemdata));
writeline(data_vector_file,dat a_file_line);
end loop;
end process;
Hubble.
Article: 88322Dear everybody, I'm a beginner in using VHDL to build hardware blocks. So, I would like to submit you a problem about clock generation. I have a 25MHz external clock driving a hardware block inside the FPGA. I need a 10MHz clock to drive another hardware block inside the same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is it possible ? Your answers will be appreciated Best Regards /Alessandro StrazzeroArticle: 88323
Hi, yes you can do that. I would suggest to study this document www.xilinx.com/bvdocs/appnotes/xapp462.pdf and in degeral read about DCM's if it a Xilinx chip, or check for PLL (sysClock pll's) for other vendors. Regards Alex On 15 Aug 2005 12:41:06 -0700, <alessandro.strazzero@gmail.com> wrote: > Dear everybody, > > I'm a beginner in using VHDL to build hardware blocks. So, I > would like to submit you a problem about clock generation. > I have a 25MHz external clock driving a hardware block inside the > FPGA. I need a 10MHz clock to drive another hardware block inside the > same FPGA. How can I have a 10Mhz clock from the 25Mhz clock ? Is > it possible ? > > Your answers will be appreciated > > Best Regards > > /Alessandro Strazzero > -- AlexArticle: 88324
I suppose you are describing your design in VHDL. Disconnect statements are used for bus signals which are controlled by an implicit GUARD signal inside of blocks. Probably not what you want. Drivers of signals can be disconnected by assigning the null waveform element. sig<=null; also not what you want. If you want to synthesize, it's best to describe in terms of standard register and latches. Your description is a bit puzzling, but it sounds to me as slv_reg0 is a normal latch, which is enabled when the external signal is valid and latching when it is invalid. You can describe this in VHDL without using disconnect or null waveform elements. Hubble.
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