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Messages from 88150

Article: 88150
Subject: Re: FPGA Programming using Block Design Files or Graphic Design Files
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 10 Aug 2005 11:04:48 -0700
Links: << >>  << T >>  << A >>
Monica wrote:

> I use graphical only on top level,that to when I would like to alter
> the top level components  and experiment with the components and their
> interfacing becausing it is easy for me to alter the connections.
> If I knew the connections between the components and if am sure that
> those top level blocks/modules and their interface is fixed then I will
> code it in HDL.

I like a graphical view of a design
but prefer text as the source.

With a good editor, copy/pasting of HDL instances
and wiring them up is no more difficult
that moving boxes and wires around graphically
and typing in labels.

With an RTL viewer you can let the
computer draw multi-level schematics for you from
the HDL text files.

With an HDL simulator you can verify
that all the wires are correct without
even looking at the HDL or schematic views.

       -- Mike Treseler


Article: 88151
Subject: Re: FPGA Programming using Block Design Files or Graphic Design Files
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 10 Aug 2005 11:28:29 -0700
Links: << >>  << T >>  << A >>
I just wanted to say that I write all of my code in text form, but I
create a symbol of the text code. Then in my schematic page, I just
insert the newly created symbol. I thought I needed to add this piece
of information. When everything is done I have a nice functional
diagram and when I click on the symbol it opens up my text code,
written in .VHDL, or Verilog, or Altera's AHDL (which is very easy to
write). I'm using Quartus and MaxPlus both from Altera. I don't know if
you can do this in Xlinx or other FPGA IDE's. A great idea to help
manage a complex design.

I'm so happy to hear people discussing this topic and appreciate all
responses.

thanks,
joe


jjlindula@hotmail.com wrote:
> Hello, I know this is a off-the-wall question, but bear with me. In my
> effort to become more efficient and improve my design process in my
> FPGA design I always create a top block diagram that is either a Block
> Design File (.bdf) or a Graphic Design File (.gdf). If you are not
> familiar with these files, they are basically a schematic where you can
> graphically add symbols and connect symbols via wires or buses. I
> believe using these files reduces complexity, and creates documentation
> while you design. I know it does take some time placing the wires,
> which is why some don't uses these files in their fpga design. In
> addition, using these graphical files allows you to create a
> hierarchical design which again helps manage complexity and makes the
> design easier to modify/maintain. I'm just wondering how many people
> use some sort of graphic design in their FPGA programs? I see so many
> benefits of doing so, but my co-workers see it as a waste of time
> placing those wires and symbols they would just rather have a design
> contain lots of .vhdl, .v, and .tdf files. Any thoughts, comments,
> suggestions, experiences on the topic? I'm not trying to be picky, its
> just when I see a tool that can help reduce complexity if can't
> understand why people wouldn't use it.
> 
> thanks,
> joe


Article: 88152
Subject: Re: FPGA Programming using Block Design Files or Graphic Design Files
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 10 Aug 2005 11:33:25 -0700
Links: << >>  << T >>  << A >>
Andy,

I know that commenting in schematics is a pain, but if you give your
schematic (FPGA project) to someone else they could gain so much
information pertaining to the design and any assumptions/comments that
needed to be passed on. Most people I work with say, "I do all my
documenation in Power Point" and I say that doing it in the schematic
it is already there and there's no need to start a Power Point project.
Document as you go. Just my thoughts, do what works well for you and
thanks for your comments.

joe


Article: 88153
Subject: Re: About post synthesize
From: "Vladislav Muravin" <muravinv@advantech.ca>
Date: Wed, 10 Aug 2005 16:31:21 -0400
Links: << >>  << T >>  << A >>
Dear Sumesh,

Sorry for late reply.
The best I can offer you is as following : Never use timing issues in 
simulation. Use simulation only for functional verification of your design. 
As a post-synthesis process, always use Timing Analyzer. If your design has 
a very high speed, simply pipeline it as much as possible.

There are some books on digital design, which may give you the idea of 
quantisizing the combinational logic by number of its level, but in my 
humble opinion, nothing substitutes the real experience and this is why all 
of us are in this newsgroup, to offer our help to everybody else...

Vladislav


"vssumesh" <vssumesh_asic@yahoo.com> wrote in message 
news:1123217592.243976.194350@g44g2000cwa.googlegroups.com...
> in that case is there any better procedure/tool with which i can
> analyse timing issues better than simulation. Please suggest any
> books/materials on this topic.
> I agree that the real silicon is the best model. But how can we analyse
> it if there is some problem in the timings ???
> Thanks for your advice
> Sumesh V S
> 



Article: 88154
Subject: Re: Hiding data inside a FPGA
From: Kris Vorwerk <kpvorwer@engmail.uwaterloo.ca>
Date: Wed, 10 Aug 2005 16:36:41 -0400
Links: << >>  << T >>  << A >>
>   I am working on cryptographic application over VirtexII FPGAs. I
> need to store a simmetric key inside a reg of the FPGA, but I dont
> want that someboy could read it analizyng the bitstream. The bitstream
> could not be encrypted. Has anybody experience about hide data inside
> a FPGA?. Anyone knows some papers about this topic?


As a possible alternative, you might want to consider ...

http://www.actel.com/products/rescenter/security/solutions/flash.aspx
http://www.actel.com/products/pa3/index.aspx

cheers,
Kris

Article: 88155
Subject: Using an oscillator in a rugged environment
From: alessandro.strazzero@gmail.com
Date: 10 Aug 2005 14:00:42 -0700
Links: << >>  << T >>  << A >>
Dear everybody,

I have to design an ALTERA Cyclone FPGA based board which will be
used in a rugged environment in terms of operating temperature
(-40 to +85 =B0C) and strong EMI interference.
I have to provide for the clock to the FPGA and I would like to use
a 16 MHz oscillator which will be multiplicated by 8 by the Cyclone
internal PLL in order to obtain a 128 MHz clock for the NIOS II
processor.

My doubts are the following:
- is a good choise to connect directly the oscillator output to the
  FPGA pin or for this kind of environment is suggested to build a
  more reliable circuit around the oscillator ?
- is a good choise using the internal PLL ?  Is it reliable in a
  rugged environment ? (I have chosen an external low frequency
  oscillator to reduce EMI emissions)
- are there exist on the market any oscillator specifically designed
  for rugged environment ?

Hope someone of you have already experienced these kind of
problematics in order to suggest me the best way to run.

Best Regards

/Alessandro Strazzero


Article: 88156
Subject: XBERT module.
From: sjm1218@gmail.com
Date: 10 Aug 2005 14:31:32 -0700
Links: << >>  << T >>  << A >>
I am a FPGA beginner. So, I worry that my question might be stupid.

Can I put a XBERT module on FPGA platform?

Does anyone have a pseuo-random bit generator code? 

Thanks.


Article: 88157
Subject: Re: XBERT module.
From: "austin" <austin@xilinx.com>
Date: 10 Aug 2005 14:56:10 -0700
Links: << >>  << T >>  << A >>
sj**

The XBERT(tm) module already contains the psuedo random bit generator.

If you download our IP, it is all conteined in there, and you do not
need to create the bit generator, received bit checker, error rate
calculator, etc.

If you wish to create your own BERT (bit error rate test) hardware,
that will be quite challenging, and take you a while to get it all
correct, and working right.

Since we offer this to you as a completed module, the only reason to
re-invent a wheel, is because you are a student, and this is an
exercise.

If you are a student, and this is an exercise, then you are cheating by
reverse engineering the XBERT(tm) module.

Austin


sjm1...@gmail.com wrote:
> I am a FPGA beginner. So, I worry that my question might be stupid.
>
> Can I put a XBERT module on FPGA platform?
> 
> Does anyone have a pseuo-random bit generator code? 
> 
> Thanks.


Article: 88158
Subject: Xilinx: Where has all the data gone?
From: "Gabor" <gabor@alacron.com>
Date: 10 Aug 2005 15:01:20 -0700
Links: << >>  << T >>  << A >>
Browsing the Xilinx website documentation I seem to get
no data sheets, user guides, or package drawings.  Just:

Sorry...
Technical difficulties with the Xilinx.com web site have been solved.
If you are continuing to have difficulty accessing Xilinx.com, you may
need to exit your browser software and restart it. Please accept our
apologies for any difficulties you have experienced.

I tried Netscape 7.2 and Internet Explorer 6.0 (restarted twice)
with the same results...


Article: 88159
Subject: Re: Xilinx: Where has all the data gone?
From: "Gabor" <gabor@alacron.com>
Date: 10 Aug 2005 15:14:03 -0700
Links: << >>  << T >>  << A >>

Gabor wrote:
> Browsing the Xilinx website documentation I seem to get
> no data sheets, user guides, or package drawings.  Just:
>
> Sorry...
> Technical difficulties with the Xilinx.com web site have been solved.
> If you are continuing to have difficulty accessing Xilinx.com, you may
> need to exit your browser software and restart it. Please accept our
> apologies for any difficulties you have experienced.
>
> I tried Netscape 7.2 and Internet Explorer 6.0 (restarted twice)
> with the same results...

Never mind... Everything seems to be back now...


Article: 88160
Subject: Re: XBERT module.
From: sjm1218@gmail.com
Date: 10 Aug 2005 15:19:49 -0700
Links: << >>  << T >>  << A >>
Austin,

Thanks for your reply. I am Jaemin.
Actually, I am not a student and don't want to develop it for an
exercise. :) Today, I tried to contact a Xilinx, but I donot have a
reponse yet. I would like to communicate with you for this thing by
email. 

Thanks.


Article: 88161
Subject: ASIC suggestions
From: "dave94024" <david.pariseau@sbcglobal.net>
Date: 10 Aug 2005 16:34:02 -0700
Links: << >>  << T >>  << A >>
We're about to move an existing design to an ASIC.  The prototype was
built using a small PIC and some discretes, so the ASIC will look
nothing like the prototype.

I'm looking for some suggestions for ASIC design house people have used
and been happy with as well as ASIC design services (someone able to
take a project successfully from concept through production), should we
decide to use outside services.

There are too many issues to detail here, but here are a few:
- Super-low power, we're looking for aggressive sleep mode, low power
while running, some kind of built-in RC oscillator if that's possible
(4MHz and 32KHz and off).
- Low voltage would be ideal 1.5 - 1.8 volts or thereabouts.
- Need some beefy I/O lines if possible 15-25ma
- The application itself is reasonably straight-forward, we need a
UART, a state machine, some switch debouncing, jelly-bean stuff like
that, as well as some kind of ROM space a few K and some RAM a hundred
bytes or so.

The more I think about the problem, the more it seems like a custom
micro-controller.  Any thoughts?

Thanks,
Dave.


Article: 88162
Subject: Re: FPGA Programming using Block Design Files or Graphic Design Files
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 10 Aug 2005 16:55:39 -0700
Links: << >>  << T >>  << A >>
jjlindula@hotmail.com wrote:
> I just wanted to say that I write all of my code in text form, but I
> create a symbol of the text code. Then in my schematic page, I just
> insert the newly created symbol. I thought I needed to add this piece
> of information. When everything is done I have a nice functional
> diagram and when I click on the symbol it opens up my text code,
> written in .VHDL, or Verilog, or Altera's AHDL (which is very easy to
> write). I'm using Quartus and MaxPlus both from Altera. I don't know if
> you can do this in Xlinx or other FPGA IDE's. A great idea to help
> manage a complex design.

I guess whether you can use this block-diagram-linked-to-code method
depends on how you partition and code your design.  I don't see any
gain in insight if you have a bunch of small blocks connected together,
and each of the small blocks has, say, a mux or a register.  I'd guess
that you have a bunch of disjoint files called MUX16_1 and such, each
containing a simple entity, and I agree that there's a lot of typing
involved in wiring these things together.

I hate having to constrain my coding style to fit a tool that'll change
with the next release.

-a


Article: 88163
Subject: EDK and ISE questions
From: "el_boricua" <nrivera.eng@gmail.com>
Date: 10 Aug 2005 19:44:41 -0700
Links: << >>  << T >>  << A >>
1. When creating a core in EDK 7.1 when it creates the dirver file
there is a core_selftest.c file at it includes a reference to a "
extern Xuint LocalBRAM " where is that LocalBRAM suppose to be defined
since the file doesn't compile like that.

2. What is the EDK simulation path for the BFM file?

3. What is the ISE simulation path?

Thanks,
NOel


Article: 88164
Subject: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "PeterC" <peter@geckoaudio.com>
Date: 10 Aug 2005 20:28:04 -0700
Links: << >>  << T >>  << A >>

I would like to ask if anyone knows of a good way to generate a 44.1
kHz clock (without ridiculous jitter) on an FPGA that is driven by a
98.304 MHz crystal.

It is required for an audio application (CD audio is sampled at 44.1
kHz). The digital frequency synthesizer core from Xilinx is not good
enough (frequency resolution is too coarse), and neither are the DCMs
(98.304 and 44.1 don't divide nicely). I also don't want to do sample
rate conversion!

Any suggestions would be greatly appreciated.

PeterC.


Article: 88165
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 10 Aug 2005 20:55:57 -0700
Links: << >>  << T >>  << A >>
It depends what you mean by ridiculous jitter. The ratio is, as you
know, 2,229.1156.
You can build a DDS (phase accumulator) running at 98.304 MHz clock
rate, and achive a jitter that is max half a period, i.e. <5 ns.
You could also build a controlled divider that can divide by 2229 or
2230, and switch between the two  ratios with a separate sequencer.
Better yet:
Can you stand a frequency error?  If you simply divide by 2229, you
have an error of about 50 ppm, and your incoming frequency will hardly
be more accurate. The advantage is: No jitter at all, except from the
incoming clock..

All these circuits can be built with two dozen flip-flops, i.e. just a
couple of CLBs in Xilinx parlance. And the frequency is very benign.
Peter Alfke, Xilinx Applications


Article: 88166
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 11 Aug 2005 16:38:47 +1200
Links: << >>  << T >>  << A >>
PeterC wrote:
> I would like to ask if anyone knows of a good way to generate a 44.1
> kHz clock (without ridiculous jitter) on an FPGA that is driven by a
> 98.304 MHz crystal.
> 
> It is required for an audio application (CD audio is sampled at 44.1
> kHz). The digital frequency synthesizer core from Xilinx is not good
> enough (frequency resolution is too coarse), and neither are the DCMs
> (98.304 and 44.1 don't divide nicely). I also don't want to do sample
> rate conversion!
> 
> Any suggestions would be greatly appreciated.

98.304 to 44.1KHz is ~52ppm error, about the same as a low cost crystal.
How precise does it need to be ?
-jg


Article: 88167
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "PeterC" <peter@geckoaudio.com>
Date: 10 Aug 2005 21:43:07 -0700
Links: << >>  << T >>  << A >>

Thanks Peter, I appreciate your insight.

The divider sounds most promising - 50 ppm frequency error is about as
good as my 98.304 MHz source as you said. The next question I suppose
is how best to do a divider by 2229?

The obvious design would be a counter with the limit set to 2229 as
this number is obviously not DCM friendly. This amounts to a 13 bit
counter which would indeed be quite small. If you can suggest an even
simpler way (or any other possible alternatives as to me the counter
seems like to only way) I'd like to hear it (judging by your 6 easy
pieces tech-xclusive you know a trick or two!).

PeterC.


Article: 88168
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "PeterC" <peter@geckoaudio.com>
Date: 10 Aug 2005 21:51:50 -0700
Links: << >>  << T >>  << A >>


52 (or 51.88 to be exact) is good enough for me, thanks jg.


Article: 88169
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 10 Aug 2005 22:22:19 -0700
Links: << >>  << T >>  << A >>
The easiest method is to build a presettable 12-bit counter, which
naturally divides by 4096.
Extend it by an overflow bit to 13 bits. Whenever the 13th bit becomes
1, it acivates the synchronous loading, and preset the whole counter to
the appropriate value (you figure it out, but make sure you account for
the one-bit overflow time, and dont forget to set the 13th bit to 0.)
The 13th bit gives you a 1-period spike, while the 12th bit gives you a
nice long signal.

There are LFSRs, but they are not worh the trouble, now that we have
carry structures.
You can also get rid of the 13th bit, by looking at a 11 of the two
MSBs.
Or you ould build a divide-by-three prescaler, but all of that is just
unnecessary trickery.
In Virtex-4 you might use the 42-bit accumulator/counter in the same
way.

The important thing is to build it as a synchronous counter and avoid
all ripple or asynchronous circuitry. (Well,the carry structure
ripples, but it i plenty fast enough, and you do not see the ripple
delay on any output)
I take it, you are in Sidney. Nice city. I spent some time at Darling
Harbor (?), even crawling through a submarine...
Peter Alfke

PeterC wrote:
> Thanks Peter, I appreciate your insight.
>
> The divider sounds most promising - 50 ppm frequency error is about as
> good as my 98.304 MHz source as you said. The next question I suppose
> is how best to do a divider by 2229?
>
> The obvious design would be a counter with the limit set to 2229 as
> this number is obviously not DCM friendly. This amounts to a 13 bit
> counter which would indeed be quite small. If you can suggest an even
> simpler way (or any other possible alternatives as to me the counter
> seems like to only way) I'd like to hear it (judging by your 6 easy
> pieces tech-xclusive you know a trick or two!).
> 
> PeterC.


Article: 88170
Subject: Re: EDK and ISE questions
From: Paul Hartke <phartke@Stanford.EDU>
Date: Wed, 10 Aug 2005 22:35:41 -0700
Links: << >>  << T >>  << A >>
1) Never run across that before.
When I grep for LocalBRAM in $XILINX_EDK, it only appears in 
/rtf/bin/nt/createip.exe and /rtf/bin/nt/libMdtWiz_CreateIpGui.dll
What core were you creating that used this variable?

2) I typically use full system simulation when testing custom
peripherals since using the IPIF pretty much enforces CoreConnect
compliance.  However, Xilinx has a whole doc dealing with BFM sims: 
http://www.xilinx.com/ise/embedded/bfm_simulation.pdf 

3) The Compile button under "Options"-->"Project Options"-->"HDL and
Simulation" is quite handy to correctly compile and setup the simulation
libraries.

If you are going to simulate the PowerPC, be sure to setup SWIFT
following Xilinx solution record 14019:
http://www.xilinx.com/techdocs/14019.htm

Paul

el_boricua wrote:
> 
> 1. When creating a core in EDK 7.1 when it creates the dirver file
> there is a core_selftest.c file at it includes a reference to a "
> extern Xuint LocalBRAM " where is that LocalBRAM suppose to be defined
> since the file doesn't compile like that.
> 
> 2. What is the EDK simulation path for the BFM file?
> 
> 3. What is the ISE simulation path?
> 
> Thanks,
> NOel

Article: 88171
Subject: Re: Cypress CY7B923/33 models
From: Klaus Falser <kfalser@durst.it>
Date: Thu, 11 Aug 2005 07:55:43 +0200
Links: << >>  << T >>  << A >>
In article <1123693516.744412.140800@g49g2000cwa.googlegroups.com>, 
ernielin@gmail.com says...
> Hi All,
> 
> I am looking for a VHDL model for the CY7B923 and CY7B933 Hotlink
> Transmitter and Receiver.  The tech support at Cypress referred me to
> Synopsys, but I can't get anything from Synopsys because I don't have a
> site ID (and thus can't register for Synopsys SolvNet).
> 
> Does anyone know another site where I can obtain the functional models?
> 
> 
> Thanks
> Ernie
> 

Hello,
as you probably know, for a new project it's much 
better and cheaper to use the newer CYP15G0101DBX chip.
We used the CY7B923/CY7B933 devices, but switched to 
the newer device without problems.  

And they seem to have a VHDL model for it, but I think 
you need to sign a NDA.

Best regards
Klaus

Article: 88172
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: "PeterC" <peter@geckoaudio.com>
Date: 10 Aug 2005 23:24:53 -0700
Links: << >>  << T >>  << A >>

OK, I'm not sure I follow your reasoning.

>From what I understand of your reply - the 13th bit, which toggles
every 8192 cycles, would be used to set the counter limit to the
"appropriate value" - either 2229 or 2230?

The 1-period pulse on the 13-th bit comes from the fact that the
counter limit is reloaded when the 13-th bit is set to 1, and when this
occurs 13-th bit is reset to 0, correct?

Could you please clarify what would be the purpose of using the 12-th
bit? I apologize for the ingnorance, but I'm thoroughly confused. I
appreciate you may not have time for a detailed response but any
further hints would be very useful.

I had envisaged using nothing more than the Xilinx counter core with a
fixed limit set at 2229. But then again additional logic would be
required to detect the case of count=2229, but I don't see any problems
here (from memory I think the counter core has a "threshold" output
which could be used for this purpose).

Yes, we are based in beautiful Sydney, about 5 minutes walking time
from Darling Harbour, and I think the submarine is still there! Not
exactly San Jose as far as technical/commercial action is concerned
though...


Article: 88173
Subject: Delays in verilog
From: "Gerr" <gertvierman@hotmail.com>
Date: 10 Aug 2005 23:36:00 -0700
Links: << >>  << T >>  << A >>

Hi,

I'm a bit confused by the do's and dont's of delay's (#) in verilog,
like the following snippet :

always @(posedge clk)
	load_r <= #1 load;

I'm trying to learn some tricks by reading other peoples code
(opencores.org, mostly), and a lot of projects are using delays like
this. All the books tell you not to use delays in verilog, though,
because it's not synthesizable.

So what's the use of those delays in code that's ment to be synthesized
?

Thanks,


Article: 88174
Subject: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 11 Aug 2005 18:51:57 +1200
Links: << >>  << T >>  << A >>
  Peter A is probably asleep now, so I'll try and reply;

PeterC wrote:
> OK, I'm not sure I follow your reasoning.
> 
>>From what I understand of your reply - the 13th bit, which toggles
> every 8192 cycles, would be used to set the counter limit to the
> "appropriate value" - either 2229 or 2230?

No, the target is now /2229

> The 1-period pulse on the 13-th bit comes from the fact that the
> counter limit is reloaded when the 13-th bit is set to 1, and when this
> occurs 13-th bit is reset to 0, correct?

Yes, the 13 th bit is effectively a synchronous carry-out, that is
hi only one clock cycle.

> Could you please clarify what would be the purpose of using the 12-th
> bit? I apologize for the ingnorance, but I'm thoroughly confused. I
> appreciate you may not have time for a detailed response but any
> further hints would be very useful.

Difference is duty cycle. 13th/cary bit is one CLK wide, or 10ns,
whilst 12th bit is going to be 1024/1205, or not far off 50%.
Both are 44.1KHz.
If you needed a clock-enable inside the FPGA, at 44KHz, then the 13th 
bit could be a better choice; if you want to clock an external ADC/DAC, 
they will prefer something around 50%

> 
> I had envisaged using nothing more than the Xilinx counter core with a
> fixed limit set at 2229. But then again additional logic would be
> required to detect the case of count=2229, but I don't see any problems
> here (from memory I think the counter core has a "threshold" output
> which could be used for this purpose).

  That would also work, but you consume more logic in doing a count==2229
compare, plus it is slower.
  The SyncCarry scheme costs one FF, and then you preset the counter 
with a value that results in a period of 2229 clocks.

-jg




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