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you probably can, but i am suggesting to use VIO.
first, its probably easier.
second its a lot of fun :)
you can instantiate it in a pretty similar manner as the previous two.
just make ICON with two control ports and connect as an example below.
though if you are using VIO you have to remove all your inputs and make
them as internal signals and then connect them to VIO. otherwise it
will give you an error message.
here's an example, good luck
entity top is
port (
clk : in std_logic;
cnt : out std_logic_vector(7 downto 0);
cost1 : out std_logic_vector(COST_SIG-1 downto 0));
end top;
architecture Behavioral of top is
-----------------------------------------------------------------------------
-- instatiating ICON
-----------------------------------------------------------------------------
signal control_bus0 : std_logic_vector(35 downto 0);
signal control_bus1 : std_logic_vector(35 downto 0);
component icon
port(
control0 : out std_logic_vector(35 downto 0);
control1 : out std_logic_vector(35 downto 0));
end component;
-----------------------------------------------------------------------------
-- instatiating VIO
-----------------------------------------------------------------------------
signal async_in : std_logic_vector(199 downto 0);
signal async_out : std_logic_vector(199 downto 0);
component vio
port(
control : in std_logic_vector(35 downto 0);
async_in : in std_logic_vector(199 downto 0);
async_out : out std_logic_vector(199 downto 0));
end component;
-----------------------------------------------------------------------------
-- instatiating ILA
-----------------------------------------------------------------------------
signal data : std_logic_vector(255 downto 0);
signal trig0 : std_logic_vector(0 downto 0);
signal trig1 : std_logic_vector(4 downto 0);
signal trig2 : std_logic_vector(0 downto 0);
component ila
port(
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(255 downto 0);
trig0 : in std_logic_vector(0 downto 0);
trig1 : in std_logic_vector(4 downto 0);
trig2 : in std_logic_vector(0 downto 0));
end component;
-----------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------
-- instatiating ICON
-----------------------------------------------------------------------------
i_icon : icon port map(
control0 => control_bus0,
control1 => control_bus1);
-----------------------------------------------------------------------------
-- instatiating VIO
-----------------------------------------------------------------------------
-- connect things that i want to control to async_out
-- (inputs)
process (async_out)
begin
vio_data_in(73 downto 0) <= async_out(199 downto 126);
end process;
-- here async_in gets signals that are coming out
-- (outputs)
async_in(0) <= cnt_sig(0);
i_vio : vio port map(
CONTROL => control_bus0,
async_in => async_in,
async_out => async_out);
-----------------------------------------------------------------------------
-- instatiating ILA
-----------------------------------------------------------------------------
-- here assign triggers
trig0(0) <= read_mem_sig;
-- here assign data
data(79 downto 64) <= cost_2;
i_ila : ila port map(
control => control_bus1,
clk => clk,
data => data,
trig0 => trig0,
trig1 => trig1,
trig2 => trig2);
-----------------------------------------------------------------------------
end Behavioral;
Article: 87701It works! My script is much cleaner now. :D Thanks.Article: 87702
Can one use the JTAG-USB cable from digilent with chipscope ? SumitArticle: 87703
Peter Alfke wrote: > Methi, you have received many suggestions from this group. Perhaps it > is time to tell us which ones you have tried or are going to try. It > seems to me that the original title of this thread has become > meaningless. You can fit your design many times over into the quoted > device... > Peter Alfke, Xilinx Applications Thankyou everybody...for all the suggestions I have received lots of help I am first tryint the BlockRAM And am also goin to try the simple counter... Thankyou once again MethiArticle: 87704
Brandon wrote: > Does XST 7.1 support TCL scripting? I would imagine that it does; the Xilinx installer includes a tcl shell. > I don't see any mention of it in the XST User Manual and I find the > command line mode to be very awkward performing synthesis using the GUI > or command line without a script. > > I'm new to XST, and I'm looking for ways to organize my synthesis > process. By default the tool dumps all of synthesis files all over the > place, ugh. I was hoping I could have some control over all this, which > I could do it. I hate how the tools dump things all over the place, too. Calling the various programs from a script can help with that but it's not ideal. > If anyone has any recommendations to using XST in command line I'm all > ears. The GUI is useful for initial project set-up. Among other things, if you look carefully you'll see the exact command line for each of the various processes. The GUI is also helpful when creating constraints and for interactively driving the timing analyzer. I've created a couple of makefiles (one for FPGAs, one for CPLDs) that I use under cygwin to synthesize and build my chips. "make cleanup" gets rid of all of the excess files and directories (I found a list of the files buried in the Xilinx docs). It took awhile to figure out what does what and where. I couldn't figure out what xflow was doing, so my makefile calls the individual programs as needed. -aArticle: 87705
No. It does work with the Digilent Adept Suite. do_not_reply_to_this_addr@yahoo.com wrote: > > Can one use the JTAG-USB cable from digilent with chipscope ? > > SumitArticle: 87706
> The GUI is useful for initial project set-up. Among other things, if > you look carefully you'll see the exact command line for each of the > various processes. The GUI is also helpful when creating constraints > and for interactively driving the timing analyzer. There is .cmd_log file that logs every command was run. > I've created a couple of makefiles (one for FPGAs, one for CPLDs) that > I use under cygwin to synthesize and build my chips. "make cleanup" > gets rid of all of the excess files and directories (I found a list of > the files buried in the Xilinx docs). It took awhile to figure out > what does what and where. Search for *.gfl file, which has a list of most (if not all) of the intermediate files. HTH, JimArticle: 87707
In article <1122377144.005204.205540@g47g2000cwa.googlegroups.com>, sabatian@libero.it says... > Hi all, > > I am looking for information about licensing of HW designs. <snip > I read on the OpenCores web site that > they refer to the GPL licence but after having read it on > http://www.gnu.org I have a lot of questions. <snip> Curious about gpl, I found this transcription of the Massachusetts Software Council's Open Source Summit. Quote: "to facilitate a dialog between professionals who are engaged in efforts around the topic of open source". End Quote. http://www.groklaw.net/article.php?story=20050727214837480 It's discussion may cover some of your questions. -- James HarryArticle: 87708
"Peter K." <p.kootsookos@iolfree.ie> writes: > Randy Yates wrote: >> >> It's a fact. >> > > I doubt it! Our marketplaces (or those of the companies we work for) > are quite different... If you still think I work for Sony Ericsson, you'd be wrong. -- % Randy Yates % "Though you ride on the wheels of tomorrow, %% Fuquay-Varina, NC % you still wander the fields of your %%% 919-577-9882 % sorrow." %%%% <yates@ieee.org> % '21st Century Man', *Time*, ELO http://home.earthlink.net/~yatescrArticle: 87709
Jim Granville wrote: > austin wrote: > > Marc, > > > > It turns out that if you are going only to the DFS, and you do not move > > the frequency very fast, you can sweep from min to max input (output) > > frequency before losing lock. > > > > The DLL is fussier, as it chooses to arrange its six delay lines based > > on what options, range, and where it locks. So in the DLL, if you > > start sweeping the frequency, you may get an overflow or underflow on > > one of the delay lines, and lose lock. > > > > We typically spec +/- 100 ppm, because just about any trashy crystal > > can do that. In reality, +/- .01 is probably safe. Thank you for the response, Austin. > Austin, > Suppose the clock starts as 'any trashy crystal', but is then fed via > another Xilinx DLL - is there a chain-limit of jitter degradation, in > such a system ? > This will become a more common scenario... Howdy Jim, Indeed it is. Not to put words in his mouth, but I suspect that Austin did not mean to imply that crystal oscillators had a large amount of jitter. I took "trashy" to refer to cheap XO's that typically have wide ppm tolerance's (+/- 100 ppm, for example). Even cheap XO's should have relatively low jitter (compared with a DLL)... so meeting the jitter tolerance requirement in the datasheet shouldn't generally be a problem (at least for the first DLL). Have fun, MarcArticle: 87710
johnp wrote: > Has anyone seen any timing specs for the V4 local/regional clocks? > I don't see anything in the data sheets. I'm interested in the > clock to Q output delay from a local clock pad to an output pad, > obviously without using a DCM. I'll probably be using the output > SERDES capabilities of the IOB as well. Howdy John, Since no one has responded, I'll take a stab. Tickofcs, mentioned in table 59, seems like what you need - except that the table entry is blank (a little annoying considering that the devices have "been in production" since Feburary). You should be able to manually add up the various prop delays and come up with a ballpark number. An offset constraint would confirm it. Just to throw around some numbers, I estimate the prop delays through the IBUF, BUFIO, to the OSERDES total about 2.1 ns max... so after you add the clock to out of the OSERDES, you have about 2.7 ns (max) total. If you go through the BUFR as well, add another 0.5 ns or so. Have fun, MarcArticle: 87711
ALuPin@web.de wrote: > Hi, > > in Quartus there is an option "Remove Duplicate Registers / Remove > Duplicate Logic". > > Is there something similar in Lattice ispLEVER 5.0 SP1 ? > I want the fitter to keep duplicate registers but I do know where > to make that setting. > > Thank you. > > Rgds > Andr=E9 Hi: Please follow the setup. Assignments =3D> Settings =3D> Analysis & Synthesis Settings =3D> More Settings =3D> Remove Duplicate Register=20 Regards AlexArticle: 87712
Does anybody know whether it's possible to configure a slice in a V2PRO as a 2-bit memory element such that you can have separately addressable read and write ports, but not a write port output? ie, sort of like a RAM16X1D, but with no SPO port, and two bits wide in two LUTS, instead of 1 bit wide in two LUTs. It kind of looks like it might be possible, looking at fpga_editor and P48 of the V2P datasheet, but I don't see a clear way to do it - so I was wondering whether or not it could be done? (On a related note - would MC15 be useful for getting more bits out of a RAM element? The docs indicate its use as an alternate for D in an SRL configuration) Thanks, JeremyArticle: 87713
Antti Lukats wrote: > "Yaju Nagaonkar" <yaj_n@hotmail.com> schrieb im Newsbeitrag > news:1122330050.620218.117110@g47g2000cwa.googlegroups.com... > >>I guess I have lot to catch up on in the FPGA technolgy area.I just >>learnt about FPSLIC, as Atmel has been advertising it as a better FPGA >>choice in recent magazines. >> >>Although I have not used FPSLIC, I am curious whether, it is easy to >>port VHDL for Xilinx (used at my univ.) to FPSLIC? >> >>Also in term of soft-core processors, are there FPGA-portable open >>source soft-core processors to download to FPGAs? If there are, wouldnt >>those be a good choice for benchmark studies with different FPGAs? >> >>Are most of the open-cores (example: opencores.org) designed >>specifically for fpga brand (xilnx/alterra)? >> >>Thank you for your answers and helping me learn more about FPGA >>technolgies. >> >>-Yaju >> > > > most open cores are not FPGA dependant or can be modified easily to work for > different FPGAs. > as of Atmel FPSLIC - this is the almost only FPGA where the FPGA vendor does > not provide free software. > and the software doesnt work also, almost impossible to use. > > Antti > > > > > > > Although an open core soft-processor might be written in a vendor independent manner, the underlying differentiator will be the synthesis tools. If you synthesize the same core for different vendors using the same synthesis tool you will get results that differ quite wildly for different FPGAs (from the same or different vendors). It is inevitable that you will have to hand tweak the source code for the particular FPGA being targeted to achieve maximum results. Alternatively, you can use a synthesis tool that is not only favorable to the chosen vendor of the targeted FPGA, but one that understands the style of VHDL/Verilog code that the core is written in. Regards BenArticle: 87714
Thank you for your answer, but settings in Quartus are very clear. I want to know if there are such settngs in Lattice ispLEVER . Rgds Andr=E9Article: 87715
Hi, I have one more question about placing registers: If I have a bidirectional bus do I have to make the decision whether to place the "input"bus into input registers (for better tSU/tH) or whether to place the "output" bus into output registers (for better tCO) ? Or is there some option for both ? I can imagine of situations when using input AND output registers could be necessary, Thank you for your answers. RgdsArticle: 87716
Hi Duane,
I much appreciate your help.
Duane Clark wrote:
>> I want to use the SRAM in a pipeline manner, capturing the data from
>> the previous read in the same cycle that I present new data. Assuming
>> the delay of getting my address to the SRAM is roughly equivalent to
>> the delay getting the data back I should only have to worry about the
>> tOH (data hold time) of the SRAM being large enough.
>
> I think you have a fundamental misunderstanding there. The two delays
> mentioned add up, and along with the input setup time, need to be less
> than the clock cycle time. For the 100MHz clock previously mentioned,
> they do not.
I think I'm starting to understand it. While I'm still using it in a
pipelined manner (latching the previous data while presenting a new
address), I see now that I need to allow for additional timing margin.
Is it correctly understood though, that if I _didn't_ use it this way,
but instead held the address stable while I latched the data, I wouldn't
be able to achieve the same memory bandwidth?
So I wonder what Altera means when they write zero-wait-states? In
other words, what kind of bandwidth does Nios sees when using this 10ns
async sram?
> You seem to have switched boards on me, and I don't have Altera specs
> handy. But on the previous board mentioned with a Virtex2P chip, the
> registered inputs do not even have a hold time requirement, only the
> setup time.
Sorry, no trickery intended. I have two Xilinx boards, but it's my
Altera board I use the most. AFAICT, both X and A are very similar and
both have zero hold time.
> Yes, 20nS should be enough if the only thing there is the SRAM, and
> assuming the Altera timing is similar to the Xilinx timing. But you need
> to check several thing. First, when you say the flash and ethernet are
> fully disabled, do you mean they are never enabled? Have you verified
> that is really the case?
To the best of my knowledge:
...
assign flash_cs_n = 1'b1;
assign flash_oe_n = 1'b1; // Unnecessary?
assign enet_aen = 1'b1;
assign enet_be_n = 4'b1111; // Unnecessary?
...
where
set_location_assignment PIN_A12 -to flash_cs_n
set_location_assignment PIN_B12 -to flash_oe_n
set_location_assignment PIN_B15 -to enet_aen
set_location_assignment PIN_C16 -to enet_be_n[0]
set_location_assignment PIN_B16 -to enet_be_n[1]
set_location_assignment PIN_D16 -to enet_be_n[2]
set_location_assignment PIN_E16 -to enet_be_n[3]
in the constraints file. Of course, the Nios Dev Kit documentation is
needed to verify this assignment. In case you're interested, the whole
thing is not that big and I've put it up on
http://numba-tu.com/sram
> Have you verified that all signals to and from the SRAM are registered
> within the IOBs of the FPGA? Including the data output enable signals? I
> assume Altera has something similar to FPGA editor to make sure this is
> really the case.
Good point, I haven't yet. (Though I doubt that's the problem, given
that it works for 24 out of 32 bits :-)
> Assuming that ALL inputs and outputs, including output enables, are
> registered, then timing constraints on external pins are completely
> irrelevant, and will have absolutely no effect. The timing is fixed, and
> can be obtained from the FPGA data sheet. In general, you should be
> registering all these signals within the IOBs. You should need a very
> good reason not to.
D'oh! It's so obvious now that you point it out. Excellent.
Thank you,
Tommy
Article: 87717Problem solved: if you set a constraint file in which you specify an input oder output delay, the Synplify Pro synthesis report will give a frequency estimation.Article: 87718
ALuPin@web.de writes: > Hi, > I have one more question about placing registers: > > If I have a bidirectional bus do I have to make the decision > whether to place the "input"bus into input registers (for better > tSU/tH) or whether to place > the "output" bus into output registers (for better tCO) ? > Or is there some option for both ? > You can register both, but the target silicon will dictate whether you get the performance you want. For example, the Flex10K architecture only has one flop in the IO cell, so the other has to go in teh fabric. Altera claim this is mitigated by the fast local interconnect, but I could never get the timing to be reliable over all temp/voltage/process for a 100MHz SDRAM interface. I either met tsu because the input register was packed in the IO cell, or tco, because the output one was. I could never persuade the software to place the "other" register close enough in the fabric to meet timing. Still, it worked in the environment we needed it to in the end - so long as it didn't get too hot. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 87719
Hi Vladislav, now I solved my problem: I used 4 DCMs (2 BUFGs each), but I thought it were only 3 (copy and paste mistake at own IPs). That's why I run out of BUFGs. > Stefan, > > You cannot have 9 GCLKs, as S3 has only 8, yet there are only 8 BUFGs. > You may have a limitation of interconnect between DCMs and respective BUFGs. > > Can you explain a bit more? > > Vladislav > > > "Stefan" <holzi_stefan@hotmail.com> wrote in message > news:dca9si$hdu$1@wsc10.lrz-muenchen.de... > > Hi everyone, > > > > in my design on a Spartan3 there are 9 GCLKs used, but there are only 8 > > available. Is the number of GCLKs related to the BUFG, or where can I > > change > > the design to use fewer of these global clocks. (I'm just using one single > > system clock at 100 MHz, but some BUFGs for DCMs, but not too much). > > Anyone can help? > > > > Thanks in advance, > > > > Stefan > > > > > >Article: 87720
Andy Peters schrieb: > Brandon wrote: > > Does XST 7.1 support TCL scripting? > > I would imagine that it does; the Xilinx installer includes a tcl > shell. > Can anybody confirm that ISE can be run with a TCL script? I was looking for that option and did not find anything? I am using a Makefile now, but that is not enough, as the synthesis tool requires its own script files. What makes it even harder is the fact that one tool uses a different device specification format as the other. For example, calling the map or ngbuild tool a Spartan 3 is given as: xc3s50-tq144-4. Where as in the synthesis script it needs to be specified as: xc3s50-4-tq144. Having those different files makes it really tedious to do changes. GuenterArticle: 87721
Hi Brandon, > Does XST 7.1 support TCL scripting? This doesn't help at all, but all Altera's design tools (even Altera's free Web Edition) have TCL scripting built-in. Altera even included matching Tk libs to build your own GUI. Plus, the Quartus GUI will even generate a TCL file for your current project that compiles the whole design for you. Alternatively, you can also use some form of Make if you want. All this is useless when targeting a Xilinx device, of course ;-) Best regards, BenArticle: 87722
Hi
I need some more help --:
Based on original counter (VHDL 1) and your template (VHDL 2, Thankyou
:).....VIO, ILA, ICON are generated.
It is not clear for me to how to make VIO work --:
My goal is
- to drive "internal reset input signal" to <'1' ---> '0'> (or '0' from
beginning) using VIO and
- to see the proper waveform in 'Analyzer'.
It seems that it is problematic for VIO to add virtual input to
internal reset signal.
Thankyou again for the help. Regards
BTW, Mapping process does not create any warning, while synthesis
process generates following warnings.
=========================================================================
* Low Level Synthesis
*
=========================================================================
Launcher: "ila.ngo" is up to date.
Launcher: "vio.ngo" is up to date.
Launcher: "icon.ngo" is up to date.
WARNING:Xst:1474 - Core <ila> was not loaded for <i_ila> as one or more
ports did not line up with component declaration. Declared input port
<control<35>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <vio> was not loaded for <i_vio> as one or more
ports did not line up with component declaration. Declared input port
<control<35>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1474 - Core <icon> was not loaded for <i_icon> as one or
more ports did not line up with component declaration. Declared output
port <control0<3>> was not found in the core. Please make sure that
component declaration ports are consistent with the core ports
including direction and bus-naming conventions.
WARNING:Xst:1291 - FF/Latch <counter_35> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_32> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_33> is unconnected in block <top>.
WARNING:Xst:1291 - FF/Latch <counter_34> is unconnected in block <top>.
*********** VHDL 1
***********************************************************
---------------------------------------------------------------------------------------------
-- Design under "simulation"
-- Original 4 bit (internally 36bit) counter
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
(
clk : in std_logic;
cnt : out std_logic_vector(3 downto 0)
);
end top;
architecture behave of top is
signal counter : std_logic_vector(35 downto 0):= (others => '0');
signal rst_tmp: std_logic:='0'; -- internal reset signal
begin
process(rst_tmp,clk)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;
cnt <= counter(31 downto 28);
end behave;
-------------------------------------------------------------------------------
******* VHDL 2 ************************************************
----------------------------------------------------------------------
-- Design under Verification
-- 4 bit counter (internally 36 bit counter)
-- With internal "reset" input signal
-- VIO, ICON, ILA : Core generated
--------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
(
clk : in std_logic;
cnt : out std_logic_vector(3 downto 0)
);
end top;
architecture behave of top is
signal counter : std_logic_vector(35 downto 0):= (others => '0');
signal rst_tmp : std_logic:='0';
--- ICON declaration ------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal control1 : std_logic_vector(35 downto 0);
component icon
port
( control0 : out std_logic_vector(35 downto 0);
control1 : out std_logic_vector(35 downto 0) );
end component;
--------------------------------------------------------
--- ILA declaration ------------------------------------
signal data : std_logic_vector(3 downto 0);
signal trig0 : std_logic_vector(3 downto 0);
component ila
port
( control : in std_logic_vector(35 downto 0);
clk : in std_logic;
data : in std_logic_vector(3 downto 0);
trig0 : in std_logic_vector(3 downto 0) );
end component;
--------------------------------------------------------
---- VIO declarations ----------------------------------
signal sync_in : std_logic_vector(3 downto 0);
signal async_out : std_logic_vector(0 downto 0);
component vio
port
( control : in std_logic_vector(35 downto 0);
clk : in std_logic;
async_out : out std_logic_vector(0 downto 0);
sync_in : in std_logic_vector(3 downto 0) );
end component;
---------------------------------------------------------
begin
process(rst_tmp,clk)
begin
if rst_tmp='1' then
counter <= (others => '0');
elsif ( clk'event and clk = '1' ) then
counter <= counter + 1;
end if;
end process;
cnt <= counter(31 downto 28);
---- ICON instantiation -------------
i_icon : icon
port map
( control0 => control0,
control1 => control1 );
--------------------------------------
--- ILA instantiation ------------
trig0(0) <= counter(0);
trig0(1) <= counter(1);
trig0(2) <= counter(2);
trig0(3) <= counter(3);
data(0) <= counter(0);
data(1) <= counter(1);
data(2) <= counter(2);
data(3) <= counter(3);
i_ila : ila
port map
( control => control0,
clk => clk,
data => data,
trig0 => trig0 );
-----------------------------------
---- VIO intantiation -------------
rst_tmp <= async_out(0); -- this part is wierd
sync_in(0) <= counter(0);
sync_in(1) <= counter(1);
sync_in(2) <= counter(2);
sync_in(3) <= counter(3);
i_vio : vio
port map
( control => control1,
clk => clk,
async_out => async_out,
sync_in => sync_in );
-----------------------------------
end behave;
****************************************************************
Article: 87723
ALuPin@web.de wrote:
> If I have a bidirectional bus do I have to make the decision
> whether to place the "input"bus into input registers (for better
> tSU/tH) or whether to place
> the "output" bus into output registers (for better tCO) ?
> Or is there some option for both ?
Registers are inferred from the code,
only placement can be constrained.
If I use both input and output registers
then I usually only need Fmax as a constraint and
I can let the place and route pick the
register location. Without an input
register, timing constraints are more
complicated.
-- Mike Treseler
Article: 87724When should we see VDHL 200x incorporated in our EDA tools?
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