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I'm really sorry for late reply about your help. A few days ago, I've installed the service pack 1(SP1) as someone's comment. And then I made a new project with same source ion the SP1. Surprisingly, everything worked fine !! I quess that someting keeps the lock on the configuration pins on the user-mode at no service pack version. But I don't know the exact cause. Anyway, a little bit late, I appreciate you, Adam. If you know the usage of "asmi_parallel" ip core, I'd like get some advice about using "write operation". There are two kind of write operation as below. 1) single byte write operation 2) page write operation (2~256 byte) When I used the page write operation with 256 byte PAGE_SIZE, the "busy" signal (it's "doing" output from asmi_parallel ip core) keeps "high" during 30us after write command. Strangely, when I tried to use single byte write operation, the "busy" signal keeps "high" during 300us after write command !! I cannot believe it and its time is different from the data sheet. On the data sheet, the "busy" high time is shown as about 3 us on the single byte write operation.. It bothers me not to select actual write operation at this time. If you have advice for me, please donot hesitate. Thanks in advanced Regards Paul >Hi Paul, > >Any progress ? > >Adam > >> Hi Paul, >> >> First of all try to use Indirect flash programming using jtag interface. >> If it will work fine your EPCS is connected correctly and your fpga >> should start automatically. >> If not , check epcs connection to fpga and msel pins configuration. >> >> Second step is to write and read back epcs config using your rs connection. >> >> Then you have to prepare flash image using >> sof2flash" --epcs --input="example.sof" --output="example.flash" >> >> Adam >> >>> Hi,all >>> >>> I'm Paul Ham in Korea and have some difficulties in using ASMI_PARALLEL >>> altera ip core. >>> Anyone who knows well this problem could advice to me. >>> >>> I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service pack. >>> My design is very simple like below : >>> 1) receive the data from PC via RS232. >>> The data is .rpd file made by Conver Programming Files of Quartus menu. >>> Due to the EPCS spec, its size is 512KByte. >>> 2) write the data to internal dpram. (double buffering) >>> 3) read the data from dpram to asmi_parallel every 256 bytes.(page write) >>> >>> When I simulated it with signaltap, it wrote other .rpd file into EPCS4 >>> well. >>> And it configured well after power-up. >>> >>> But it didn't work when I programmed itself directly to EPCS4. >>> It always generate the illegal_erase and illegal_write. >>> >>> I found some ways to solve the problem like below but anything didn't >>> work >>> well. >>> 1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS >>> REGULAR IO" at .qsf file. >>> -> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS >>> REGULAR IO" >>> set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS >>> REGULAR IO" >>> set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS >>> REGULAR IO" >>> set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION >>> "USE AS REGULAR IO" >>> 2) modify the value of "ncs_reg" in asmi_parallel.v as below. >>> -> always @ ( negedge clkin_wire or posedge end_ophdly) >>> if (end_ophdly == 1'b1) ncs_reg<= 1'b1; >>> else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0; >>> 3) install the service pack 1 : I didn't try it >>> >>> I guess that the problem is related to the setting of 4 configuration >>> pins. >>> But I'm not sure what could I do. >>> If you have any advice or solution, please let me know. >>> >>> Thanks advance >>> Regards >>> Paul >>> >>> >>> >>> >>> --------------------------------------- >>> Posted through http://www.FPGARelated.com >> > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149201
On 10/4/2010 1:11 AM, Alexander Kane wrote: > Hello. > I'm currently coming to the end of my last semester of my four year > engineering degree in electronics and computer systems engineering. > I've really enjoyed working with FPGAs as part of my degree and am now > tutoring the FPGA course. Basically I want to start a career working > with FPGAs, but am not sure how to go about it. I live in New > Zealand, but as the job market here is so small I'm looking at Europe > (as I speak both English and German I figure that opens up several > countries I could work in). Does anyone have any suggestions or > advice as to how I go about entering such a career, or what kind of > options are out there, or even websites I can look for jobs on? > Thanks in advance. > - Alexander Hi Alexander, I've got a mate who works in NZ for this lot. http://www.taitworld.com/main/index.cfm/1,111,0,44,html/Jobs-Christchurch-NZ As well as keeping me up-to-date with Paul Henry's latest gaffes, he sent me that job link a while back. I'm assured that there are still some bits of Christchurch left standing. HTH., Syms.Article: 149202
hi . I can't know english very well,so excuse me. I have xc5vfx100t board.I generate pci express core with vendo id=0x10EE, device id =0x0007 , frequency(MHZ)=125, lane with=x4 . then implement and program on flash board,set s5(PCI express clock select) on board to 111 until get 125 MHz when input = 100 MHz. then plug into x4 slot motherboard ,pc detect pci express root port3-2944 but didn't detect as xilinx device. I change vedor id=8086 , device id=2944 ,so detect it as xilinx device.why with vendor id =0x10EE dedn't detect? but in windriver display BAR0,BAR1 while I select BAR2 as a memory 64 bit. when I plug into motherboard test my sihnal's core by chipscope,core doesn't have clk and link up didn't assert,why???????? please help me,I completely confuse, --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149203
hello
i am trying to synthesize the following code.i am creating 4 different
clocks by clock division and then i want to get different led outputs
according to switches change in my virtex2pro fpga
i am kind of new to vhdl and i get the following error
ERROR:Xst:827 - "C:/Xilinx91i/lab3/lcok.vhd" line 150: Signal LEDS<0>
cannot be synthesized, bad synchronous description.
here is my code
entity lock is
Port ( SWITCHES : in STD_LOGIC_VECTOR (3 downto 0);
RESET : in STD_LOGIC;
fpga_clock: in STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (3 downto 0));
end lock;
architecture Behavioral of lock is
signal cur_state: std_logic_vector(2 downto 0);
signal next_state: std_logic_vector(2 downto 0);
signal state1s,state2s,state10s,state_miso,state_tetarto: std_logic;
signal clk,clk_1s,clk_2s,clk_10s,clk_miso,clk_tetarto,blink1: std_logic;
begin
process(fpga_clock)
variable counter2 : integer range 0 to 100000000;
variable counter1 : integer range 0 to 50000000;
variable counter_miso : integer range 0 to 25000000;
variable counter_tetarto : integer range 0 to 12500000;
-- variable a:integer:=0;
begin
-- if (a<1) then cur_state<="000"; else cur_state<=cur_state; end if;
-- a:=a+1;
if (rising_edge(fpga_clock)) then
if (counter1=50000000) then
if (state1s = '1')then
state1s<='0';
clk_1s<='1';
else
state1s<='1';
clk_1s<='0';
end if;
counter1:=1;
else
counter1 := counter1 +1 ;
end if;
if (counter2=100000000) then
if (state2s = '1')then
state2s<='0';
clk_2s<='1';
else
state2s<='1';
clk_2s<='0';
end if;
counter2:=1;
else
counter2 := counter2 +1 ;
end if;
if (counter_miso=25000000) then
if (state_miso = '1')then
state_miso<='0';
clk_miso<='1';
else
state_miso<='1';
clk_miso<='0';
end if;
counter_miso:=1;
else
counter_miso := counter_miso +1 ;
end if;
if (counter_tetarto=12500000) then
if (state_tetarto = '1')then
state_tetarto<='0';
clk_tetarto<='1';
else
state_tetarto<='1';
clk_tetarto<='0';
end if;
counter_tetarto:=1;
else
counter_tetarto := counter_tetarto +1 ;
end if;
end if;
if (reset = '1') then
cur_state <= "000";
end if;
CASE SWITCHES IS
WHEN "0110" => if (cur_state = "000") then cur_state<="001" ;
end if;
WHEN "1001" => if (cur_state = "001") then cur_state<="010" ;
end if;
WHEN "1010" => if (cur_state = "010") then cur_state<="011" ;
end if;
WHEN "0101" => if (cur_state = "100") then cur_state<="101" ;
end if;
WHEN OTHERS => cur_state<="100";
end case;
if ((cur_state = "101") and (reset = '1')) then
cur_state<= "000";
else cur_state<="100";
end if;
next_state<=cur_state;
end process;
process(next_state)
variable seq:integer:=0;
variable c:integer:=0;
begin
CASE next_state IS
WHEN "000" => if ((clk_2s='1') and (c < 1)) then
LEDS(3 downto 0) <= "0000";
c:=c+1;
else if (clk_1s='1') then
LEDS(2 DOWNTO 0)<= NOT ("000");
LEDS(3)<='1';
else
LEDS(3) <='0';
end if;
end if;
WHEN "001" => if (clk_1s = '1') then
LEDS(1 DOWNTO 0)<= "11";
LEDS(3 downto 2)<="11";
else
LEDS(3 downto 2) <="00";
end if;
WHEN "010" => if (clk_1s = '1') then
LEDS(0)<= '1';
LEDS(3 downto 1)<="111";
else
LEDS(3 downto 1) <="000";
end if;
WHEN "011" => if (clk_miso = '1') then
LEDS(3 downto 0)<="1111";
else
LEDS(3 downto 0) <="0000";
end if;
WHEN "100" => if (rising_edge(clk_tetarto)) then
if (seq=0) then
LEDS<= "0111";
seq:=1;
else if
(seq=1) then
LEDS<= "1011";
seq:=2;
else if
(seq=2) then
LEDS<= "1101";
seq:=3;
else if
(seq=3) then
LEDS<= "1110";
seq:=0;
end if;
end if;
end if;
end if;
end if;
WHEN OTHERS => LEDS<="0101";
end case;
end process;
end Behavioral;
any help would be appreciated!
thank you
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 149204
Hello Airol,
Your problem most likely lies within the following chunk of code:
case rdy_out_i is
when '0' => slv_reg1 <= (others => '0');
when '1' => slv_reg1 <= dct_2d_i;
when others => slv_reg1 <= (others => '0');
end case;
Are you sure, that you hold dtc_2d asserted long enough, while you
read slv_reg1 through the IPIC interface back to your MicroBlaze/PPC?
Try the following:
case rdy_out_i is
when '0' => slv_reg1 <= (others => '1');
when '1' => slv_reg1 <= dct_2d_i;
when others => slv_reg1 <= (others => '0');
end case;
If you read X"FFFF" you will have your answer.
Regards,
Kim P.
On Thu, 7 Jan 2010 03:12:20 -0800 (PST), airol <hairoljb@gmail.com>
wrote:
>Hello there,
>
>I'm adding custom IP (DCT core) to EDK 9.1. Input (xin) is write to
>slv_reg0 while output (dct2d_out) is write to slv_reg1.
>
>I'm following a tutorial from
>http://www.ee.cooper.edu/~stefan/projects/tutorials/edk_custom_ip/edk_custom_ip.pdf
>
>I can write and read from the slv_reg0 (for input, xin), but I cannot
>read the value from slv_reg1 (for dct2d_out). The output enable,
>rdy_out is used to enable writing dct2d_out value to the slv_reg1.
>
>Can anyone point me out any correction should i make.
>
>Thanks in advance.
>
>=============================================
>user_logic.vhd
>
>------------------------------------------------------------------------------
>-- user_logic.vhd - entity/architecture pair
>------------------------------------------------------------------------------
>
>-- DO NOT EDIT BELOW THIS LINE --------------------
>library ieee;
>use ieee.std_logic_1164.all;
>use ieee.std_logic_arith.all;
>use ieee.std_logic_unsigned.all;
>
>library proc_common_v2_00_a;
>use proc_common_v2_00_a.proc_common_pkg.all;
>-- DO NOT EDIT ABOVE THIS LINE --------------------
>
>--USER libraries added here
>
>------------------------------------------------------------------------------
>-- Entity section
>------------------------------------------------------------------------------
>
>entity user_logic is
> generic
> (
> -- ADD USER GENERICS BELOW THIS LINE ---------------
> --USER generics added here
> -- ADD USER GENERICS ABOVE THIS LINE ---------------
>
> -- DO NOT EDIT BELOW THIS LINE ---------------------
> -- Bus protocol parameters, do not add to or delete
> C_DWIDTH : integer := 32;
> C_NUM_CE : integer := 2
> -- DO NOT EDIT ABOVE THIS LINE ---------------------
> );
> port
> (
> -- ADD USER PORTS BELOW THIS LINE ------------------
> --USER ports added here
> -- ADD USER PORTS ABOVE THIS LINE ------------------
>
> -- DO NOT EDIT BELOW THIS LINE ---------------------
> -- Bus protocol ports, do not add to or delete
> Bus2IP_Clk : in std_logic;
> Bus2IP_Reset : in std_logic;
> Bus2IP_Data : in std_logic_vector(0 to
>C_DWIDTH-1);
> Bus2IP_BE : in std_logic_vector(0 to
>C_DWIDTH/8-1);
> Bus2IP_RdCE : in std_logic_vector(0 to
>C_NUM_CE-1);
> Bus2IP_WrCE : in std_logic_vector(0 to
>C_NUM_CE-1);
> IP2Bus_Data : out std_logic_vector(0 to
>C_DWIDTH-1);
> IP2Bus_Ack : out std_logic;
> IP2Bus_Retry : out std_logic;
> IP2Bus_Error : out std_logic;
> IP2Bus_ToutSup : out std_logic
> -- DO NOT EDIT ABOVE THIS LINE ---------------------
> );
>end entity user_logic;
>
>------------------------------------------------------------------------------
>-- Architecture section
>------------------------------------------------------------------------------
>
>architecture IMP of user_logic is
>
> --USER signal declarations added here, as needed for user logic
> component dct
>
> PORT (
>
> CLK : IN std_logic;
>
> RST : IN std_logic;
>
> xin : IN std_logic_vector(7 downto 0); --
>8 bit input.
>
> dct_2d : OUT std_logic_vector(11 downto 0);
>
> rdy_out : OUT std_logic);
>
> END component;
>
> ------------------------------------------
> -- Signals for user logic slave model s/w accessible register
>example
> ------------------------------------------
> signal slv_reg0 : std_logic_vector(0 to
>C_DWIDTH-1);
> signal slv_reg1 : std_logic_vector(0 to
>C_DWIDTH-1);
> signal slv_reg_write_select : std_logic_vector(0 to 1);
> signal slv_reg_read_select : std_logic_vector(0 to 1);
> signal slv_ip2bus_data : std_logic_vector(0 to
>C_DWIDTH-1);
> signal slv_read_ack : std_logic;
> signal slv_write_ack : std_logic;
>
> signal dct_2d_i : std_logic_vector(0 to 11);
> signal rdy_out_i : std_logic;
>
>begin
>
> --USER logic implementation added here
>dct_0 : dct
>
> port map (
>
> CLK => Bus2IP_Clk,
>
> RST => Bus2IP_Reset,
>
> xin => slv_reg0(0 to 7),
>
> dct_2d => dct_2d_i,
>
> rdy_out => rdy_out_i
>
> );
>
>
> slv_reg_write_select <= Bus2IP_WrCE(0 to 1);
> slv_reg_read_select <= Bus2IP_RdCE(0 to 1);
> slv_write_ack <= Bus2IP_WrCE(0);-- or Bus2IP_WrCE(1);
> slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
>
> -- implement slave model register(s)
> SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
> begin
>
> if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
> if Bus2IP_Reset = '1' then
> slv_reg0 <= (others => '0');
>-- slv_reg1 <= (others => '0');
> else
> case slv_reg_write_select is
> when "10" =>
> for byte_index in 0 to (C_DWIDTH/8)-1 loop
> if ( Bus2IP_BE(byte_index) = '1' ) then
> slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data
>(byte_index*8 to byte_index*8+7);
> end if;
> end loop;
>-- when "01" =>
>-- for byte_index in 0 to (C_DWIDTH/8)-1 loop
>-- if ( Bus2IP_BE(byte_index) = '1' ) then
>-- slv_reg1(byte_index*8 to byte_index*8+7) <=
>Bus2IP_Data(byte_index*8 to byte_index*8+7);
>-- end if;
>-- end loop;
> when others => null;
> end case;
> end if;
> end if;
>
> end process SLAVE_REG_WRITE_PROC;
>
> write_enable_process : process (Bus2IP_Clk) is
> begin
>
> if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
>
> if Bus2IP_Reset = '1' then
> slv_reg1 <= (others => '0');
> else
> case rdy_out_i is
> when '0' => slv_reg1 <= (others => '0');
> when '1' => slv_reg1 <= dct_2d_i;
> when others => slv_reg1 <= (others => '0');
> end case;
> end if;
> end if;
>
> end process write_enable_process;
>
>-- slv_reg1(13 to 15) <= (others => '0');
>
> -- implement slave model register read mux
> SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
>slv_reg1 ) is
> begin
>
> case slv_reg_read_select is
> when "10" => slv_ip2bus_data <= slv_reg0;
> when "01" => slv_ip2bus_data <= slv_reg1;
> when others => slv_ip2bus_data <= (others => '0');
> end case;
>
> end process SLAVE_REG_READ_PROC;
>
> ------------------------------------------
> -- Example code to drive IP to Bus signals
> ------------------------------------------
> IP2Bus_Data <= slv_ip2bus_data;
> IP2Bus_Ack <= slv_write_ack or slv_read_ack;
> IP2Bus_Error <= '0';
> IP2Bus_Retry <= '0';
> IP2Bus_ToutSup <= '0';
>
>end IMP;
>
>========================================================
>
>========================================================
>
>my software application code.
>
>#include "xparameters.h"
>#include "stdio.h"
>#include "my_dct.h"
>#include "xbasic_types.h"
>
>Xuint32 *baseaddr_p = (Xuint32 *)XPAR_MY_DCT_0_BASEADDR;
>
>int main()
>{
>
>
> Xuint32 baseaddr, i;
>
>
>
> // Check that the peripheral exists
>
>
>
> XASSERT_NONVOID(baseaddr_p != XNULL);
>
> baseaddr = (Xuint32) baseaddr_p;
>
> Xuint16 data[8], data_read;
>
> data[0]=0x28;
>
> data[1]=0x21;
>
> data[2]=0x21;
>
> data[3]=0x16;
>
> data[4]=0x1A;
>
> data[5]=0x28;
>
> data[6]=0x24;
>
> data[7]=0x1A;
>
> for(i=0; i<8; i++)
> {
> MY_DCT_mWriteSlaveReg0(baseaddr, data[i]);
> data_read = MY_DCT_mReadSlaveReg0(baseaddr);
> xil_printf("data write to reg0: 0x%04X\r\n", data_read);
> }
>
>
> for(i=0; i<8; i++)
> {
> data_read = MY_DCT_mReadSlaveReg1(baseaddr);
> xil_printf("data read from reg1: 0x%04X\r\n", data_read);
> }
>
> return 0;
>
>}
>
>=============================================================================
>
>============================================================================
>
>this is the ouput from terminal.
>
>data write to reg0: 0x0028
>data write to reg0: 0x0021
>data write to reg0: 0x0021
>data write to reg0: 0x0016
>data write to reg0: 0x001A
>data write to reg0: 0x0028
>data write to reg0: 0x0024
>data write to reg0: 0x001A
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>data read from reg1: 0x0000
>
>======================================================================
Article: 149205I can't cause I used NIOS & C library to do remote update ( Quartus II 7.0 ). Sorry I can't help you with this IP. BR Adam > I'm really sorry for late reply about your help. > A few days ago, I've installed the service pack 1(SP1) as someone's > comment. > And then I made a new project with same source ion the SP1. > Surprisingly, everything worked fine !! > > I quess that someting keeps the lock on the configuration pins on the > user-mode at no service pack version. > But I don't know the exact cause. > > Anyway, a little bit late, I appreciate you, Adam. > > If you know the usage of "asmi_parallel" ip core, I'd like get some advice > about using "write operation". > There are two kind of write operation as below. > 1) single byte write operation > 2) page write operation (2~256 byte) > When I used the page write operation with 256 byte PAGE_SIZE, > the "busy" signal (it's "doing" output from asmi_parallel ip core) keeps > "high" during 30us after write command. > Strangely, when I tried to use single byte write operation, > the "busy" signal keeps "high" during 300us after write command !! > I cannot believe it and its time is different from the data sheet. > On the data sheet, the "busy" high time is shown as about 3 us on the > single > byte write operation.. > > It bothers me not to select actual write operation at this time. > If you have advice for me, please donot hesitate. > Thanks in advanced > Regards > Paul > > > > > > >> Hi Paul, >> >> Any progress ? >> >> Adam >> >>> Hi Paul, >>> >>> First of all try to use Indirect flash programming using jtag > interface. >>> If it will work fine your EPCS is connected correctly and your fpga >>> should start automatically. >>> If not , check epcs connection to fpga and msel pins configuration. >>> >>> Second step is to write and read back epcs config using your rs > connection. >>> >>> Then you have to prepare flash image using >>> sof2flash" --epcs --input="example.sof" --output="example.flash" >>> >>> Adam >>> >>>> Hi,all >>>> >>>> I'm Paul Ham in Korea and have some difficulties in using > ASMI_PARALLEL >>>> altera ip core. >>>> Anyone who knows well this problem could advice to me. >>>> >>>> I'm using Cyclone FPGA with EPCS4 and Quartus V9.1 without service > pack. >>>> My design is very simple like below : >>>> 1) receive the data from PC via RS232. >>>> The data is .rpd file made by Conver Programming Files of Quartus > menu. >>>> Due to the EPCS spec, its size is 512KByte. >>>> 2) write the data to internal dpram. (double buffering) >>>> 3) read the data from dpram to asmi_parallel every 256 bytes.(page > write) >>>> >>>> When I simulated it with signaltap, it wrote other .rpd file into > EPCS4 >>>> well. >>>> And it configured well after power-up. >>>> >>>> But it didn't work when I programmed itself directly to EPCS4. >>>> It always generate the illegal_erase and illegal_write. >>>> >>>> I found some ways to solve the problem like below but anything didn't >>>> work >>>> well. >>>> 1) make 4 pins related to configuration, nCS/ASDO/DCLK/DATA0, "USE AS >>>> REGULAR IO" at .qsf file. >>>> -> set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE > AS >>>> REGULAR IO" >>>> set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS >>>> REGULAR IO" >>>> set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS >>>> REGULAR IO" >>>> set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION >>>> "USE AS REGULAR IO" >>>> 2) modify the value of "ncs_reg" in asmi_parallel.v as below. >>>> -> always @ ( negedge clkin_wire or posedge end_ophdly) >>>> if (end_ophdly == 1'b1) ncs_reg<= 1'b1; >>>> else if (wire_ncs_reg_ena == 1'b1) ncs_reg<= 1'b0; >>>> 3) install the service pack 1 : I didn't try it >>>> >>>> I guess that the problem is related to the setting of 4 configuration >>>> pins. >>>> But I'm not sure what could I do. >>>> If you have any advice or solution, please let me know. >>>> >>>> Thanks advance >>>> Regards >>>> Paul >>>> >>>> >>>> >>>> >>>> --------------------------------------- >>>> Posted through http://www.FPGARelated.com >>> >> >> > > --------------------------------------- > Posted through http://www.FPGARelated.comArticle: 149206
[code snipped - it was bad enough once!] Open the "XST User Guide" (probably file xst.pdf). It is a fine manual. Read the chapter entitled "XST Hardware Description Language (HDL) Coding Techniques". Have you ever considered a career in golf course maintenance? ;-) --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149207
On 2010-10-07, Nial Stewart <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:
>> FreeRtos (freertos.org) + NXP LPC17xx.
>
>
> Thanks Nico but this isn't much simpler than implementing an OS & TCP/IP
> on a NIOS (I presume).
Yes it is. It's way, way, way, simpler.
I've used a NIOS core. There's nothing even remotely simple about it.
[And we never did get the OpenCores Ethernet MAC to work very well.]
--
Grant Edwards grant.b.edwards Yow! I'm thinking about
at DIGITAL READ-OUT systems
gmail.com and computer-generated
IMAGE FORMATIONS ...
Article: 149208>> Thanks Nico but this isn't much simpler than implementing an OS & TCP/IP >> on a NIOS (I presume). > > Yes it is. It's way, way, way, simpler. > > I've used a NIOS core. There's nothing even remotely simple about it. I'm OK with setting the NIOS system up, it's integrating the OS and TCP/IP stack I haven't got a clue about. > [And we never did get the OpenCores Ethernet MAC to work very well.] It looks like the Lantronix XPort or a Wiznet chip (if volumes are big enough) is the easiest way for me to get this done. Thanks all for your feedback. Nial.Article: 149209
> I haven't defined any timing constraints and my design passes the timing > constraints test. Now i am looking at the warnings if anything is getting > optimized out. And i didn't know that these black boxes can create > problems, i am using many fifos and embedded rams.i'll have to check on > them. > You haven't defined any timing constraints!!!!! How could this possibly work?Article: 149210
On Oct 7, 6:30=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > [code snipped - it was bad enough once!] > > Open the "XST User Guide" (probably file xst.pdf). > It is a fine manual. > Read the chapter entitled "XST Hardware Description Language (HDL) Coding > Techniques". > > Have you ever considered a career in golf course maintenance? > ;-) That might be a bit harsh, depending on the OP's background, although I agree it'll only get worse from here if he's not the manual- and/or Google-reading sort. The specific question is addressed at http://www.xilinx.com/support/answers/14047.htm .Article: 149211
"mprfgen" is a simple-minded multi-port memory generator that you can use for your VHDL designs. It can generate either generic or Xilinx- specific (through component instantiation) multi-port memories. "mprfgen" was written during the course of a few days back in 2007. I guess I'm releasing this now since it is still useful and relevant. I would appreciate any comments and suggestions regarding its improvement. You can find this little tool at this website: http://www.nkavvadias.co.cc Direct link is: http://www.nkavvadias.co.cc/misc/mprfgen.zip "mprfgen" is licensed under the LGPL, version 3. Kind regards Nikolaos Kavvadias (nikolaos<dot-here!>kavvadias#at#gmail.com) Adjunct lecturer - Research scientist Website: http://www.nkavvadias.co.ccArticle: 149212
On Oct 6, 1:12 pm, Kolja Sulimma <ksuli...@googlemail.com> wrote: > On 6 Okt., 07:06, rickman <gnu...@gmail.com> wrote: > A > > > lot of the presentation talked to the cost savings that was possible > > using PR. But that only makes sense to me if it can be used with low > > cost parts. Reducing the cost of using a more expensive part by using > > a complex process is a poor substitute to just using a part that costs > > less. But if I can use the less expensive part and cut my costs > > further by using PR, that can make a number of projects practical that > > otherwise wouldn't be. > > I completely disagree. > If you have a design that barely fits in a 6k$ part and can reduce the > LUT > count by a factor of 4 by using PR you save about 4k$ per chip > This is what happens for DNA pattern matching machines. > > Try saving 4k$ with a spartan-3. > > The volume where saving 10$ per chip justifies the more complex PR > design process > is rather high. Yes, the designs that use a $10 chip ARE high volume apps. I've never seen a part that costs $6000, but I did see one that used a $1500 chip. The unit this was going in sold for $100,000 and they expected to sell much less than 100 per year. I remember that the initial design for that chip used less than 20% of the LUTs. Do you think they cared at all about using a tool like PR? I'm sure there are designs using Vertex chips (high cost) that would benefit from the PR. My point is that if PR were available for the low cost Spartan line, it would result in significant additional sales. Xilinx doesn't want to sell lower costs chips unless it somehow means more profit. The only way PR makes profit for them is if it sells chips they otherwise would not have sold. That makes much more sense at the low end than the high end. The real problem is that Xilinx doesn't "get" the low end. Yes, they will brag about some product where they sold a million Spartan chips without saying it required cutting their margin to under a buck, picking an imaginary example. But if PR makes a design feasible by cutting the part size they could have sold the cheaper chips at the same price with a two dollar margin yielding twice the total profit. Or better yet, design variations of their chips for the truly low end like Silicon Blue does. Xilinx thinks they can't make any worthwhile money at $2 a chip. Maybe they can't, but others will. RickArticle: 149213
Hi Delgeris,
The following will give you problems for sure:
WHEN "100" => if (rising_edge(clk_tetarto)) then
if (seq=0) then
LEDS<= "0111";
...
Above this line of code you also assign values to LEDS, but without
the clk_tetarto sync signal. This means, that the synthesis tool will
try to infer flip flops on LEDS, clocked by clk_tetarto and at the
same time do it asynchronously.
I think it would help you alot to read some basic design guides on
synchronous design. The XST guide is quite good.
Good luck!
Regards,
Kim P.
On Thu, 07 Oct 2010 06:42:19 -0500, "delgeris"
<demetrisdelgeris@n_o_s_p_a_m.hotmail.com> wrote:
>hello
>i am trying to synthesize the following code.i am creating 4 different
>clocks by clock division and then i want to get different led outputs
>according to switches change in my virtex2pro fpga
>i am kind of new to vhdl and i get the following error
>
>ERROR:Xst:827 - "C:/Xilinx91i/lab3/lcok.vhd" line 150: Signal LEDS<0>
>cannot be synthesized, bad synchronous description.
>
>here is my code
>
>entity lock is
> Port ( SWITCHES : in STD_LOGIC_VECTOR (3 downto 0);
> RESET : in STD_LOGIC;
> fpga_clock: in STD_LOGIC;
> LEDS : out STD_LOGIC_VECTOR (3 downto 0));
>end lock;
>
>architecture Behavioral of lock is
>
>signal cur_state: std_logic_vector(2 downto 0);
>signal next_state: std_logic_vector(2 downto 0);
>signal state1s,state2s,state10s,state_miso,state_tetarto: std_logic;
>signal clk,clk_1s,clk_2s,clk_10s,clk_miso,clk_tetarto,blink1: std_logic;
>
>begin
>
>
>
>
>process(fpga_clock)
> variable counter2 : integer range 0 to 100000000;
> variable counter1 : integer range 0 to 50000000;
> variable counter_miso : integer range 0 to 25000000;
> variable counter_tetarto : integer range 0 to 12500000;
> -- variable a:integer:=0;
>
>
> begin
> -- if (a<1) then cur_state<="000"; else cur_state<=cur_state; end if;
> -- a:=a+1;
> if (rising_edge(fpga_clock)) then
>
> if (counter1=50000000) then
> if (state1s = '1')then
> state1s<='0';
> clk_1s<='1';
> else
> state1s<='1';
> clk_1s<='0';
> end if;
>
> counter1:=1;
> else
> counter1 := counter1 +1 ;
> end if;
>
>
> if (counter2=100000000) then
> if (state2s = '1')then
> state2s<='0';
> clk_2s<='1';
> else
> state2s<='1';
> clk_2s<='0';
> end if;
>
> counter2:=1;
> else
> counter2 := counter2 +1 ;
> end if;
>
>
> if (counter_miso=25000000) then
> if (state_miso = '1')then
> state_miso<='0';
> clk_miso<='1';
> else
> state_miso<='1';
> clk_miso<='0';
> end if;
>
> counter_miso:=1;
> else
> counter_miso := counter_miso +1 ;
> end if;
>
>
> if (counter_tetarto=12500000) then
> if (state_tetarto = '1')then
> state_tetarto<='0';
> clk_tetarto<='1';
> else
> state_tetarto<='1';
> clk_tetarto<='0';
> end if;
>
> counter_tetarto:=1;
> else
> counter_tetarto := counter_tetarto +1 ;
> end if;
> end if;
>
>
>
>if (reset = '1') then
>cur_state <= "000";
>end if;
>
> CASE SWITCHES IS
> WHEN "0110" => if (cur_state = "000") then cur_state<="001" ;
> end if;
> WHEN "1001" => if (cur_state = "001") then cur_state<="010" ;
> end if;
> WHEN "1010" => if (cur_state = "010") then cur_state<="011" ;
> end if;
> WHEN "0101" => if (cur_state = "100") then cur_state<="101" ;
> end if;
> WHEN OTHERS => cur_state<="100";
> end case;
>
>
>if ((cur_state = "101") and (reset = '1')) then
>cur_state<= "000";
>else cur_state<="100";
>end if;
>
>next_state<=cur_state;
>
>end process;
>
>process(next_state)
>
> variable seq:integer:=0;
> variable c:integer:=0;
>
>begin
>
> CASE next_state IS
> WHEN "000" => if ((clk_2s='1') and (c < 1)) then
> LEDS(3 downto 0) <= "0000";
> c:=c+1;
> else if (clk_1s='1') then
> LEDS(2 DOWNTO 0)<= NOT ("000");
> LEDS(3)<='1';
> else
> LEDS(3) <='0';
> end if;
> end if;
> WHEN "001" => if (clk_1s = '1') then
> LEDS(1 DOWNTO 0)<= "11";
> LEDS(3 downto 2)<="11";
> else
> LEDS(3 downto 2) <="00";
> end if;
> WHEN "010" => if (clk_1s = '1') then
> LEDS(0)<= '1';
> LEDS(3 downto 1)<="111";
> else
> LEDS(3 downto 1) <="000";
> end if;
> WHEN "011" => if (clk_miso = '1') then
> LEDS(3 downto 0)<="1111";
> else
> LEDS(3 downto 0) <="0000";
> end if;
> WHEN "100" => if (rising_edge(clk_tetarto)) then
> if (seq=0) then
> LEDS<= "0111";
> seq:=1;
> else if
> (seq=1) then
> LEDS<= "1011";
> seq:=2;
> else if
> (seq=2) then
> LEDS<= "1101";
> seq:=3;
> else if
> (seq=3) then
> LEDS<= "1110";
> seq:=0;
> end if;
> end if;
> end if;
> end if;
> end if;
> WHEN OTHERS => LEDS<="0101";
> end case;
>
>
>end process;
>
>
>end Behavioral;
>
>any help would be appreciated!
>thank you
>
>
>
>---------------------------------------
>Posted through http://www.FPGARelated.com
Article: 149214
"delgeris" <demetrisdelgeris@n_o_s_p_a_m.hotmail.com> writes:
Some comments on your code below (I don't normally write at this
length on Usenet, but I'm waiting for something long running to
finish... :)
> hello
> i am trying to synthesize the following code.i am creating 4 different
> clocks by clock division and then i want to get different led outputs
> according to switches change in my virtex2pro fpga
> i am kind of new to vhdl and i get the following error
>
> ERROR:Xst:827 - "C:/Xilinx91i/lab3/lcok.vhd" line 150: Signal LEDS<0>
> cannot be synthesized, bad synchronous description.
>
> here is my code
>
> entity lock is
> Port ( SWITCHES : in STD_LOGIC_VECTOR (3 downto 0);
> RESET : in STD_LOGIC;
> fpga_clock: in STD_LOGIC;
> LEDS : out STD_LOGIC_VECTOR (3 downto 0));
> end lock;
>
> architecture Behavioral of lock is
>
> signal cur_state: std_logic_vector(2 downto 0);
> signal next_state: std_logic_vector(2 downto 0);
> signal state1s,state2s,state10s,state_miso,state_tetarto: std_logic;
> signal clk,clk_1s,clk_2s,clk_10s,clk_miso,clk_tetarto,blink1: std_logic;
>
> begin
>
>
>
>
> process(fpga_clock)
> variable counter2 : integer range 0 to 100000000;
> variable counter1 : integer range 0 to 50000000;
> variable counter_miso : integer range 0 to 25000000;
> variable counter_tetarto : integer range 0 to
> 12500000;
Interesting ranges - most people would use (2^n)-1 as a maximum value,
unless they have good reason not ot.
But, full marks for using variables (an endless debate on variable vs
signals around these parts :) for things which only need to be local
to this process.
And using integers for counters (not some horribleness like
std_logic_unsigned) - good also.
> -- variable a:integer:=0;
>
>
> begin
> -- if (a<1) then cur_state<="000"; else cur_state<=cur_state; end if;
> -- a:=a+1;
> if (rising_edge(fpga_clock)) then
Good, using the rising_edge() function.
But don't use brackets on if statements - they make you look like a
C-programmer :)
>
> if (counter1=50000000) then
Any time you are using a "magic" number more than once, use a constant
to refer to it.
so, when you define the variable above do this:
constant counter1_high : integer := 50000000;
variable counter1 : integer range 0 to counter1_high;
and then use:
if counter1 = counter1_high then.
or alternatively, use a proper subtype:
subtype t_counter1 is integer range 0 to 50000000;
variable counter : t_counter;
then:
if counter1 = t_counter1'high then
Both a re a little more typing (although with Emacs and tab
completion, they don't get in the way much), but it means you can
change the value in *one* place and not have to remember all the other
places you have to update.
> if (state1s = '1')then
> state1s<='0';
> clk_1s<='1';
> else
> state1s<='1';
> clk_1s<='0';
> end if;
>
> counter1:=1;
> else
> counter1 := counter1 +1 ;
> end if;
>
Try and indent properly - it makes it much easier for us to read the
code. And you in the coming weeks!
Also, try and be consistent in whether you have spaces around <= and
:=. I like having spaces around them. Others don't. But be
consistent.
Emacs VHDL-mode and Sigasi's HDT will reformat your code prettily
without any effort. I use emacs, and when my code starts to look a
mess (about every compile :) I run the beautify function.
>
> if (counter2=100000000) then
Again, use a constant or suitable subtype.
> if (state2s = '1')then
> state2s<='0';
> clk_2s<='1';
> else
> state2s<='1';
> clk_2s<='0';
> end if;
>
> counter2:=1;
> else
> counter2 := counter2 +1 ;
> end if;
>
>
> if (counter_miso=25000000) then
And again.
> if (state_miso = '1')then
> state_miso<='0';
> clk_miso<='1';
> else
> state_miso<='1';
> clk_miso<='0';
> end if;
>
> counter_miso:=1;
> else
> counter_miso := counter_miso +1 ;
> end if;
>
>
> if (counter_tetarto=12500000) then
And again!
> if (state_tetarto = '1')then
> state_tetarto<='0';
> clk_tetarto<='1';
> else
> state_tetarto<='1';
> clk_tetarto<='0';
> end if;
>
> counter_tetarto:=1;
> else
> counter_tetarto := counter_tetarto +1 ;
> end if;
> end if;
>
>
>
> if (reset = '1') then
> cur_state <= "000";
use an enumerated type for your states, so they have useful names
rather than just being numbers. Let the synth figure out a good
encoding for them.
> end if;
>
And usually the reset bit is done:
if (reset = '1') then
-- do reset stuff
else
-- do the normal stuff
end if;
rather than being stuck in the middle (and without an else to stop the
rest of the code "running" during reset)...
> CASE SWITCHES IS
> WHEN "0110" => if (cur_state = "000") then cur_state<="001" ;
> end if;
Don't write lots of code on one line it's harder to understand
usually. If you must, then at least make it *all* on one line. Not
and endif; on a 2nd line!
> WHEN "1001" => if (cur_state = "001") then cur_state<="010" ;
> end if;
> WHEN "1010" => if (cur_state = "010") then cur_state<="011" ;
> end if;
> WHEN "0101" => if (cur_state = "100") then cur_state<="101" ;
> end if;
> WHEN OTHERS => cur_state<="100";
The synthesizer will likely ignore this others clause.
> end case;
This is an unusual state machine - usually we do "case cur_state" and
then you'd have "if switches = some_value" inside each of the "when"
sections of the case statement.
>
>
> if ((cur_state = "101") and (reset = '1')) then
> cur_state<= "000";
> else cur_state<="100";
> end if;
>
This seems to set cur_state to "100" all the time that reset is '0' or
cur_state isn't "101" - unless I'm reading wrong?
> next_state<=cur_state;
>
Normally, "next state" is assigned to in the case statements and then
at the end cur_state <= next_state.
But (and there are many others who'd agree) I'd use a single process
for the state machine, keep it all together. If you google "single
process state machines" you'll find many previous discussions ;)
> end process;
>
> process(next_state)
>
> variable seq:integer:=0;
> variable c:integer:=0;
>
> begin
>
<snip more badly formatted code>
> end if;
> WHEN "100" => if (rising_edge(clk_tetarto)) then
And, as someone else pointed out - you can't do this!
This is a process which is sensitive to the change of state - you
can't then make it sensitive to the edge of a clock signal (the
flipflops only have one clock input in the vast majority of FPGAs)
If you do all your code in a single process, you'll find it easier to
avoid doing this!
<snip more badly formatted code>
>
> end process;
>
>
> end Behavioral;
>
> any help would be appreciated!
Essential:
* Reformat the code to be indented and laid out consistently
* Use a single process with a single clock and reset. (Make sure that
the reset signal you are using *is* synchronised to the clock).
* Make sure the reset covers everything (you can relax this later on
when you know what the implications are, but for now do this:
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
--- resetty things
else
-- normal running things
end if;
end if;
end process;
The template outlined in the XST synthesis templates guide looks a lot
like this :)
* Avoid using magic numbers more than once - make use of the language
to define them in one place and then just refer to them elsewhere.
Even if they are only used once, it can help to define them as a
constant which describes how you came to that number, rather than the
number just being there. For example using a constant called
"maxcount" doesn't help, but one called "setup_time" might (depending
on the context!)
Improvement:
* Use an enumerated type for your state
> thank you
>
You're welcome!
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.co.uk/capabilities/39-electronic-hardware
Article: 149215On Oct 7, 3:26=A0pm, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > >> Thanks Nico but this isn't much simpler than implementing an OS & TCP/= IP > >> on a NIOS (I presume). > > > Yes it is. =A0It's way, way, way, simpler. > > > I've used a NIOS core. =A0There's nothing even remotely simple about it= . > > I'm OK with setting the NIOS system up, it's integrating the OS and > TCP/IP stack I haven't got a clue about. > > > [And we never did get the OpenCores Ethernet MAC to work very well.] > > It looks like the Lantronix XPort or a Wiznet chip (if volumes are big > enough) is the easiest way for me to get this done. > > Thanks all for your feedback. > > Nial. Hi Nial I have been using Wiznet in a number of 'in production' designs for the last 4 years. Currently the W5300 or module with the same would be the best choice. I evaluated the other options but required > 50Mb/s and ability to use only UDP (harsh industial heavy welding environments along with real time data meant TCP retries would not be desirable to say the least). A few registers to set up (from the client side) and thereafter it's akin to FTDI. The Wiznet chip cost is in the same ball park as a separate PHY or MAC/ PHY in 100 to 1k volume. Can buy from Wiznet (watch out for the new VAT customs rubbish) or from their UK disty (Hero?) Regards DGArticle: 149216
Martin gave you some excellent advise. I would add the following. It looks like your state machine's next state logic is coded in the synchronous process, but the output decoding is in a combinatorial process. This is fine, if you need combinatorial outputs. However, combinatorial processes can easily create latches if you don't watch it very closely. Short answer: if you must use a combinatorial process, assign every output with a default value right up front in that process, before and flow-control code (if-then, case-when, etc.). Since the code will make an assignment to every output on every pass, there is no "remembering what was the previous value" required, and no latches get generated. In your state transition coding, most users code a case statement using the state, and use if-statements or case statements within each state description to define what happens in response to inputs while in that state. You've switched it around by using an outer case statement to consider the switch inputs, then using subordinate if- then statements to manage what you do in which states. While this may work, most people find it easier to mentally manage what's going on in a state machine using the traditional coding approach. Also most users do not use separate current_state and next_state signals in one synchronous process. The way you have done it appears to insert an additional clock cycle delay from current_state to next_state, and then you have a combinatorial output process that uses next_state. But next_state is never used to create current_state (?). If you omit the additional next_state, and move the output logic to your synchronous process (and thus avoid any latches), but use current_state instead of next_state, the clock-cycle timing of your outputs should not change. It's the difference between combinatorial outputs derived from a delayed registered state, or registered outputs derived from a non-delayed registered state: both take the same number of clocks to generate the outputs from the state, but the latter is easier to code in the same case statement as the state transition logic. AndyArticle: 149217
On Oct 6, 3:56=A0am, Uwe Bonnes <b...@elektron.ikp.physik.tu- darmstadt.de> wrote: > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > On Oct 5, 3:12=A0pm, Uwe Bonnes <b...@elektron.ikp.physik.tu- > > darmstadt.de> wrote: > > > Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > ... > > > > > There is no announced date for Artix-7 device availability at this > > > > time. > > > > Is there something announced for S6? > > > With the exception of the XC6SLX4 and XC6SLX9 all devices are in > > production and in stock at Avnet for small quantities and 6-8 weeks > > times for larger quantities. > >http://avnetexpress.avnet.com/store/em/EMController?action=3Dproducts&N.= .. > > Any expected roll-out time for SLX4/SLX9? They are the only parts in QFP.= .. > > -- > Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar= mstadt.de > > Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------- Hide q= uoted text - > > - Show quoted text - There isn't an announced date for the 6SLX4 and 6SLX9 devices at this time, but it will be sooner rather than later. Ed McGettigan -- Xilinx Inc.Article: 149218
On 10/7/2010 4:42 AM, delgeris wrote:
> hello
> i am trying to synthesize the following code.i am creating 4 different
> clocks by clock division and then i want to get different led outputs
A related example:
http://mysite.ncnetwork.net/reszotzl/count_enable.vhd
-- Mike Treseler
Article: 149219
>> I haven't defined any timing constraints and my design passes the timing
>> constraints test.
It *is* easier to vault over the bar, when it is on the ground ;)
For designs with a single clock, synthesis will
report Fmax, but for multiple clocks or
external interfaces, constraints (or luck) is required
to make the system work.
>> Now i am looking at the warnings if anything is getting
>> optimized out. And i didn't know that these black boxes can create
>> problems, i am using many fifos and embedded rams.i'll have to check on
>> them.
On 10/7/2010 10:56 AM, mike wrote:
> You haven't defined any timing constraints!!!!! How could this
> possibly work?
It seems that no spare luck was available in this case.
-- Mike Treseler
Article: 149220Hi, i am using xilinx 12.1 PlanAhead to make partitions of my design but there seems to be some problem. When i import the source files, i can see the files of my design. but when i open a netlist deisgn it only picks up the netlists of blackboxes i.e. cores generated from CoreGen wizard and doesn't pick other NGC files. Can someone tell me why is it happening.Or am i interpreting it wrongly? Thanks Regards SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149221
Hi I am using Xilinx Sapartan 3 . I have wrote HDL in verilog for testing an external memory attached to FPGA. Mapping end up with error. Pack:2309 - Too many bonded comps of type "IOB" found to fit this device. I am a beginner in this field. In the first place , It seems that I am using more resources than the FPGA can provide ? . Please suggest , how to get rid of this error Thanks and Regards Faisal --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149222
ok problem solved. i wasn't synthesizing the modules with "KEEP HIERARCHY = YES" attribute. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149223
A 16qam signal is upsampled by 2 and shaped by root raised cosine. At the Rx it is matched-filtered with same rrcos filter and decimated by 2 to get the symbols. All looks ok. Symbols are recovered clean. However, the decimation leads to two phases i.e. depending on which samples you choose from the decimator output(even or odd), only one phase is the correct symbols. The question is: is there a way to choose even or odd correctly without eyeballing? or do we need some logic to work it out? Regards Kadhiem --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149224
On 7 Oct, 18:58, Nikolaos Kavvadias <nikolaos.kavvad...@gmail.com> wrote: > "mprfgen" is a simple-minded multi-port memory generator that you can > use for your VHDL designs. It can generate either generic or Xilinx- > specific (through component instantiation) multi-port memories. > > "mprfgen" was written during the course of a few days back in 2007. I > guess I'm releasing this now since it is still useful and relevant. I > would appreciate any comments and suggestions regarding its > improvement. > > You can find this little tool at this website:http://www.nkavvadias.co.cc > Direct link is:http://www.nkavvadias.co.cc/misc/mprfgen.zip > > "mprfgen" is licensed under the LGPL, version 3. > > Kind regards > Nikolaos Kavvadias (nikolaos<dot-here!>kavvadias#at#gmail.com) > Adjunct lecturer - Research scientist > Website:http://www.nkavvadias.co.cc Thanks. It built OK with gcc on my Win7 x64 laptop. I've just installed the latest Xilinx ISE, and I'll see how it behaves with that. Leon
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