Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Nov 24, 8:01=A0am, gnirre <gni...@gmail.com> wrote: > On Nov 24, 12:03=A0am, Thomas Entner <thomas.ent...@entner- > > > > > > > > > > electronics.com> wrote: > > I am mainly refering to:http://www.techfocusmedia.net/embeddedtechnolog= yjournal/feature_artic... > > > I think there will be some market for such a device, especially in the > > medical and industrial control market, maybe also networking. In fact > > we did already design a board with an FPGA connected to a Qseven Atom > > module by PCIe. Also I think, that $72 is a reasonable price for that > > kind of FPGA (so the Atom is really almost for free, if it is not even > > "negative" priced...) > > > But I think there are some "buts": > > - There are 3 main (new) families of FPGAs from Altera (low-, mid- and > > high-end), all with some "sub-families" and a lot of different family- > > members varying in size (and price) dramatically. The same is with > > Xilinx, Lattice and Actel (ehm... Microsemi). And then there are some > > newcomers (e.g. Achronix, which is fabbed by, hmmm, Intel). From > > Intel, I can choose from one FPGA. At least the Atom offers different > > speed-grades... So, if I just want to add just 20 UARTs to my design, > > the FPGA will be way too large/expensive. For some high end number- > > crunching-support, or integrating a lot of south-bridge-functionality, > > it might still be too small. > > - To use the Atom, in the end you have to design a PC. I doubt there > > are many designers out there having experience with this (dealing with > > BIOS, etc.), it will be quite some design-effort. Projects with that > > size are typically cost-critical and will try to find cheaper > > solutions. The other option is to use this Atom+FPGA as a module (like > > the Qseven Atom-modules) which takes away a lot of design effort from > > the product developer. (There is already one available:http://de.kontro= n.com/products/boards+and+mezzanines/pc104+sbc+and+pe.... > > Not sure how to connect e.g. a DDR2-SDRAM to the FPGA. The headers do > > not look very promosing...) (But as easily a module-manufacturer could > > integrate any FPGA on an Atom-module, no need to use the Intel-combo) > > - It is possible to integrate a soft-core-CPU that runs uC-Linux in a > > $10 FPGA. FPGA-Products with Cortex A9 are on the roadmap of Altera > > and I think also Xilinx (no idea about pricing yet, may be even more > > expensive...) Then there is also the option of using a Cortex-A8-CPU > > with many peripherals (or any other) + a FPGA. This will be the > > solutions that Intel has to compete with, both with pricing and also > > power-consumption. > > - In the past, Hard-Core-CPU + FPGA-combinations from Altera and > > Xilinx were no success. > > - Doubts if this product from Intel has a future, if they are really > > serious with it in the long term, may customers keep away from using > > it. > > > I am curios how this develops. I think the module-solution, where you > > get a quite big FPGA for an attractive price, will be the most > > interesting thing. For this applications, pricing is not that > > critical, development should be easy/quick. But I am not sure if this > > market is large enough to satisfy Intel in the long term... > > > Thomas > > >www.entner-electronics.com > > > P.S.: Sorry for cross-posting, but I think this is interesting for > > both newsgroups. > > So Stellarton is basically a product that is the optimal choice for > almost no application, almost always too small, or too expensive. > > So why did Intel have this one built? Who ordered it? Which is the One > Single App where an Atom E and 60 000 fpga gates is the optimal > combination? > Being as big as it is and having the resources it has, including a temporarily unassailable lead in a very profitable business, Intel can afford to throw things randomly at the wall to see if they stick. They go around buying and selling companies, announcing and abandoning technologoy initiatives, and just generally behaving like a drunken sailor with too much money to spend. Intel can afford to do that. In fact, it almost needs to do that, as Intel's track record at barging into new businesses would have put any normal company out of business, but Intel absolutely must find new business areas and/or materially expand the territory implied by its x86 franchise--or go the way of Continental Can. Robert.Article: 149826
On Nov 24, 3:11=A0pm, "Roger" <rogerwil...@hotmail.com> wrote: > "Chris Maryan" =A0wrote in message > > news:6092db29-96e8-45ce-8870-9069272dc561@o4g2000yqd.googlegroups.com... > > On Nov 23, 5:00 pm, "Roger" <rogerwil...@hotmail.com> wrote: > > > The latest Xilinx PlanAhead seems to do everything that a project needs > > from > > VHDL input to bit stream. So what's ISE for now? > > > Thanks, > > Rog. > > My understanding is that the plan is for PlanAhead to replace ISE. > Though I'm not sure at what point this will happen. > > Chris > > Chris, > > Thanks for the reply. I suspected this might be the case. Did you hear th= is > from Xilinx? > > Rog. I'm not sure where I heard this, it was a while ago. Possibly my AE, possibly just internet rumors. If you watch some of the demo videos on the Xilinx website, they tend to be working with planahead exclusively. However, the best thing I've ever done for myself is to stop using any GUI based compile flow. Both Planahead and ISE just run the command line tools with a specific set of options. Usually those options are easy to figure (they're in the report files for the tools) out and stick in a .bat file or a makefile. Though I do like to use PlanAhead for figuring out area groups and pin planning. ChrisArticle: 149827
On Thu, 25 Nov 2010 16:35:12 +0100, David Brown <david@westcontrol.removethisbit.com> wrote: >On 24/11/2010 22:22, Petter Gustad wrote: >> Benjamin Couillard<benjamin.couillard@gmail.com> writes: >> >>> Do you have a suggestion for Linux? For example, can we use Ubuntu or >>> should we stick with the "Xilinx-approved" linux flavors? >> > >I have no experience with fpga design in Linux, but if Xilinx approves >Red Hat, then Fedora, Centos or Scientific Linux would alternatives that >are pretty close to Red Hat enterprise versions. Centos is as similar to Redhat Enterprise as possible without calling it as such. The only difference is the logos and text which refer to Redhat. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149828
Am 25.11.2010 10:11, schrieb Philip Herzog: > On 11/20/2010 10:27, Thomas Heller wrote: >> Which series / package should I choose for long availability? > > What's long in your terms? > > I'm in the measurement equipment industry, our oldest products have been > on the market for fifteen years and they contain Xilinx FPGAs that have > been introduced about seventeen years ago, which have been discontinued > lately. We are in a very similar situation; our product lifetime is also around 10 years. We have boards still in production based on parts like 4006 (no longer available but we have some stock although they were very expensive), XCS05, XC3S200. Plus XC9572/XC9572XL cplds. > Usually, we aim for parts which are targeted at the automotive industry > since they have the tendency to have a longer lifetime. Thanks for this tip. ThomasArticle: 149829
Am 24.11.2010 11:48, schrieb Morten Leikvoll: > "Thomas Heller"<theller@ctypes.org> wrote in message > news:8ks9nqF329U1@mid.individual.net... >> How are you doing prototyping with BGA packages? > > FPGA's I would prototype on an eval board. > I don't use these myself, but look at http://www.emulation.com/ > They may have some sockets that could just squeeze in. > > Looks interesting, but expensive ;-).Article: 149830
Hi
I've got problem to load linux image to my 2c35 FPGA on DE2 board. The
example sof with NIOS2 come from examples(/opt/altera9.1sp1/nios2eds/
examples/verilog/niosII_cycloneII_2c35/full_featured/). All
instructions I get from this site:
http://www.nioswiki.com/OperatingSystems/UClinux/QuartusforLinux
[NiosII EDS]$ jtagconfig
1) USB-Blaster [USB 5-1.2]
020B40DD EP2C35
[NiosII EDS]$ nios2-configure-sof
/opt/altera9.1sp1/nios2eds/examples/verilog/niosII_cycloneII_2c35/
full_featured/
NiosII_cycloneII_2c35_full_featured.sof
Info:
*******************************************************************
Info: Running Quartus II Programmer
Info:
Command: quartus_pgm --no_banner --mode=jtag -o
p;/opt/altera8.0/nios2eds/examples/verilog/niosII_cycloneII_2c35/
full_featured/
NiosII_cycloneII_2c35_full_featured.sof
Info: Using programming cable "USB-Blaster [USB 5-1.2]"
Info: Started Programmer operation at Fri Dec 8 11:35:01 2006
Info: Configuring device index 1
Info: Device 1 contains JTAG ID code 0x020B40DD
Info: Configuration succeeded -- 1 device(s) configured
Info: Successfully performed operation(s)
Info: Ended Programmer operation at Fri Dec 8 11:35:04 2006
Info: Quartus II Programmer was successful. 0 errors, 0 warnings
Info: Processing ended: Fri Dec 8 11:35:04 2006
Info: Elapsed time: 00:00:22
[NiosII EDS$ nios2-download -g ~/uClinux-dist/images/zImage
Using cable "USB-Blaster [USB 5-1.2]", device 1, instance 0x00
Pausing target processor: OK
Initializing CPU cache (if present)
OK
Downloaded 1016KB in 16.2s (62.7KB/s)
Verified OK
Starting processor at address 0x04500000
[NiosII EDS$ nios2-terminal
nios2-terminal: connected to hardware target using JTAG UART on cable
nios2-terminal: "USB-Blaster [USB 5-1.2]", device 1, instance 0
nios2-terminal: (Use the IDE stop button or Ctrl-C to terminate)
Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.Uncompressing Linux... Ok, booting the kernel.
Linux version 2.6.17-uc1 (hippo@darkstar) (gcc version 3.4.6) #46
PREEMPT Thu Dec 7 15:22:06 CST 2006
Unfortunately when I download image to NIOS I receive:
Using cable "USB-Blaster [USB 1-1.3.1]", device 1, instance 0x00
Pausing target processor: not responding.
Resetting and trying again: FAILED
Leaving target processor paused
When I try another sof file example from site:
http://www.nioswiki.com/OperatingSystems/UClinux/TryOutuClinux
Article: 149831When I try another sof file example from site: http://www.nioswiki.com/OperatingSystems/UClinux/TryOutuClinux (part for For DE2 2C35 dev board) everything is running. Linux is booting and I got this when I trying donwload image: Using cable "USB-Blaster [USB 1-1.3.1]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloaded 1208KB in 6.6s (183.0KB/s) Verified OK. Why example from altera doesn't work?Article: 149832
Hi all, I'm a newbye in VHDL and I would like to submit a question. I have a system wich is clocked at 24MHz by an external oscillator. This clock is the input of a PLL internal to the FPGA. The outputs of the PLL are two clocks: one at 48MHz to clock a CPU and a custom logic called "A", and the other one at 24MHz to clock a custom logic called "B". These two clocks are produced without phase shifts as stated by the PLL megawizard plug-in manager. The custom logic "A" (clocked at 48MHz) receives some input signals from the custom logic "B" (clocked at 24MHz). The question is: do the custom logic "B" signals have to be syncronized with the 48MHz clock ? Does the metastability issue apply also if the 24MHz clock is strictly derived from the 48MHz one ? Best Regards /AlessandroArticle: 149833
On 11/25/2010 8:49 AM, Michael S wrote: > On Nov 24, 3:01 pm, gnirre<gni...@gmail.com> wrote: >> On Nov 24, 12:03 am, Thomas Entner<thomas.ent...@entner- >> >> >> >> So Stellarton is basically a product that is the optimal choice for >> almost no application, almost always too small, or too expensive. >> >> So why did Intel have this one built? > > Being cynical, because they have MCM technology. > Unlike current generation, Intel's next generation desktop/laptop > processors are single die so the MCM packaging guys @Intel will have > to go unless there is something new to keep them busy. MCM is a great way to build real world prototype products. Place two or more chips in a package, sell it at a reasonable price - and if a lot of people buy it, then and only then should you invest in a design team to put it into a single chip and reduce costs. Avoids those pointless hypothetical arguments about what people would buy. This way, you get to find out. Of course, in this case it is a real world prototype of a chip good for prototyping. Plus - with MCM you can imagine doing stuff that we can't currently put on the same die. RF?Article: 149834
alessandro.strazzero@gmail.com <alessandro.strazzero@gmail.com> wrote: > I'm a newbye in VHDL and I would like to submit a question. I have a > system wich is clocked at 24MHz by an external oscillator. > This clock is the input of a PLL internal to the FPGA. > The outputs of the PLL are two clocks: one at 48MHz to clock > a CPU and a custom logic called "A", and the other one at 24MHz to > clock a custom logic called "B". (snip) > The question is: do the custom logic "B" signals have to be > syncronized with the 48MHz clock ? If you can meet the setup and hold times, then you are safe. -- glenArticle: 149835
> Intel site doesn't tell us which Altera chip they are using, but from > description it looks like EP2AGX65. It is an Altera Arria II GX, so you might well be right.Article: 149836
Hi, I have V6 design which instantiates a number (6) idelayctrl primitives. (They're not really different, it just turned out easier to structure the code that way.) Recently, a co-worker modified the design so that the module hierarchy is slightly different, in that the module containing four of the idelayctrl primitives is now one level deeper in the hierarchy. I am reasonably sure that there were no functional changes to the code, just a change in hierarchy. With the change, XST silently removes the four idelayctrl from the design. In the resource utilization (sic) part of the synthesis report file, it says it uses 2 idelayctrl. If I revert the changes in the source files and run XST again, it reports 6 idelayctrl. Can someone please give me a hint as to what's going on? I suspect there is a rule that XST follows regarding merging of idelayctrl primitives, but I can't find anything about it in any documentation. TIA, AllanArticle: 149837
On Nov 25, 4:18=A0pm, "alessandro.strazz...@gmail.com" <alessandro.strazz...@gmail.com> wrote: > Hi all, > > I'm a newbye in VHDL and I would like to submit a question. I have a > system wich is clocked at 24MHz by > an external oscillator. This clock is the input of a PLL internal to > the FPGA. The outputs of the PLL are > two clocks: one at 48MHz to clock a CPU and a custom logic called "A", > and the other one at 24MHz to > clock a custom logic called "B". These two clocks are produced without > phase shifts as stated by the PLL > megawizard plug-in manager. > > The custom logic "A" (clocked at 48MHz) receives some input signals > from the custom logic "B" (clocked at > 24MHz). The question is: do the custom logic "B" signals have to be > syncronized with the 48MHz clock ? > Does the metastability issue apply also if the 24MHz clock is strictly > derived from the 48MHz one ? > > Best Regards > > /Alessandro In general, if you don't need domains to be synchronous, you should specify TIG constraints between the domains so the tool doesn't have to spend time timing those paths, which improves overall time-cost budget. If you want the domains to be synchronous, beings that both clocks are derived as simple multiple (1x/2x) and from the same PLL, this is no problem. The tool should time those paths as if they are synchronous by default as long as you put your clock constraint on the input to the PLL. And both of these type of outputs from the same PLL typically have a low-skew characteristic between these outputs of the same PLL. JohnArticle: 149838
On Nov 25, 4:18=A0pm, "alessandro.strazz...@gmail.com" <alessandro.strazz...@gmail.com> wrote: > Hi all, > > I'm a newbye in VHDL and I would like to submit a question. I have a > system wich is clocked at 24MHz by > an external oscillator. This clock is the input of a PLL internal to > the FPGA. The outputs of the PLL are > two clocks: one at 48MHz to clock a CPU and a custom logic called "A", > and the other one at 24MHz to > clock a custom logic called "B". These two clocks are produced without > phase shifts as stated by the PLL > megawizard plug-in manager. > > The custom logic "A" (clocked at 48MHz) receives some input signals > from the custom logic "B" (clocked at > 24MHz). The question is: do the custom logic "B" signals have to be > syncronized with the 48MHz clock ? > Does the metastability issue apply also if the 24MHz clock is strictly > derived from the 48MHz one ? > > Best Regards > > /Alessandro Your synthesis/place and route/timing tools will likely properly constrain data moving from the B to the A clock domain (i.e. accounting for whatever phase offset there may be in the actual implementation). That said, it's common to implement a proper clock domain crossing in a case like this, even if it's just a simple clock enable transfer. ChrisArticle: 149839
On Nov 25, 6:51=A0am, David Brown <da...@westcontrol.removethisbit.com> wrote: > On 24/11/2010 20:38, rickman wrote: > > > > > On Nov 16, 6:09 am, David Brown<da...@westcontrol.removethisbit.com> > > wrote: > >> On 15/11/2010 19:21, rickman wrote: > > >> My gut feeling here is that you are not going to get significant > >> resonance between the power plane and the bypass capacitors, especiall= y > >> if the power "plane" is actually just a polygon, and therefore fairly > >> small, while the capacitors are large. =A0The power "plane" is then fa= r > >> too small in comparison to have a noticeable effect on the bypass > >> capacitor, and therefore the bypass capacitor will work as expected. > >> The power "plane" (viewed as a capacitor) is mainly for bypassing very > >> high frequencies - these will be isolated from the bypass capacitors b= y > >> the capacitors' inductance and ESR, thus it will also continue to work > >> as expected. > > > I have no idea why your gut feels the way it does. =A0All you need to d= o > > is gin up a simple spice circuit and check its response vs. > > frequency.... at high frequencies, say 100 MHz to 5 GHz. =A0You will se= e > > this clearly. =A0The idealized circuit does perform worse than a real > > circuit because this is one of the times when the parasitic effects > > can help you. =A0The ESR of the cap prevents it from having a sharp Q > > and a very high impedance at resonance. =A0But it will have a resonance > > and it can easily create a problem at some specific frequency. > > > The seat of the pants analysis you gave has nothing to do with the > > resonance effect. =A0In fact, you seem to think the inductance of the > > bypass caps "isolate" them from a resonance effect while it is this > > inductance that *creates* the resonance when coupled with the power > > planes capacitance. > > Yes, that is pretty much how I thought - but you have given me cause to > think again. =A0I will have to take your advice and try some simulations = - > that's probably the best way for me to see what's happening, where the > resonances are coming from, and the sort of effect they have. =A0Until I > have proved otherwise, I'll take your word over my gut feeling here. > > > > >> And again the disclaimer - I haven't worked with this sort of thing in > >> practice (the fastest card I have made was about 200 MHz), nor have I > >> studied the theory or the maths here in detail. =A0My theories are bas= ed > >> on reading articles and guides, thinking about how things work, readin= g > >> c.a.f., etc. =A0I am posting here to ask and learn, and perhaps also t= o > >> make the experts here think. > > > Please do some searches on power supply decoupling and resonance > > effects. =A0I am sure Lee Ritchey is not the only person who knows abou= t > > this. =A0I heard it from others before him, but didn't take it > > seriously. > > The thing about searching on-line for this sort of thing is that there > is no consistency in the answers. =A0Either there are several different > ways to do good bypassing, or the reality is that it doesn't matter too > much. =A0But it's easy to find "experts" (some of whom may actually /be/ > expert) advocating multiple large power planes, or no power planes, lots > of capacitors or few capacitors, lots of capacitor values or few > capacitors, capacitors placed on the backside under the component or > capacitors just roughly in the neighbourhood. Once I took Lee Ritchey's course, I realized that as you say, the experts disagree on how to design power delivery systems. So now when I hear someone, no matter who, say something about a topic, not just power systems, I look behind what they are saying at the proof. If it isn't there, I view it with a cautious eye. For power delivery, check out Lee Ritchey's web site called, "The Speeding Edge". They sell a book which I think has been updated and/or expanded since I took the class. It may be well worth the few bucks it costs. Even better, and much more expensive, is the class. If you are local to where it is being presented, I think the class is only a kilobuck or two. I found it well worth the money although it wasn't my money... > A bit of spice simulation is what I need here. > > > One thing about power supply system design and decoupling... it is not > > hard to make one that works. =A0But to know that it will work before yo= u > > build it, that takes some knowledge. =A0The old rule of thumb of adding > > a cap per power pin is pretty useless. =A0So too are all the other > > "guidelines" that aren't based on theory, simulation and testing... > > all three. =A0There are lots of things that may sound good until you > > actually verify them. =A0The single most surprising fact I got from the > > high speed digital design course was that not only are much fewer caps > > needed than expected, but they don't need to be especially close to > > the power and ground pins of the chip! > > On the boards I have worked on (which were not more than about 200 MHz), > I didn't have nearly as many as one capacitor per power pin, and I > scattered them around to a fair extent. =A0So my "gut feeling" gave me a > similar result in the end. 200 MHz is actually pretty fast. The edge rate of a 5 ns clock has very high freq harmonics. That is what you need to be concerned about. If you did well on that design, then you must have done something right. But in the real world just because your design worked, it doesn't mean your approach is always sound. I still don't have as much confidence in applying these ideas as I would like. But then most designs don't need all that much attention to power. The question is how do you know unless you actually do the math on the entire board? Let us know what find in your simulations. RickArticle: 149840
On 26/11/2010 16:04, rickman wrote: > On Nov 25, 6:51 am, David Brown<da...@westcontrol.removethisbit.com> > wrote: >> On 24/11/2010 20:38, rickman wrote: >> >>> Please do some searches on power supply decoupling and resonance >>> effects. I am sure Lee Ritchey is not the only person who knows about >>> this. I heard it from others before him, but didn't take it >>> seriously. >> >> The thing about searching on-line for this sort of thing is that there >> is no consistency in the answers. Either there are several different >> ways to do good bypassing, or the reality is that it doesn't matter too >> much. But it's easy to find "experts" (some of whom may actually /be/ >> expert) advocating multiple large power planes, or no power planes, lots >> of capacitors or few capacitors, lots of capacitor values or few >> capacitors, capacitors placed on the backside under the component or >> capacitors just roughly in the neighbourhood. > > Once I took Lee Ritchey's course, I realized that as you say, the > experts disagree on how to design power delivery systems. So now when > I hear someone, no matter who, say something about a topic, not just > power systems, I look behind what they are saying at the proof. If it > isn't there, I view it with a cautious eye. For power delivery, check > out Lee Ritchey's web site called, "The Speeding Edge". They sell a > book which I think has been updated and/or expanded since I took the > class. It may be well worth the few bucks it costs. Even better, and > much more expensive, is the class. If you are local to where it is > being presented, I think the class is only a kilobuck or two. I found > it well worth the money although it wasn't my money... > I've read a few things on "The Speeding Edge" - there was a lot of good stuff there. Maybe sometime I'll get the book, though I already have too many text books on my shelf waiting to be read! And I doubt if I'll make it to class - I don't think Norway counts as "local" in this case! > >> A bit of spice simulation is what I need here. >> >>> One thing about power supply system design and decoupling... it is not >>> hard to make one that works. But to know that it will work before you >>> build it, that takes some knowledge. The old rule of thumb of adding >>> a cap per power pin is pretty useless. So too are all the other >>> "guidelines" that aren't based on theory, simulation and testing... >>> all three. There are lots of things that may sound good until you >>> actually verify them. The single most surprising fact I got from the >>> high speed digital design course was that not only are much fewer caps >>> needed than expected, but they don't need to be especially close to >>> the power and ground pins of the chip! >> >> On the boards I have worked on (which were not more than about 200 MHz), >> I didn't have nearly as many as one capacitor per power pin, and I >> scattered them around to a fair extent. So my "gut feeling" gave me a >> similar result in the end. > > 200 MHz is actually pretty fast. The edge rate of a 5 ns clock has > very high freq harmonics. That is what you need to be concerned > about. If you did well on that design, then you must have done > something right. But in the real world just because your design > worked, it doesn't mean your approach is always sound. I still don't > have as much confidence in applying these ideas as I would like. But > then most designs don't need all that much attention to power. The > question is how do you know unless you actually do the math on the > entire board? > > Let us know what find in your simulations. > > RickArticle: 149841
On Thu, 25 Nov 2010 13:18:09 -0800 (PST), "alessandro.strazzero@gmail.com" <alessandro.strazzero@gmail.com> wrote: >Hi all, > >I'm a newbye in VHDL and I would like to submit a question. I have a >system wich is clocked at 24MHz by >an external oscillator. This clock is the input of a PLL internal to >the FPGA. The outputs of the PLL are >two clocks: one at 48MHz to clock a CPU and a custom logic called "A", >and the other one at 24MHz to >clock a custom logic called "B". These two clocks are produced without >phase shifts as stated by the PLL >megawizard plug-in manager. > Even with phase-shifts, >The custom logic "A" (clocked at 48MHz) receives some input signals >from the custom logic "B" (clocked at >24MHz). The question is: do the custom logic "B" signals have to be >syncronized with the 48MHz clock ? you don't need synchronization. Timing engine knows the relative output delays of the PLL and adjusts the paths accordingly. >Does the metastability issue apply also if the 24MHz clock is strictly >derived from the 48MHz one ? No. As long as you compensate for the phase (which is no different from building a good clock tree) you can meet setup/hold which is all you need for this case. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149842
On Nov 25, 5:26=A0am, Philippe <philippe.f...@gmail.com> wrote: > On Nov 24, 8:22=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I wish I had a smart(er) editor that understood VHDL a bit more. > > Hi Rick, > > You might want to take a look at Sigasi:http://www.sigasi.com > We have a VHDL development environment with a VHDL parser inside. This > way, as you put it, the VHDL editor "understands" what you type. > > > I have some search/replace regex strings I copy and paste from one file > > to another which change an entity port list into a port map or a > > signal list. =A0This helps with the tedium of instantiation. > > Thirty second screencast on instantiations:http://www.sigasi.com/screenca= st/entity-instantiation > > kind regards > > -- > Philippe Faes > Sigasi To what extent does the editor "understand" the VHDL I type? I am already using an editor that recognizes keywords, comments, numbers, ect... and colors them as I require. What more does the Sigasi editor do? RickArticle: 149843
On Oct 9, 5:44=A0am, "pfaisalbe" <pfaisalbe@n_o_s_p_a_m.gmail.com> wrote: > Hi > > I am using Xilinx Sapartan 3 . I have wrote HDL in verilog for testing an > external memory attached to FPGA. Mapping end up with error. > > Pack:2309 -Toomanybondedcompsof type "IOB" found to fit this device. > > I am a beginner in this field. In the first place , It seems that I am > using more resources than the FPGA can provide ? . > > Please suggest , =A0how to get rid of this error > > Thanks and Regards > > Faisal > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com This just started happening to an existing design that I migrated from ISE 11.5 to 12.3. No idea why, as the floorplan is nowhere near full. You might try building your project under ISE 11. -- john, KE5FXArticle: 149844
Hallo! I'm only starting with Xilinx EDK, so i'm sorry for my probably stupid question. Also my english is not a perfect. The problem is: I use Xilinx EDK 10.1 and ModelSim SE 6.3d. I made a simple project (led blink) with Microblaze and try to do behavioral simulation from EDK (I have compiled sim libraries, generate simulation files and run ModelSim). But when I run the simulation in Modelsim i see, that many signals are in 'U' or 'X' state and the project didn't work in a right way at all. Then I tried to do a structural model simulation and i was wondered that it worked perfect! For structural model simulation i did all the same things as for behavioral (and of course i didn't change anything in my hardware or software). Tell me, please, what I have done wrong? I can't understand why I can't do a behavioral simulation, but structural simulation work in a right way? Thank you for attention, I really need your help. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149845
I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDIF netlist of my program which is write as a behavioral verilog code. Suppose I write the code (a+b), than I could see in the RTL and Technology schematics that a full-adder has been created inside a LUT but i want to access the EDIF netlist of this RTL diagram created by XIlinx. Moreover, I learned in the Xilinx Development Reference Guide that the NGD netlist is a logical description of the circuit whereas the NGD netlist Xilinx created for my programs are totally vague. It seems like it is based on the local primitives of the xilinx board but atleast no logical description is available. Thanks for your time. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149846
Hi All,
I am compiling a SOPC project with a user developed IP. When I compiling
the user IP alone, everything is fine, no error reported. However when I
compiling the SOPC project (user IP+ microblaze soft core + some xilinx IP
cores), I got the following error message:
Pack:1653 - At least one timing constraint is impossible to meet because
component delays alone exceed the constraint......
The log is as follows:
INFO:Timing:3284 - This timing report was generated using estimated delay
information. For accurate numbers, please refer to the post Place and
Route
timing report.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case |
Best Case | Timing | Timing
| | Slack |
Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -0.723ns|
7.781ns| 18| 7173
G_DCM0_CLKFX = PERIOD TIMEGRP "clock_gene | HOLD | 0.188ns|
| 0| 0
rator_0_clock_generator_0_SIG_DCM0_CLKFX" | | |
| |
TS_sys_clk_pin * 2.4 HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | 3.303ns|
3.394ns| 0| 0
G_DCM0_CLK0 = PERIOD TIMEGRP "clock_gener | HOLD | -0.456ns|
| 288| 24751
ator_0_clock_generator_0_SIG_DCM0_CLK0" T | | |
| |
S_sys_clk_pin HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* TS_clock_generator_0_clock_generator_0_SI | SETUP | -0.404ns|
29.688ns| 4| 1612
G_DCM0_CLKDV = PERIOD TIMEGRP "clock_gene | HOLD | -0.189ns|
| 497| 9610
rator_0_clock_generator_0_SIG_DCM0_CLKDV" | | |
| |
TS_sys_clk_pin / 2 HIGH 50% | | |
| |
----------------------------------------------------------------------------------------------------------
* NET "fpga_0_Ethernet_MAC_PHY_rx_clk_pin_I | SETUP | 12.323ns|
4.791ns| 0| 0
BUF" PERIOD = 40 ns HIGH 14 ns | HOLD | -0.186ns|
| 48| 5976
..........
However, I did not set any timing constrains in the UCF file. The above
timing constrains were generate by the system in the system.pcf file.
It seems that the error is caused by a DCM, it looks very strange. If I
compile the system without user IP, no error reported. If I compile the
user IP alone, still no error. However, if I compile the whole system +
user IP, the error appeared. Can anyone kindly tell me how to solve this
problem?
Many thanks!
regards
sam
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 149847has really nobody a hint for me regarding this subject? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149848
"Jahanzebanwer" <jahanzebanwer2002@n_o_s_p_a_m.gmail.com> writes: > I am using Xilinx Project Navigator ISE 8.1i. I want to access the EDIF Your installation might contain the program ngc2edif which can be used to convert from the Xilinx netlist format to EDIF. Petter -- .sig removed by request.Article: 149849
Do you have 2 DCMs in your design? You might have a clock generator in the processor module and another dcm external to the processor. Jon --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z