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Hi, I an new to FPGA develepement and I want to build a litte embeded system using the SP601 SPARTAN-6, to develepod my VHDL,c++ and PCB skill. But I dont kwon if my projet is realitical, so I seek input from experience developer here, before I buy the stuff. I am currently designing a dauterboard for the SP601 kit to the include the folowing periferals : - tft LCD http://www.sparkfun.com/products/8335 - 1 or more CMOS camera like this one http://www.sparkfun.com/products/8667 - an audio codex (to be chosen) - SD card reade As a first projet with this board. I would like to code in VHDL the LCD and camera controler and use the microblaze softcore to devepod in c++ a GUI using the QT tools (http://qt.nokia.com/). So basically I want the user to be able to take a shot using the GUI control and display it to the LCD. Latter I would like to implement function like music and video player and maybe latter implement some cool computer vision processing using the openCV library and dedicated FPGA hardware. 1) Do this look possible to you ? 2) is the microblaze core able to handle the QT and OpenCV lib ? 3) any suggestion to help me get that project started ? Thx for your inputs Eric --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149901
> I think you intended to say 8MB/s and 60MB/s right? Yes sorry, Bytes not bits. > And Nial, have you ever developed a PCI driver to Linux? I am trying to > work with the example i posted on my last post and LDD third edition, but i > still got many doubts... No, that's always been someone else's problem! :-) Nial.Article: 149902
On 12/1/2010 7:13 AM, Sink0 wrote: >> I think I managed ~ 8Mb/s using target reads, bursting you can aim for >> ~60Mb/s (in a system with other things on the PCI bus). >> >> >> Nial >> > > I think you intended to say 8MB/s and 60MB/s right? > > And Nial, have you ever developed a PCI driver to Linux? I am trying to > work with the example i posted on my last post and LDD third edition, but i > still got many doubts... > > Thabk you! > > --------------------------------------- > Posted through http://www.FPGARelated.com As a note, while I haven't done any Linux driver development our former programmer did. He said that LDD 3rd ed. is chock full o' both errata and things that were only true under the 2.4 kernel, not 2.6. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 149903
rickman wrote:
>
>
> Yes, if "only full word match" is used, then "write_n" won't match a
> "write" search and replace so only "write" will change.
It seems that you do not appreciate the difference between Rename
and global search and replace yet.
The same identifier may refer to a lot of different objects in
a design. Rename is based on object identify, not identifier identity.
This makes it intelligent and safe.
1 minute screencast on Rename (no sound as yet):
http://www.sigasi.com/screencast/rename
> And those completions include both keywords as well as your signal/
> variable names? If this feature works well enough I might consider
> Sigasi. Especially if it could be used for other languages than just
> VHDL. Is the VHDL aspect hard coded? I expect it will also support
> Verilog, but what about generic languages? Does it have a means of
> setting it up for an arbitrary language like CW does?
Sigasi HDT is available as a plugin to a standard Eclipse installation,
which means that it plays well with thousands of open-source and
commercial plugins from other parties. More info:
http://www.sigasi.com/download
Sigasi HDT itself has no Verilog support yet.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Python as a HDL: http://www.myhdl.org
VHDL development, the modern way: http://www.sigasi.com
Analog design automation: http://www.mephisto-da.com
World-class digital design: http://www.easics.com
Article: 149904On Dec 1, 12:20=A0pm, Jan Decaluwe <j...@jandecaluwe.com> wrote: > rickman wrote: > > > Yes, if "only full word match" is used, then "write_n" won't match a > > "write" search and replace so only "write" will change. > > It seems that you do not appreciate the difference between Rename > and global search and replace yet. > > The same identifier may refer to a lot of different objects in > a design. Rename is based on object identify, not identifier identity. > This makes it intelligent and safe. Oh? How does that work. When can you use the same name for different objects??? Why would you if you can? > 1 minute screencast on Rename (no sound as yet): > > =A0 =A0http://www.sigasi.com/screencast/rename > > > And those completions include both keywords as well as your signal/ > > variable names? =A0If this feature works well enough I might consider > > Sigasi. =A0Especially if it could be used for other languages than just > > VHDL. =A0Is the VHDL aspect hard coded? =A0I expect it will also suppor= t > > Verilog, but what about generic languages? =A0Does it have a means of > > setting it up for an arbitrary language like CW does? > > Sigasi HDT is available as a plugin to a standard Eclipse installation, > which means that it plays well with thousands of open-source and > commercial plugins from other parties. More info: I don't use eclipse or any plugins of that nature. > =A0 =A0http://www.sigasi.com/download > > Sigasi HDT itself has no Verilog support yet. There is a definite strike against it. I had planned to spend some time this year learning Verilog at least well enough to figure out if I wanted to make it my primary HDL. It seems very limiting to use a tool that works great for only one language. RickArticle: 149905
On Nov 30, 6:11=A0pm, rickman <gnu...@gmail.com> wrote: > On Nov 30, 9:58 am, Gabor <ga...@alacron.com> wrote: > > > > > On Nov 30, 8:46 am, rickman <gnu...@gmail.com> wrote: > > > > On Nov 30, 2:35 am, Newman <newman5...@yahoo.com> wrote: > > > > > On Nov 29, 11:54 pm, rickman <gnu...@gmail.com> wrote: > > > > > > I'm not sure what is wrong here. I have a design that I have used= in > > > > > the past and has worked ok. I am making modifications to it and m= y Hi- > > > > > Z outputs are being grounded. This creates some problems during > > > > > operation. The VHDL code is like this... > > > > > > TMS_B1 <=3D 'Z'; > > > > > > I just want this output to be Hi-Z for this design so that the pi= n > > > > > output is not driven (which clobbers these signals from other > > > > > sources). The lines for this output in the preference file are... > > > > > > LOCATE COMP "TMS_B1" SITE "36" ; > > > > > IOBUF PORT "TMS_B1" IO_TYPE=3DLVCMOS33 PULLMODE=3DKEEPER DRIVE=3D= 8 > > > > > SLEWRATE=3DSLOW ; > > > > > > When I load the design into the part, the output is always low an= d > > > > > checking the design in Epic, I see the tri-state driver has a 0 o= n the > > > > > input and a 0 on the enable. I believe the 0 on the enable turns = on > > > > > the output driver because that is how the outputs are configured. > > > > > > I also looked at the Technology View in Synplify and I find TMS_B= 1 is > > > > > driven by a OB with a 0 on it's input. > > > > > > Is this a bug or is there something wrong with the way I am doing > > > > > this? I made a lot of changes to the overall design before I > > > > > discovered this bug so I'm not certain that the preference file l= ines > > > > > have not been changed since this was working, but I don't see how= they > > > > > can be causing this problem. > > > > > > Rick > > > > > Rick, > > > > I suppose you have already convinced yourself that it is not the > > > > buskeeper circuit driving the line low. > > > > > Bus Maintenance Circuit > > > > Each pad has a weak pull-up, weak pull-down and weak buskeeper > > > > capability. The pull-up and pull-down settings > > > > offer a fixed characteristic, which is useful in creating wired log= ic > > > > such as wired ORs. However, current can be > > > > slightly higher than other options, depending on the signal state. = The > > > > bus-keeper option latches the signal in the > > > > last driven state, holding it at a valid level with minimal power > > > > dissipation. Users can also choose to turn off the bus > > > > maintenance circuitry, minimizing power dissipation and input leaka= ge. > > > > Note that in this case, it is important to > > > > ensure that inputs are driven to a known state to avoid unnecessary > > > > power dissipation in the input buffer. > > > > Thanks for the suggestion, but yes, I eliminated that by looking at > > > the I/O block settings in Epic, the layout editor. =A0I originally sa= w > > > this problem with an LED driving pin. =A0I set it for hi-z and it was > > > driving the LED on hard. =A0A bus keeper wouldn't drive that hard. > > > Besides, this pin is driving two LEDs, one up and one down. =A0Hi-z i= s > > > the only state where neither LED is on. =A0When I use logic to select > > > the three states, 1, 0, Z; then the hi-z state is enabled > > > appropriately. > > > > I can always work around this by controlling it from some signal such > > > as reset so that it is always hi-z after the FPGA is up. =A0It is odd > > > that this worked just fine before and now screws up. =A0I haven't > > > updated any of the development software that I know of, but I haven't > > > messed with this design since 2008, so there's been a lot of water > > > under the dam since then. =A0If it is a tool problem, I may not get a= n > > > update. =A0My maintenance ran out long ago and this is a paid for cop= y. > > > I'd hate to have to shell out a kilobuck to get a bug fix so I can > > > continue using the software that I already paid for. > > > > Rick > > > This looks remarkably like something I remember from older Xilinx > > projects where assigning an output to 'Z' effectively removed it from > > the > > design. =A0(the output isn't "driven" so get rid of it) =A0Then the > > default > > action for the backend tools is to take any undriven outputs and > > ground them (you must have forgotten to assign a value to this). > > > What would happen if you changed the output so it is only tristate > > under some condition? =A0You could pick some condition that you > > know is always true, but the synthesizer can't guess, or make the > > output briefly drive (high or low) as the design comes out of reset. > > > Does your project perhaps have a setting or unused IOB's to > > be "virtual grounds"? > > > All I can think of... > > > -- Gabor > > Hi Gabor. =A0I also have outputs driving pairs of LEDs that are > conditional and can be either '0', '1' or 'Z'. =A0They work just fine. > In fact, I first saw this on LED drive outputs that I drove with a > 'Z'. =A0The red LEDs came on which means it was pulled hard to ground. > I turned off the buskeeper mode and it still drove the output hard to > ground. =A0That was when I first looked at the design in Epic and saw > the tri-state control driven to a fixed '0' instead of a fixed '1', > like it is now! =A0If I hadn't see this before, it would have been ten > times harder to figure out what was keeping my programming cable from > working with by target boards! =A0These JTAG signals are also connected > to the test fixture FPGA in case I get to the point where I want the > FPGA to program the target boards instead of using the Lattice > software. =A0Oddly enough, Lattice cautions you against using the USB > cable for production programming. =A0I guess this is just a CYA thing in > case it doesn't work correctly and you ship 10,000 boards that aren't > programmed right... "don't come back to us"! > > I had considered controlling the tri-states with some signal that > would not conflict with an external driver of the JTAG signals, such > as the GSR or maybe a switch input. =A0But the issue seems to have > resolved itself. =A0I'm not sure I will ever know what was wrong unless > it returns. =A0I know the preference file gets rewritten each time I run > the tool, but I can't say the file actually changes. =A0I haven no idea > why it has to write the file back out each time. =A0The only thing it > seems to change is when I put a title block at the head of the file, > the tools keep writing the line, "COMMERCIAL;" just in front of it. > No matter where I put this line in the file, it gets moved to the > first line. > > If nothing else, it helps to have others make suggestions. =A0It can be > easier to figure things out when you have to explain something and > think about other's comments. =A0Thanks. > > Rick Rick, It is odd, and I completely understand your frustration. To analyze why this happened, one will need your whole project data-base and I'll have to ask you to engage your local FAE, if you decide to go this way... Also if it is a bug in the SW, then very possibly you won't see it in a later release (the release 7.2 SP2 you're using is two revs behind, we have ispLever 8.1 sp1 now and also the new Diamond SW). The good news is that you can use Lattice free Starter SW to support the part you're using (all Lattice non-volatile families are fully covered by the free SW option, you'll need non-free SW only for FPGA with multi-GB transceivers -SERDES's in Lattice terminology). So I'd suggest to download the latest ispLever Starter SW and try to use it. Another thing that I wanted to mention is that you can also try to use the free version of Lattice new Diamond SW. The point tools are the same but the GUI is considerably improved (and, of course changed...). We're getting quite positive feedback from all the customers who tried the new SW. Alex Lattice FAE, writing from homeArticle: 149906
On Dec 1, 2:09=A0pm, Alex <engin...@gmail.com> wrote: > On Nov 30, 6:11=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Nov 30, 9:58 am, Gabor <ga...@alacron.com> wrote: > > > > On Nov 30, 8:46 am, rickman <gnu...@gmail.com> wrote: > > > > > On Nov 30, 2:35 am, Newman <newman5...@yahoo.com> wrote: > > > > > > On Nov 29, 11:54 pm, rickman <gnu...@gmail.com> wrote: > > > > > > > I'm not sure what is wrong here. I have a design that I have us= ed in > > > > > > the past and has worked ok. I am making modifications to it and= my Hi- > > > > > > Z outputs are being grounded. This creates some problems during > > > > > > operation. The VHDL code is like this... > > > > > > > TMS_B1 <=3D 'Z'; > > > > > > > I just want this output to be Hi-Z for this design so that the = pin > > > > > > output is not driven (which clobbers these signals from other > > > > > > sources). The lines for this output in the preference file are.= .. > > > > > > > LOCATE COMP "TMS_B1" SITE "36" ; > > > > > > IOBUF PORT "TMS_B1" IO_TYPE=3DLVCMOS33 PULLMODE=3DKEEPER DRIVE= =3D8 > > > > > > SLEWRATE=3DSLOW ; > > > > > > > When I load the design into the part, the output is always low = and > > > > > > checking the design in Epic, I see the tri-state driver has a 0= on the > > > > > > input and a 0 on the enable. I believe the 0 on the enable turn= s on > > > > > > the output driver because that is how the outputs are configure= d. > > > > > > > I also looked at the Technology View in Synplify and I find TMS= _B1 is > > > > > > driven by a OB with a 0 on it's input. > > > > > > > Is this a bug or is there something wrong with the way I am doi= ng > > > > > > this? I made a lot of changes to the overall design before I > > > > > > discovered this bug so I'm not certain that the preference file= lines > > > > > > have not been changed since this was working, but I don't see h= ow they > > > > > > can be causing this problem. > > > > > > > Rick > > > > > > Rick, > > > > > I suppose you have already convinced yourself that it is not the > > > > > buskeeper circuit driving the line low. > > > > > > Bus Maintenance Circuit > > > > > Each pad has a weak pull-up, weak pull-down and weak buskeeper > > > > > capability. The pull-up and pull-down settings > > > > > offer a fixed characteristic, which is useful in creating wired l= ogic > > > > > such as wired ORs. However, current can be > > > > > slightly higher than other options, depending on the signal state= . The > > > > > bus-keeper option latches the signal in the > > > > > last driven state, holding it at a valid level with minimal power > > > > > dissipation. Users can also choose to turn off the bus > > > > > maintenance circuitry, minimizing power dissipation and input lea= kage. > > > > > Note that in this case, it is important to > > > > > ensure that inputs are driven to a known state to avoid unnecessa= ry > > > > > power dissipation in the input buffer. > > > > > Thanks for the suggestion, but yes, I eliminated that by looking at > > > > the I/O block settings in Epic, the layout editor. =A0I originally = saw > > > > this problem with an LED driving pin. =A0I set it for hi-z and it w= as > > > > driving the LED on hard. =A0A bus keeper wouldn't drive that hard. > > > > Besides, this pin is driving two LEDs, one up and one down. =A0Hi-z= is > > > > the only state where neither LED is on. =A0When I use logic to sele= ct > > > > the three states, 1, 0, Z; then the hi-z state is enabled > > > > appropriately. > > > > > I can always work around this by controlling it from some signal su= ch > > > > as reset so that it is always hi-z after the FPGA is up. =A0It is o= dd > > > > that this worked just fine before and now screws up. =A0I haven't > > > > updated any of the development software that I know of, but I haven= 't > > > > messed with this design since 2008, so there's been a lot of water > > > > under the dam since then. =A0If it is a tool problem, I may not get= an > > > > update. =A0My maintenance ran out long ago and this is a paid for c= opy. > > > > I'd hate to have to shell out a kilobuck to get a bug fix so I can > > > > continue using the software that I already paid for. > > > > > Rick > > > > This looks remarkably like something I remember from older Xilinx > > > projects where assigning an output to 'Z' effectively removed it from > > > the > > > design. =A0(the output isn't "driven" so get rid of it) =A0Then the > > > default > > > action for the backend tools is to take any undriven outputs and > > > ground them (you must have forgotten to assign a value to this). > > > > What would happen if you changed the output so it is only tristate > > > under some condition? =A0You could pick some condition that you > > > know is always true, but the synthesizer can't guess, or make the > > > output briefly drive (high or low) as the design comes out of reset. > > > > Does your project perhaps have a setting or unused IOB's to > > > be "virtual grounds"? > > > > All I can think of... > > > > -- Gabor > > > Hi Gabor. =A0I also have outputs driving pairs of LEDs that are > > conditional and can be either '0', '1' or 'Z'. =A0They work just fine. > > In fact, I first saw this on LED drive outputs that I drove with a > > 'Z'. =A0The red LEDs came on which means it was pulled hard to ground. > > I turned off the buskeeper mode and it still drove the output hard to > > ground. =A0That was when I first looked at the design in Epic and saw > > the tri-state control driven to a fixed '0' instead of a fixed '1', > > like it is now! =A0If I hadn't see this before, it would have been ten > > times harder to figure out what was keeping my programming cable from > > working with by target boards! =A0These JTAG signals are also connected > > to the test fixture FPGA in case I get to the point where I want the > > FPGA to program the target boards instead of using the Lattice > > software. =A0Oddly enough, Lattice cautions you against using the USB > > cable for production programming. =A0I guess this is just a CYA thing i= n > > case it doesn't work correctly and you ship 10,000 boards that aren't > > programmed right... "don't come back to us"! > > > I had considered controlling the tri-states with some signal that > > would not conflict with an external driver of the JTAG signals, such > > as the GSR or maybe a switch input. =A0But the issue seems to have > > resolved itself. =A0I'm not sure I will ever know what was wrong unless > > it returns. =A0I know the preference file gets rewritten each time I ru= n > > the tool, but I can't say the file actually changes. =A0I haven no idea > > why it has to write the file back out each time. =A0The only thing it > > seems to change is when I put a title block at the head of the file, > > the tools keep writing the line, "COMMERCIAL;" just in front of it. > > No matter where I put this line in the file, it gets moved to the > > first line. > > > If nothing else, it helps to have others make suggestions. =A0It can be > > easier to figure things out when you have to explain something and > > think about other's comments. =A0Thanks. > > > Rick > > Rick, > > It is odd, and I completely understand your frustration. To analyze > why this happened, one will need your whole project data-base and I'll > have to ask you to engage your local FAE, if you decide to go this > way... > > Also if it is a bug in the SW, then very possibly you won't see it in > a later release =A0(the release 7.2 SP2 you're using is two revs behind, > we have ispLever 8.1 sp1 now and also the new Diamond SW). > > The good news is that you can use Lattice free Starter SW to support > the part you're using (all Lattice non-volatile families are fully > covered by the free SW option, you'll need non-free SW only for FPGA > with multi-GB transceivers -SERDES's in Lattice terminology). So I'd > suggest to download the latest ispLever Starter SW and try to use it. > > Another thing that I wanted to mention is that you can also try to use > the free version of Lattice new Diamond SW. The point tools are the > same but the GUI is considerably improved (and, of course changed...). > We're getting quite positive feedback from all the customers who tried > the new SW. Hi Alex, Thanks again for the reply. I likely won't pursue this unless the symptom returns. I have never really understood what is provided with what versions of the software. The reason that I paid for a copy two years (or more) ago was because the simulation was not included with the free versions. Is that no longer true? Can I simulate my designs with the starter package now? If so, I guess I don't need to keep my paid for package and can switch to the free, but up to date tools. RickArticle: 149907
On 11/24/2010 05:58 PM, Thomas Womack wrote: > I think two lanes of PCI-E is a qualitatively better interface than > the parallel port in EPP mode (4 gigabit per second each way); on the > other hand you obviously don't need gigabit interface rates to go to > servo motors, and the Atom+Altera chip will be using low-voltage IO > and on aggressive lead-free BGAs so you still have the soldering > issues and need the level translators. Even one PCI-E lane would be way higher performance than the EPP parallel port. But, that requires putting a board inside the PC, rather than in the CNC machine, and also involves some IP from somebody. I don't have tools to debug the PCI-E, so if it doesn't work, I'm pretty well stuck. If the EPP parallel port has a problem, I hook up my logic analyzer and see what is wrong. Also, some of these boards I make have rows of solid state relays and wire terminal blocks, so they won't fit in a PC. Now, there is a LOT to be said for making a PCI-E adaptor, and maybe even using something like the EPP scheme, just using a much better cable allowing the speed to be turned up. A twisted-pair ribbon cable could probably handle handshaked byte transfers in 200 ns easily. So, I want to avoid BGAs (I do down to 0.4mm leaded chips), have to pretty much stay with open-source IP as I am a VERY small volume manufacturer, and probably want to keep the main board outside the PC cabinet. If I can do everything I want with the EPP parallel port, that seems to be the best solution, it keeps the system down to one board. But, the Atom + FPGA does have some possibilities, and I am certainly keeping an eye on the technology. I also have worked with the Beagle Board, and am waiting for RTAI to get ported to it to move forward on the CNC project. I have built a little TCP server based on it that operates some signal switches in an inaccessible location. JonArticle: 149908
On 11/25/2010 12:19 PM, Robert Myers wrote: > > Intel can afford to do that. In fact, it almost needs to do that, as > Intel's track record at barging into new businesses would have put any > normal company out of business, but Intel absolutely must find new > business areas and/or materially expand the territory implied by its > x86 franchise--or go the way of Continental Can. Yeah, in the old days, when porting apps and OSes to different architectures was a multi-year/multi-man project, a lock on a particular architecture was both a competitive edge AND a huge curse. Now that software can sometimes be recompiled for a different architecture literally in hours, being locked to the hoary, decades-old X86 architecture is in itself a curse, and why the ARM Cortex processors can have an entire system run on under 3 W when the Atom needs 20+. If Intel can't move to something a lot more modern and efficient, it may be NECESSARY for them to die. JonArticle: 149909
> > As a note, while I haven't done any Linux driver development our former > programmer did. =A0He said that LDD 3rd ed. is chock full o' both errata > and things that were only true under the 2.4 kernel, not 2.6. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order- Hide quoted text - > > - Show quoted text - Haha thank you for the information. Can you point me any other good reference? Other than the drivers already placed on the linux? And as you guys got some experience with PCI can you answer me some questions that are probablt veeery simple, but i cant understand? 1 - Where exactly is phisicaly placed the configuration space? At host memory? Or at the car controler? 2 - Why there are more than one BAR? I could not understand how can i configure BARs? 3 - What is an image address? 4 - What is an mask address? 5 - Why the address need to be decoded? Now questions related to the Open Cores PCI Bridge 1 - How does the adress that i am sending to the PCI is related to the wishbone address? 2 - How can i configure that? 3 - How about the oposite? How the address that i use at the wishbone side is related to the PCI message? I am reading the PCI documentation but could not understand. Thank you!Article: 149910
Hi, I'm using the Xilinx EDK 11.5. I open with XPS my reference design and loaded it via SDK. I can create valid C/C++ code and compile it without errors. Now I'm trying to debug it, without using JTAG (JTAG debugging works fine). So I choose for debugging the microblaze simulator. Everything works fine, but I can't make any output with print() or printf() because, the debugger allways tries to send the output string via uart and this logically can't work. I also set in the "OS and Libraries" page the debugger and not rs232. Is it possible to configure my system so that every output is shown in the XMD shell or somewhere else? I don't want to use the JTAG debugging because there isn't so much space on my desk. If there are any good tutorials for using SDK I'm also glad to get them :) Thanks a lot for every help. Greets TobiasArticle: 149911
Thanks for the additional responses. I'm experimenting with the Altera PCI core which can be configured to run as either a master or as a master/target. As a first step I'll implement the fpga as a PCI target and simply try to get a linux driver to read single data words from it. From what you've told me on this thread it seems I may ultimately need to run the FPGA as a master in order to get the bandwidth I need.Article: 149912
The features of this editor sound great! (Althought rickman persistently denies the usefulness of the refactoring-feature ;-) Especially the integrated error-checking would be a big help (for some reason, I have a feeled 20x more typos in the same amount of code when writing VHDL compared to e.g. C). In the moment I use mainly the editors from the vendors-IDEs, simply because they are well integrated regarding double-clicking on errors, etc., althought the editors themself, with minor differences between the vendors, quite primitive. The only thing that is not attractive is the price (also considering that it appears to be heavily based on Eclipse, an open-source- software). Maybe you can find a license-model with about a 10th of the pricing (EUR 150,- perpetual + EUR 20,- maintainance), maybe with the restriction to FPGA-use only, or small companies/private use, or something... I think this would make it more attractive to many users. Thomas www.entner-electronics.comArticle: 149913
On Nov 30, 7:05=A0am, "Gravis" <fpgarelated@n_o_s_p_a_m.adaptivetime.com> wrote: > I have a FPGA project and it needs to interface with my PC. =A0The proble= m > I've run into is finding a fast form of communication with very low > latency. =A0I've come asking for advice and possible solution. > > I need a link that can transfer 1KB 1200 times every second, not just 1.2= MB > a second because the input is dependent on the output. =A0The latency iss= ue > makes USB impossible and a normal serial port doesnt have the bandwidth. > My initial inclination was to use a IEEE 1394 connection but the interfac= e > driver ICs are both expensive and too small to solder. =A0I've looked for= an > HDL implementation of the driver but I cannot find one. =A0Does anyone kn= ow > of a way to interface with a PC that can be or has been implemented on a > FPGA or has a low component count? > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Gigabit Ethernet latency on a quiet (i.e., dedicated) port can be measured in microseconds, and your packet size is a good match for it. -- john, KE5FXArticle: 149914
On Dec 1, 1:48=A0pm, Tobias Baumann <ttob...@hotmail.com> wrote: > Hi, > > I'm using the Xilinx EDK 11.5. I open with XPS my reference design and > loaded it via SDK. > > I can create valid C/C++ code and compile it without errors. Now I'm > trying to debug it, without using JTAG (JTAG debugging works fine). So I > choose for debugging the microblaze simulator. Everything works fine, > but I can't make any output with print() or printf() because, the > debugger allways tries to send the output string via uart and this > logically can't work. > > I also set in the "OS and Libraries" page the debugger and not rs232. > > Is it possible to configure my system so that every output is shown in > the XMD shell or somewhere else? I don't want to use the JTAG debugging > because there isn't so much space on my desk. > > If there are any good tutorials for using SDK I'm also glad to get them := ) > > Thanks a lot for every help. > > Greets Tobias Would a terminal emulator on you PC work? That's what I use to capture serial debug messages. Google for "EDK Tutorial" rather than SDK - there are a lot of SDK's that aren't uBlaze. RKArticle: 149915
In article <MfqdnSqFPqJ2KWvRnZ2dnUVZ_jmdnZ2d@giganews.com>, Jon Elson <jmelson@wustl.edu> wrote: >On 11/24/2010 05:58 PM, Thomas Womack wrote: > >> I think two lanes of PCI-E is a qualitatively better interface than >> the parallel port in EPP mode (4 gigabit per second each way); on the >> other hand you obviously don't need gigabit interface rates to go to >> servo motors, and the Atom+Altera chip will be using low-voltage IO >> and on aggressive lead-free BGAs so you still have the soldering >> issues and need the level translators. >Even one PCI-E lane would be way higher performance than the EPP >parallel port. But, that requires putting a board inside the PC, rather >than in the CNC machine, and also involves some IP from somebody. >I don't have tools to debug the PCI-E, so if it doesn't work, I'm pretty >well stuck. If the EPP parallel port has a problem, I hook up my logic >analyzer and see what is wrong. Also, some of these boards I make have >rows of solid state relays and wire terminal blocks, so they won't fit >in a PC. Now, there is a LOT to be said for making a PCI-E adaptor, and >maybe even using something like the EPP scheme, just using a much better >cable allowing the speed to be turned up. A twisted-pair ribbon cable >could probably handle handshaked byte transfers in 200 ns easily. The relevance of PCI-E is simply that the connection between the Atom and the Altera FPGA in the composite chip is by two lanes of PCI-E within the chip package (and, it appears, you have to use transceiver resources in the FPGA fabric to provide the PCI-E interface; not clear whether Intel provides you with that IP and what the licensing terms are); I presume that a lot of the I/O pins of the Altera chip are brought out to balls on the bottom of the package, and thinking that you'd connect those via level translators to the relays and thence the servos/stepper motors ... they're about four orders of magnitude faster than you need for stepper motors. But, yes, it seems as if your application realm is much more suited to something like a beagleboard, unless you actually want to run Solidworks on the motor-controller computer inside the machine tool. TomArticle: 149916
Thomas Entner <thomas.entner@entner-electronics.com> wrote: > The features of this editor sound great! (Althought rickman > persistently denies the usefulness of the refactoring-feature ;-) > Especially the integrated error-checking would be a big help (for some > reason, I have a feeled 20x more typos in the same amount of code when > writing VHDL compared to e.g. C). Maybe you would like verilog better. Before I learned verilog, I was told that C programmers usually liked verilog better than VHDL. I can usually read VHDL, but won't claim to be able to write it. I have even translated some VHDL routines to verilog. (Not trying to start a verilog vs. VHDL argument, just suggesting that you might like it.) -- glenArticle: 149917
I can't speak about QT and C++ bits as I still count myself as a hardware engineer but the hardware side is viable depending on exactly what you want to do. The size of the LX16 FPGA of the SP601 may limit you a bit on what you can do and it might be better to have a bigger FPGA like a LX45-LX150. Here we have been working on a new derivative of our Drigmorn4 Sparatn-6 board http://www.enterpoint.co.uk/drigmorn/drigmorn4.html that will support a touchscreen display as an option. We are also looking at doing an add-on camera that will support a lot of our product range including all our Spartan-6 boards Raggedstone2, Drigmorn3 and Drigmorn4. If you want a board that is ISE Webpack compatible we are already shipping LX75 versions of the Drigmorn4 to customers that have asked for it. That version doesn't appear in any of our website information. John Adair Enterpoint Ltd. On Dec 1, 5:07=A0pm, "Thales2" <eric.dube.3@n_o_s_p_a_m.gmail.com> wrote: > Hi, > > I an new to FPGA develepement and I want to build a litte embeded system > using the SP601 SPARTAN-6, to develepod my VHDL,c++ and PCB skill. But I > dont kwon if my projet is realitical, so I seek input from experience > developer here, before I buy the stuff. > > I am currently designing a dauterboard for the SP601 kit to the include t= he > folowing periferals : > > - tft LCDhttp://www.sparkfun.com/products/8335 > - 1 or more CMOS camera like this onehttp://www.sparkfun.com/products/866= 7 > - an audio codex (to be chosen) > - SD card reade > > As a first projet with this board. I would like to code in VHDL the LCD a= nd > camera controler and use the microblaze softcore to devepod in c++ a GUI > using the QT tools (http://qt.nokia.com/). So basically I want the user t= o > be able to take a shot using the GUI control and display it to the LCD. > > Latter I would like to implement function like music and video player and > maybe latter implement some cool computer vision processing using the > openCV library and dedicated FPGA hardware. > > 1) Do this look possible to you ? > 2) is the microblaze core able to handle the QT and OpenCV lib ? > 3) any suggestion to help me get that project started ? > > Thx for your inputs > > Eric > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 149918
"Thales2" <eric.dube.3@n_o_s_p_a_m.gmail.com> wrote in message news:HLCdnR2u8oF1HWvRnZ2dnUVZ_j2dnZ2d@giganews.com... > Hi, > > I an new to FPGA develepement and I want to build a litte embeded system > using the SP601 SPARTAN-6, to develepod my VHDL,c++ and PCB skill. But I > dont kwon if my projet is realitical, so I seek input from experience > developer here, before I buy the stuff. > > I am currently designing a dauterboard for the SP601 kit to the include > the > folowing periferals : > > - tft LCD http://www.sparkfun.com/products/8335 > - 1 or more CMOS camera like this one > http://www.sparkfun.com/products/8667 > - an audio codex (to be chosen) > - SD card reade > > As a first projet with this board. I would like to code in VHDL the LCD > and > camera controler and use the microblaze softcore to devepod in c++ a GUI > using the QT tools (http://qt.nokia.com/). So basically I want the user to > be able to take a shot using the GUI control and display it to the LCD. > > Latter I would like to implement function like music and video player and > maybe latter implement some cool computer vision processing using the > openCV library and dedicated FPGA hardware. > > 1) Do this look possible to you ? > 2) is the microblaze core able to handle the QT and OpenCV lib ? > 3) any suggestion to help me get that project started ? > > Thx for your inputs > > Eric > > > > > > > --------------------------------------- > Posted through http://www.FPGARelated.com As John said it's possible but it's much too ambitious for a first project to learn about FPGAs. You'll get bogged down with the softcore and the touch screen etc which won't teach you much about FPGA or VHDL. Start with a much less complex design and a really cheap dev kit (Lattice have some real cheapos !). If you haven't done the traffic lights or 7 seg LCD controller in VHDL then start with them. If you are past that stage and want a big FPGA challenge try the MP3 decoder in VHDL ! (There may be more suitable projects in between but you'll get the idea - pick something which is 90% VHDL on the FPGA if it's VHDL you want to learn.) Michael KellettArticle: 149919
rickman <gnuarm@gmail.com> writes: > On Dec 1, 8:29 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: >> rickman <gnu...@gmail.com> writes: >> > On Nov 30, 8:18 am, Martin Thompson <martin.j.thomp...@trw.com> wrote: >> >> >> This is better than a global (ie multi-file) replace because when you >> >> change "write" on one entity to "write_n" you don't want every entity >> >> with a "write" pin changing! And heaven help you changing rd to wr - >> >> hope the characters 'rd' don't appear in any other pins anywhere else >> >> (like the "one_third" pin of your "divide_by_three" entity ;) >> >> > That's not a big deal. My editor, and I suspect many others, has a >> > check box on the search that says "only full word match" so that >> > write_n won't match a write search. >> >> No, my point was if you have "write" on another entity you don;t want >> that one changing as well. > > Yes, if "only full word match" is used, then "write_n" won't match a > "write" search and replace so only "write" will change. Here's a concrete example (to try and make the point I keep failing to say clearly in a single sentence, sorry about that!): I have a FIFO with a write pin on it, and a memory with a write pin on it. If I decide to change the FIFO to have an active low write, then I rename the pin write_n. I've instantiated the FIFO and the memory a dozen times each in my large project. If I do a global replace of "write" with "write_n" in the entire project, all the references on the memory block will also change. If I do an interactive global replace, I have to be really careful to get it all right. Now, admittedly it's likely the compiler will catch it, but I'll waste time sorting it all out. Sigasi just does it all for me. <snip> >> > I'm not inclined to spend a kilobuck on something that will give me >> > a minor improvement in what I do maybe 10% of the time. Then on top >> > of it all, a tool that requires support from a company is already a >> > rung lower on the ladder >> >> Sorry, which ladder are you talking about? > > Sorry, the evaluation of the tool ladder. I don't know how this tool > is licensed, but I am very down on commercial tools because of the > licensing issues and the seeming lack of support. That automatically > puts a commercial tool below any open source tool when I am evaluating > them. So the commercial tool has to be significantly better for me to > want it. > There's another aspect of the licensing which I forgot to mention - it's based around Eclipse, which is an open-source IDE which supports Java and C well out of the box (dunno about Forth :) - as a replacement for CW on it's own Eclipse isn't bad (and if you end up using Xilinx or Altera soft processors, their IDE is also Eclipse-based). So the investment in Eclipse might be worth it irrespective of Sigasi... [I still haven't quite made up my mind whether to switch from Emacs to Eclipse for C-coding. It doesn't have a Usenet reader like Gnus though, so I'll have to keep Emacs around for a bit yet!] >> >> > Is this the way it works in Sigasi with signal names? If you are >> > typing a signal name as the first thing on a line, does it add the >> > assignment operator? What happens the first time you type an >> > assignment to a signal or variable? Does it add a declaration for the >> > name? >> >> IIRC you start typing the first few chars and hit ctrl-space, and it >> gives you a drop-down of potential completions. > > And those completions include both keywords as well as your signal/ > variable names? I think so yes (it's been a while since my eval) > If this feature works well enough I might consider > Sigasi. Especially if it could be used for other languages than just > VHDL. Is the VHDL aspect hard coded? I expect it will also support > Verilog, but what about generic languages? Does it have a means of > setting it up for an arbitrary language like CW does? Raw Eclipse deals with other languages, not Verilog though. Completion works in C, for example, and the "go to declaration" type things. > > >> >> Some Other things it does (full list is athttp://www.sigasi.com/featurelist): >> >> * Autocomplete templates for "if", "process", and the rest. >> > Nice, but not a big deal, for me anyway. >> >> Ahh, I'd thought you'd said automating boilerplate code was on your >> list - sorry. > > It is, but I guess I'm saying this is not a big enough feature to move > to a new tool for. I may have some down time in the new year. Maybe > I'll give the Sigasi tool a try. You are starting to convince me. > But learning curves are a PITA and if I have to pay for the tool, the > curve has to be short and the reward has to be big! > It's another little thing that adds up :) > >> >> * Line alignment (so all your : and <= and => line up nicely) >> > That would be nice. >> >> Much more than "nice" to me - esp. if others see your code - nothing >> like bad formatting to make people wonder whether the logic is >> similarly wiggly! > > Line indentation is a bigger hassle for me. I can line up the <= > and : parts without too much trouble. But I have to admit if you > bring a number of these little features together it might be worth > something. I *can* line them up by hand, but I very rarely did in the old days, and my code looked a mess! Nowadays, I hit Ctrl-C, Ctrl-B fairly frequently to "beautify my buffer" (as Emacs terms it) as I code. > > >> > I'll be finished with my VHDL coding in another week or two and won't >> > want to spend time with a VHDL tool. I am going to look into a design >> > using a multiprocessor chip that is micro power or nano power or pico >> > power, what ever it is being called these days. Idle state is 100 >> > micro watts per processor with 144 processors on the chip. Running >> > full out they use 4.5 mW at over 500 MIPS! >> >> Sounds fun - that sounds like a greenarray? > > Give the man a cupie doll! Erm, thanks :) > In the Spring they will have a 144 processor part with five ADC and > DAC and have released a data sheet for the GA4 (4 processors) with > no device release date. But Chuck's blog indicates they have had > prototype GA4 and GA32 devices for some time. On the other hand, > Chuck's blog seems to show a company that is on the low end of > struggling. I have no idea if they will manage to stay solvent long > enough to ship product. > Yes, it looks very interesting. > I am considering designing a Radio Controlled Clock using a GA4 which > would run off of two AAA cells for over a year. That should be a good > demo of the low power capabilities, no? Would that make you believe > that the chip can be pretty low power? The interesting part is that > this can be done with the GA144 nearly as easily as the GA4, you just > pay more to have 143 processors sitting idle 100% of the time and 1 > processor idle 95% of the time. > Or you could split the job up and have all 144 of them sitting idle for 99.9% of the time :) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149920
Thomas Entner <thomas.entner@entner-electronics.com> writes: > The features of this editor sound great! (Althought rickman > persistently denies the usefulness of the refactoring-feature ;-) > Especially the integrated error-checking would be a big help (for some > reason, I have a feeled 20x more typos in the same amount of code when > writing VHDL compared to e.g. C). Likely because there's 20x as many characters to type in VHDL :) <ducks> Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149921
rickman <gnuarm@gmail.com> writes: > There is a definite strike against it. I had planned to spend some > time this year learning Verilog at least well enough to figure out if > I wanted to make it my primary HDL. It seems very limiting to use a > tool that works great for only one language. > Eclipse verilog plugin - no idea how good it is! http://sourceforge.net/projects/veditor/ Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 149922
On 01/12/2010 19:36, rickman wrote: > On Dec 1, 12:20 pm, Jan Decaluwe<j...@jandecaluwe.com> wrote: >> rickman wrote: >> >>> Yes, if "only full word match" is used, then "write_n" won't match a >>> "write" search and replace so only "write" will change. >> >> It seems that you do not appreciate the difference between Rename >> and global search and replace yet. >> >> The same identifier may refer to a lot of different objects in >> a design. Rename is based on object identify, not identifier identity. >> This makes it intelligent and safe. > > Oh? How does that work. When can you use the same name for different > objects??? Why would you if you can? > I think the key to understanding here is that "search and replace" is a purely textual function, while "rename" is a type of "refactoring". I have no experience with this in VHDL, but I have used it a bit with C programming (again using Eclipse). The point here is that Eclipse and the plugin (CDT for C or C++, Sigasi for VHDL) analyses the syntax of the code - it effectively has the front-end of a compiler for the language in question. It is not just a matter of syntax highlighting based on regular expressions, as used by most editors. It knows the difference between an entity called "write", a signal called "write" and a function called "write" - because, like a VHDL compiler, it knows the difference between these concepts. Assuming Sigasi has similar functions to CDT, this will also allow fast cross-linking of information between files. With CDT, you can hold your mouse over an identifier and a tooltip will show you a short definition of the identifier. You can navigate quickly to the definition of the identifier, or to other uses of it. Whether or not you find this sort of thing useful is up to you. Personally, I am using Eclipse more and more for C programming, though I still like a simpler and faster text editor for many other tasks. There are other editors that can do a certain amount of refactoring, or support the use of "tag" information for cross-navigation by identifier, but I don't think anything else has the support Eclipse provides. That's why a company like Sigasi has built a plugin for Eclipse - Eclipse gives them a solid base for the refactoring, and they only need to worry about the VHDL-specific part. It's also why - like it or not - steadily more tool vendors are dropping their IDE's and editors and moving to an Eclipse + plugin model.Article: 149923
Hi all, I tried and read a lot on how to construct huffman tree from a given (Character,frequency) input and it is easy to do it on software but can't get the idea on Hardware and pls give me a hint. 1)on how to make sort (synthesizable) and construct huffman tree 2)How to read the codeword from the tree Thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149924
On Dec 1, 2:47=A0pm, colin <colin_toog...@yahoo.com> wrote: > > > Does anyone know approximately what the latency of using PCI is, to > > > send an interrupt and have the 1KB of data the OP is using transferre= d > > > into RAM? > > I'm a bit confused by this. Typically high bandwidth costs you a bit > of latency. I.E. if you need to get 1KB across an interface you live > with a relatively long setup time, after which the data moves very > quickly. If you want to read or write a single word there is little > setup (latency), and your access just completes. > > Colin Hi, I found a paper here: http://www.hypertransport.org/docs/wp/Latency_Comparison_HyperTransport_PCI= e_in_Communications_Systems.pdf That takes a look at latencies on PCIe (compared with HT). The numbers are on pages 9 & 10, and as a you say its "pretty quick". Rupert
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