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I agree with the advice to achieve the "very best performance," but only if that means "fastest clock speed". However, that is true for probably < 5% of most FPGA design work (not necessarily only 2% of FPGA resources). Sure, there are pieces of many FPGA designs where Fclk rules, but those pieces are usually small (especially in terms of how difficult it is to describe) compared to the rest of it. My point is, don't start worrying about what will fit in a LUT until you have to worry about Fclk. For the other 98% of your project that doesn't care, best performance = "easiest implementation to read, write, verify and maintain". For many organizations, "verify" also means review/audit by peers, so approaches to design are preferred that are simple not only for you to understand, but also your potential reviewers/auditors. Luckily, approaches that are easy for them to understand are also likely to be easily understood by potential maintainers, which might even be yourself in another few weeks/months/years. Hint: describe the behavior you want, not the implementation you think you want, at least until the tool tells you it can't come up with an implementation on its own that meets timing and available resources.Article: 150026
Considering that you may want to use a module as a submodule, parent modules will need to be able to find your submodule's generated macros (black-boxes) for their build (sim/synt/par). If you start copying files within a submodule you will not succeed cleaning it (from a parent modules view), or you need to clean the copies as well. Which one should the parent use? The original, or the copy? I found that, as long as I know where the submodule's generated items are stored, I could, for simulation, use a configuration to override paths using generics [vhdl]. For par (ngdbuild) use -sd to point out the macro. Synthesis treats it as a blackbox but I guess timing to/from the blackbox could/should be possible? In the cleaning process I excluded removing any macros (since they are quite time consuming to regenerate), however the build process still requires the macro-control-file (e.g. .xco) to be older than the macro-result-file (e.g. .mif, .ngc etc.). -- PontusArticle: 150027
d_s_klein <d_s_klein@yahoo.com> wrote: >On Dec 6, 9:18=A0am, Tim Wescott <t...@seemywebsite.com> wrote: >> >> Could you please cite chapter and verse? >> -- >> >> Tim Wescott >> Wescott Design Serviceshttp://www.wescottdesign.com >> > >According to gnu.org: "Many people believe that the spirit of the GNU >Project is that you should not charge money for distributing copies of >software, or that you should charge as little as possible =97 just >enough to cover the cost. This is a misunderstanding." > ><http://www.gnu.org/philosophy/selling.html> The free market principle says that people will get something from the cheapest source. In this case: they download from internet. Tim Wescott's post is spot on! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150028
On Dec 6, 12:50=A0pm, rickman <gnu...@gmail.com> wrote: > On Dec 6, 1:00=A0pm, Andy <jonesa...@comcast.net> wrote: > > > I think I would use a function for the intermediate calculation, and > > then call the function in both concurrent assignment statements per > > the original implementation. > > > Integers give you the benefits of bounds checking in simulation (even > > below the 2^n granularity if desired), and a big improvement in > > simulation performance, especially if integers are widely used in the > > design (instead of vectors). > > > Andy > > I know everyone says that integers run faster, but is this a > significant effect? =A0Has it been measured or at least verified on > current simulators? > > Rick A few years back, I had a design for a small FPGA with several modules on a common bus. I started out with unsigned(4 downto 0) for the address, and each module decoded its own address (each was given a generic for address and size). Then I changed only that address to a natural with equivalent range. Just that one change sped up my RTL simulation from over 2.5 hours down to less than 1 hour. I considered it very significant... AndyArticle: 150029
On Dec 6, 12:06=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote: > On Dec 6, 3:13=A0am, Mike Harrison <m...@whitewing.co.uk> wrote: > > >http://www.youtube.com/watch?v=3Dh_USk-HNgPA&feature=3Dplayer_detailpage > > > Come on X and A - spice up your promo =A0videos! > > Everybody chooses what is important to them. =A0Some like snazzy videos, > some like to ship product to customers... Well, then Lattice is doing both. Their policy on new part announcement is to wait until they have at least _some_ silicon available. Xilinx is already announcing Virtex 8 while not shipping V7.Article: 150030
On 12/06/2010 01:43 PM, d_s_klein wrote: > On Dec 6, 9:18 am, Tim Wescott<t...@seemywebsite.com> wrote: >> >> Could you please cite chapter and verse? >> -- >> >> Tim Wescott >> Wescott Design Serviceshttp://www.wescottdesign.com >> > > According to gnu.org: "Many people believe that the spirit of the GNU > Project is that you should not charge money for distributing copies of > software, or that you should charge as little as possible — just > enough to cover the cost. This is a misunderstanding." > > <http://www.gnu.org/philosophy/selling.html> I think you're correct in the details, but still off in the main point. You can sell me some GPL-ed software, but you can't keep me from turning around and posting it on my website for free. So, sooner or later, if there's much interest in the stuff at all, it'll turn up for free. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150031
On 12/6/2010 2:39 PM, Nico Coesel wrote: > d_s_klein<d_s_klein@yahoo.com> wrote: > >> On Dec 6, 9:18=A0am, Tim Wescott<t...@seemywebsite.com> wrote: >>> >>> Could you please cite chapter and verse? >>> -- >>> >>> Tim Wescott >>> Wescott Design Serviceshttp://www.wescottdesign.com >>> >> >> According to gnu.org: "Many people believe that the spirit of the GNU >> Project is that you should not charge money for distributing copies of >> software, or that you should charge as little as possible =97 just >> enough to cover the cost. This is a misunderstanding." >> >> <http://www.gnu.org/philosophy/selling.html> > > The free market principle says that people will get something from the > cheapest source. In this case: they download from internet. Tim > Wescott's post is spot on! > This assumes your time is free. Timesys, Montavista, Wind River, and many others seem to stay entirely in business by convincing folks that their time is worth more than the cost for their Linux ports/BSPs, etc. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 150032
On Dec 6, 4:00=A0pm, "sebas" <tanarnelinistit@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.com> wrote: > Thanks for the response. I know I can use Wishbone for interconnecting so= me > slave devices to a microprocessor but the idea is that I want to get away > without using a microprocessor. So the question is can another device, > other than microprocessor, be master on a Wishbone bus? Or on any other > bus... How can I get away without using a microprocessor? From your > experience designing a FSM is much more time consuming than using a simpl= e > microprocessor core (in this case I have to spend time 1) learning to > program it and 2) writing the code)? Of course you can do it any way you want. How you configure the peripherals depends on what the peripherals are expecting. Are they designed to be configured over wishbone? Or are they designed to be configured with direct connections? It should be a simple matter to design a state machine to control your data movements to and from each peripheral. I have no idea how you want this to work, so I can't make any specific suggestions. I suspect it could easily be done like a DMA controller. RickArticle: 150033
On Dec 6, 3:52=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > rickman <gnu...@gmail.com> wrote: > > (snip) > > > The Mealy vs Moore doesn't have to do with registering the outputs. > > That is just an issue of delays since registering the inputs and/or > > the outputs delays the outputs. =A0The real difference is that the > > outputs become a sort of separate state machine on their own although > > the output values don't feed back to affect either the machine state > > or the output state. =A0But the outputs are an independent function of > > the inputs and the outputs. =A0The outputs can change value with input > > changes without the state changing. =A0The outputs can have a different > > value for the same state depending on how you reached that state. > > I used to design FSMs considering the issues of Mealy vs Moore, but > > now I just design FSMs based on what I need and don't even bother with > > the M v. M distinction. =A0The bottom line is there are many variations > > on the theme, so why bother with just these two? > > Many years ago, I was using some system with a state machine compiler. > After doing a design (I believe as part of a tutorial session) I > figured out that my design was somewhere between Mealy and Moore. > > Also, I once found a bug in the Altera state machine optimizer, > by designing one in a way that the tools didn't expect. =A0It seems > that the tools wanted a separate verilog case block for state > selection and output generation. =A0I believe that is independent > of the Mealy vs. Moore question, but they are much easier for me > to read with state selection and output selection together. I agree. I think most FSMs are done so that the outputs are assigned in the same conditionals that assign the states. Although technically this makes it a Mealy machine with the outputs defined on the state transitions, you could also consider it a Moore machine as long as there is a mapping between the states and outputs which is independent of the inputs. I guess that is more of what is meant by Mealy and Moore structures rather than the implementation. But like I said, I seldom use any of the FSM theory I learned in school. Once you get used to designing them you just make them work without any theoretical thought about it. :-) RickArticle: 150034
On Dec 6, 5:20=A0pm, Andy <jonesa...@comcast.net> wrote: > I really do not recommend combined clocked processes with > combinatorial paths from in to out. They tend to have many of the > disadvantages of both clocked and combinatorial processes. > > What's the difference between adding a flag (v_delay) and adding > another state? None in reality, except that the flag is to be used as an output and not just a state variable. The Mealy and Moore machines are inter- convertible with a direct mapping between them. There is no problem that one can solve that the other can't. You can always turn a Mealy machine into a Moore machine by adding states and vice versa. > In general, if I'm using an FSM to control the timing of something, I > don't want to also use flags set by the FSM. Unless it makes the problem easier to visualize and understand. If the problem is to generate an output that is asserted on the transition of leaving a given state and it can go to a dozen different states, to make a Moore machine you would need to add an extra dozen transition states and set the output in each of them rather than just setting the output on leaving the enabling state. RickArticle: 150035
On 06/12/2010 14:54, rickman wrote: > On Dec 6, 3:24 am, David Brown<da...@westcontrol.removethisbit.com> > wrote: >> On 03/12/2010 18:02, Rob Gaddi wrote: >> >> >> >>> On 12/3/2010 12:45 AM, David Brown wrote: >>>> Hi, >> >>>> I haven't a lot of experience with FPGA design, but have done a few >>>> projects - mostly with Altera Cyclones, some with a Nios II. We are >>>> looking at making a new design that should be low cost, but needs a high >>>> speed serial interface (for reading in a DVI and/or HDMI signal). >> >>>> The obvious choice then is Lattice ECP3 (but I am very happy to hear >>>> alternative suggestions). >> >>>> I've already had a look at quite a bit of the website, so I'll looking >>>> mainly for information that is not there - a website will seldom tell >>>> you that their software feels slow and awkward, or fast and intuitive. >>>> And a website will often tell you things are free or "low cost", but the >>>> small print and hidden costs are, well, small and hidden. >> >>>> I haven't used any Lattice tools for nearly ten years, and that was for >>>> CPLD design. My guess is that things have changed a little since then. >> >>>> Are there anything major problems or obstacles that should make me >>>> reconsider before getting in too deep? I'd like to avoid doing the >>>> design and then finding out that Lattice only sells in 10,000 >>>> quantities, or that the tools are useless without buying many >>>> kilodollars of third-party software. >> >>>> For the development software, I can only name a few features of Quartus >>>> and ask if Lattice software is similar. I like the integration of >>>> Quartus - it feels like a single coordinated tool. Is that also the case >>>> with modern Lattice software? The tools I used long ago felt more like a >>>> collection of different bits and pieces, such as two separate synthesis >>>> engines that couldn't agree on anything. >> >>>> I also like Quartus SOPC builder - we might be putting a micro and a >>>> DDR2 memory interface in this design, and SOPC builder is definitely a >>>> convenient way to set put this together. Does Lattice have something >>>> similar? Obviously it will be geared towards the Micro32 rather than the >>>> Nios, but that's fine by me. >> >>>> How are the free tools compared to the paid-for tools? I'm okay with >>>> paying for the tools if that's necessary, but it is very nice having >>>> free versions that will do a good job. Amongst other things, it makes it >>>> more convenient to work from different computers (such as at a home >>>> office). >> >>>> Finally, there is the question of ready-made IP. The main parts I'd be >>>> interested in here are a DDR2 memory interface, an embedded micro, and >>>> possibly a DVI/HDMI receiver. I gather the micro32 is ready to use, free >>>> (and open), and has a full gcc toolchain, so that should be a simple >>>> choice (and the micro8 is a smaller alternative). It may be that I'll >>>> have to make all or part of the DVI/HDMI receiver, though it would be >>>> nice to get ready-made if it's not /too/ expensive. But the DDR2 >>>> interface is definitely something we should get ready-made. >> >>>> Thanks for any hints, pointers or opinions. >> >>>> mvh., >> >>>> David >> >>> No experience with the Lattice parts, and only just switching to A from >>> X recently. But, if you're currently happy with the Altera tools, I seem >>> to recall the Arria II chips being price competitive with ECP3. Also, >>> have you looked at the Cyclone IV GX chips? They've got high speed >>> serial too, although I think availability may be an issue. >> >> The Arria II are probably price-competitive with the ECP3 when you get >> above a certain size, but the ECP3 series starts lower. We don't need a >> great deal out of the FPGA other than the video interface, an embedded >> micro (and even that is optional) and fast external memory. The Cyclone >> IV GX are a definite possibility - unfortunately the currently-available >> EP4CGX15 is too small (though the price is nice), while the EP4CGX110 is >> far too big. The EP4CGX22 or 30 would be more appropriate, if they existed. >> >> I'm beginning to think that we'll drop the HDMI input. It would be nice >> to have an integrated solution, but it looks like it will be much more >> cost-effective to have an external HDMI receiver chip and just read in >> the data as a wide data bus. Then we can use a Cyclone III or Cyclone >> IV with the tools we have used before. > > That's an interesting trade off. Lattice came out with SERDES on > their low cost chips as a marketing move because neither X or A > offered SERDES on their low cost lines. Your preference may be to > stick with the higher cost approach of using an additional chip rather > than going with a new company and new tools. I can't say I blame you > really. I don't have that concern with any of X, A or L. I guess > I've used all three enough to be confident that I can make my design > work regardless. > I am now looking at a C3 or C4 with an external HDMI receiver, because it I think it would be cheaper than an ECP3 with an integrated HDMI/DVI receiver. An integrated solution would be more elegant, but the price difference between an ECP3 (with enough other resources) and a roughly equivalent C3 or C4 is greater than the cost of an HDMI receiver chip. The ECP3 may be "low cost" for an FPGA with high speed serial links, but that's only relative to a other FPGAs with high speed links. And then there's the development costs and possible IP licensing costs to consider - reading a 36-bit parallel RGB bus is easy compared to implementing a HDMI/DVI receiver block. In the end, however, it's up to the customer. I'm not sure an FPGA solution is going to be possible within the hoped-for budget. We are also looking at various system-on-a-chip devices to see if any of them can meet the requirements. Thanks for your information and advice, DavidArticle: 150036
On 06/12/2010 23:58, Tim Wescott wrote: > On 12/06/2010 01:43 PM, d_s_klein wrote: >> On Dec 6, 9:18 am, Tim Wescott<t...@seemywebsite.com> wrote: >>> >>> Could you please cite chapter and verse? >>> -- >>> >>> Tim Wescott >>> Wescott Design Serviceshttp://www.wescottdesign.com >>> >> >> According to gnu.org: "Many people believe that the spirit of the GNU >> Project is that you should not charge money for distributing copies of >> software, or that you should charge as little as possible — just >> enough to cover the cost. This is a misunderstanding." >> >> <http://www.gnu.org/philosophy/selling.html> > > I think you're correct in the details, but still off in the main point. > You can sell me some GPL-ed software, but you can't keep me from turning > around and posting it on my website for free. So, sooner or later, if > there's much interest in the stuff at all, it'll turn up for free. > It is perfectly legal to charge for GPL'ed software (though you can only charge someone a reasonable handling fee for the source code once you have sold/given them a binary). And once you have the software, you can then give it away to anyone you want. That much is all true. But there may be additional issues in hand, such as trademarks. For example, (almost) all of Red Hat Enterprise Linux is GPL'ed. You can buy RHEL, and you can distribute the packages for free (or you can download the packages for free from Red Hat). But you can't re-distribute the entire system without infringing on Red Hat's trademarks. Thus CentOS (and Oracle, and Scientific Linux) take RHEL, remove all Red Hat's trademarks, perhaps make a few other minor changes, and distribute the code. Most GPL'ed software that is popular is already given out for free - any charges are typically for additional non-GPL software, documentation, support services, etc. More specialised software, such as Wind River's Linux packages, may well only be available for a fee. Once you've paid the fee and got the binary and source code, you can then publish it for free on your website. But would you do that, with software you've paid good money for? And would anyone download it for you, rather than getting up-to-date and supported packages from the original site? There are many people that make money from providing or selling GPL software, and they do it by providing it as professional-level software including documentation and support. It is almost invariably zero-price software that has poor documentation - after all, few people /like/ writing documentation, so they'll only do it if they get paid to do it.Article: 150037
On 12/6/2010 10:00 PM, sebas wrote: > Thanks for the response. I know I can use Wishbone for > interconnecting some slave devices to a microprocessor but the idea > is that I want to get away without using a microprocessor. So the > question is can another device, other than microprocessor, be master > on a Wishbone bus? Or on any other bus... How can I get away without > using a microprocessor? From your experience designing a FSM is much > more time consuming than using a simple microprocessor core (in this > case I have to spend time 1) learning to program it and 2) writing > the code)? > Just to give you an example, I had to develop an fpga which was able to control several heterogeneous devices (tdc with a jtag interface, adc, charge amplifier, temperature sensor...). On top of it the fpga was a slave on a custom serial link responsible for slow-control and real-time data acquisition. Everything was controlled through an FSM which handled error situations and priority, but since I didn't have any idea of the existence of SoC bus like the Wishbone, I spent half of the time designing the interconnection bus. In my case the data from each device was pretty well defined and with very little programmable needs (except for the jtag), so an fsm did the job pretty easily. What I would recommend is to check what is the type of data you are getting through your interfaces and then decide what kind of control you may need (a microprocessor/microcontroller or an fsm). The Wishbone bus is pretty simple and you may find "wishbone compliant" cores for all the interfaces you mentioned on opencores.org. Good luck, Al >>> Hi, >>> >>> I have a design in which I use multiple cores for connecting to > different >>> interfaces: SPI, I2C, UART, etc. Each interface outputs the data >>> to >> memory. >>> I want to be able to both transmit data from the interface >>> cores, read >> data >>> from them and configure them (baud rate for example for UART). >>> How can I >> do >>> this? Can I use the Wishbone bus and build a master core to >>> drive the operations, the interface cores being the slaves? Is it >>> much easier if don't use the Wishbone and just build my own >>> interconnections bus? Basically my question is how do large >>> design connect cores, do they all >> use >>> a microprocessor? Looks like it by what I see on Xilinx' >>> website, for example. >>> >>> Thanks >> >> What you need is a bus to connect your modules to memory. Usually >> the devices you mention would be slaves on the bus and you would >> have a processor as a master to read the data and send it to >> memory. There are a number of standard buses like PLB from IBM and >> AMBA from ARM. Xilinx have used PLB in the past but are now using >> buses from ARM. I havent used Wishbone but I dont see why you could >> not. You could design your own > simple >> bus using some mux and control signals. It all depends how complex >> you > need >> it. >> >> Regards >> >> Jon --------------------------------------- Posted through >> http://www.FPGARelated.com > --------------------------------------- Posted through > http://www.FPGARelated.comArticle: 150038
On Dec 6, 10:58=A0pm, Tim Wescott <t...@seemywebsite.com> wrote: > On 12/06/2010 01:43 PM, d_s_klein wrote: > > > On Dec 6, 9:18 am, Tim Wescott<t...@seemywebsite.com> =A0wrote: > > >> Could you please cite chapter and verse? > >> -- > > >> Tim Wescott > >> Wescott Design Serviceshttp://www.wescottdesign.com > > > According to gnu.org: =A0"Many people believe that the spirit of the GN= U > > Project is that you should not charge money for distributing copies of > > software, or that you should charge as little as possible just > > enough to cover the cost. This is a misunderstanding." > > > <http://www.gnu.org/philosophy/selling.html> > > I think you're correct in the details, but still off in the main point. > =A0 You can sell me some GPL-ed software, but you can't keep me from > turning around and posting it on my website for free. =A0So, sooner or > later, if there's much interest in the stuff at all, it'll turn up for fr= ee. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Do you need to implement control loops in software? > "Applied Control Theory for Embedded Systems" was written for you. > See details athttp://www.wescottdesign.com/actfes/actfes.html Petalogix of PetaLinux fame is one company who specialize in Linux on Microblaze. The offer free downloads of their software, and have put a lot of work into getting microblaze supported (to the point that it is now in the kernel mainline, instead of the uclinux branch) AFAIK you can also pay for a premimum distribution, which comes bundled with a lot more custom-written (by them) scripts and utilities to make your life a lot easier in getting it running on YOUR board - like scripts that convert the EDK mhs/mss files into kernel configurations automatically, for example. So everything GPLed that they touch is freely available, and in the linux kernel mainline, but that doesn't mean you get everything they have built around it that that makes building the complete hw-to-sw system for free (unless you are a student, in which case you can get it, I think)Article: 150039
> >So, you could add a TXD_Delay state to replace the flag: > > if (reset='1') then > act_txd_state := TXD_IDLE; > elsif (clk'event and clk ='1') >then > > > case act_txd_state is > > > when TXD_IDLE => > if (txValid = '1') then > act_txd_state := TXD_ACTIVE; > end if; > > > when TXD_ACTIVE => > if (txReady = '1') then > act_txd_state := TXD_DELAY; > end if; > > when TXD_DELAY => > act_txd_state := TXD_END; > > when TXD_END => > if (txValid = '0') then > act_txd_state := >TXD_IDLE; > end if; > end case; > > > end if; > > > if (act_txd_state = TXD_ACTIVE) OR act_txd_state = >TXD_DELAY) then > if (dataIn = "00000000") then > tx_data <= "01000000"; > else > tx_data <= "11000000"; > end if; > elsif (act_txd_state = TXD_END) then > tx_data <= dataIn; > else > tx_data <= "00000000"; > end if; > > Yes....this a cleaner solution than a flag...the approach is similar...but adding one delay state it is definitely more clear...thanx for advice... > >Of course, this last example also would be simple to split into a >separate, clocked process for FSM, and a combinatorial process for the >data path (v_flag would have to be a signal.) Here is a concurrent >assignment statement that would do the trick: > >tx_data <= "01000000" when v_flag and data_in = "00000000" > else "11000000" when v_flag > else data_in; > >Hope this helps, > >Andy > Yes...better to use concurrent assignment/another combinatorial process...and much more better to avoid combinatorial input/output path inside main fsm...you are right...I didn't like it too...That was only an example for the discussion...I had to add signals in sensitivity list of the clocked process...very bad... I'm moving toward main fsm in one clocked process...registered output...and in case I need an output unregistered concurrent statements... Thanx a lot Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150040
On 12/6/2010 6:18 PM, Tim Wescott wrote: > On 12/06/2010 09:01 AM, d_s_klein wrote: >> On Dec 6, 7:00 am, "maxascent" >> <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: >>> I am looking to get started with Linux on a Microblaze. There seems >>> to be a >>> few companies out there doing it and Xilinx has a Wiki site. What >>> exactly >>> is the difference between the Xilinx and the others. Presumably you >>> have to >>> pay for the others, although I thought Linux was supposed to be free. >>> So I >>> would of thought I should be able to get hold of the source even if I >>> dont >>> get any support. >>> >>> Any thoughts would be helpful >>> >>> Thanks >>> >>> Jon >>> >>> --------------------------------------- >>> Posted throughhttp://www.FPGARelated.com >> >> You're not paying for The Kernel, you're paying for the effort of >> porting it. Most (all?) GPL flavors allow compensation for effort. > > Could you please cite chapter and verse? That's 180 degrees out from > what I read the last time I went over a GPL in its entirety. Per the > GPL, if you distribute the software in any way shape or form it has to > be free, and you have to distribute source code. > I don't quite understand why people tend to mix "free" and "free of charge". There is no place in the GPL where it is stated the software has to be free of charge. From http://www.gnu.org/licenses/gpl.html you can read: "Preamble The GNU General Public License is a free, copyleft license for software and other kinds of works. The licenses for most software and other practical works are designed to take away your freedom to share and change the works. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change all versions of a program--to make sure it remains free software for all its users. " GPL license is a copyleft type of license (viral license) that enforce the freedom under which the piece of software was created, freedom to change it and freedom to share it. This has nothing to do with money. > The way people make money on this stuff is by never documenting it well, > and offering consulting and/or training services. Or if it's a more > widely available product (like a desktop OS) they'll document it well > enough that an individual will like it, then offer consulting for the > corporate user. > Most of the success Linux has achieved is because it is not only very well documented, but also because anyone has the chance to improve the documentation (and implementation) making it a better system. Very well documented system doesn't mean anyone can install it on a blade server in a farm cluster and make it work out of the box. That is why most of the companies dealing with Linux sell services, not products. AlArticle: 150041
On Dec 6, 5:30=A0pm, rickman <gnu...@gmail.com> wrote: > On Dec 6, 5:20=A0pm, Andy <jonesa...@comcast.net> wrote: > > In general, if I'm using an FSM to control the timing of something, I > > don't want to also use flags set by the FSM. > > Unless it makes the problem easier to visualize and understand. =A0If > the problem is to generate an output that is asserted on the > transition of leaving a given state and it can go to a dozen different > states, to make a Moore machine you would need to add an extra dozen > transition states and set the output in each of them rather than just > setting the output on leaving the enabling state. > > Rick I think we are in agreement with what you said. But more than that, I'm trying (apparently not successfully!) to communicate something else. What Carlo's design was doing was using FSM states and a flag generated by the FSM to control the data path. My preference is to use either, but not both. In other words, either rework (add states if necessary) the FSM such that a separate flag is not needed (e.g. the datapath logic only needs to decode the FSM states), or rework the FSM and flag such that only the flag is needed, and the state need not be externally decoded to control the data path. Of the two, I have a significant preference for the latter, since it allows the FSM to be changed, but so long as it correctly generates the control flag(s), the data path logic need not change. This concept is sometimes called "decoupling", and is a very good SW engineering principle for application to HDL-based HW design. SW concepts like scope control, data hiding, separation of interface from impementation, etc. all allow decoupling of one part of the design from another. The bottom line is this: we want a design that is relatively immune to small changes in one part rippling unnecessarily to other parts. This is not to say that the other method is discouraged either (at least not completely). If the data path is such that its logic can be incorporated directly into the FSM (this case is not a good example of such), then I am all in favor of doing so, rather than simply generating control flags to communicate with an external process (or section of code outside the FSM case statement). Long story short: If the datapath can be reasonably controlled within the FSM, go ahead and do it there. If not, then have the FSM generate control flags that are used by separate datapath logic, without the datapath logic having to decode the FSM states. AndyArticle: 150042
>Thanks for the response. I know I can use Wishbone for interconnecting some >slave devices to a microprocessor but the idea is that I want to get away >without using a microprocessor. So the question is can another device, >other than microprocessor, be master on a Wishbone bus? Or on any other >bus... How can I get away without using a microprocessor? From your >experience designing a FSM is much more time consuming than using a simple >microprocessor core (in this case I have to spend time 1) learning to >program it and 2) writing the code)? > From personal experience, it is not terribly difficult to design an SPI or I2C slave without local microprocessor or similar, that (on the other edge) acts as a local bus master, writing or reading local bus memory-mapped locations. Wishbone is a good-enough choice of bus for this. You need to consider how you will handle access arbitration *when* 2 of them want the bus at "the same time". Delaying writes until the bus is free is quite easy. Handling the read access case may be a bit harder, especially for SPI, although for I2C you just hold off the clock until the data is ready. Before you ask, I no longer have access to the code... --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150043
>On Dec 6, 1:00=A0pm, Andy <jonesa...@comcast.net> wrote: >> I think I would use a function for the intermediate calculation, and >> then call the function in both concurrent assignment statements per >> the original implementation. >> >> Integers give you the benefits of bounds checking in simulation (even >> below the 2^n granularity if desired), and a big improvement in >> simulation performance, especially if integers are widely used in the >> design (instead of vectors). >> >> Andy > >I know everyone says that integers run faster, but is this a >significant effect? Has it been measured or at least verified on >current simulators? > >Rick > They certainly use less memory in simulation than wide vectors. An integer (32 bit) is 4 bytes. A std_logic_vector (9 states) is 3 bits per bit. If your data is >= 11 bits in width, integers are more efficient. Also, no need for resolution function calls, either. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150044
> The Cyclone IV GX are a definite possibility - unfortunately the currently-available EP4CGX15 is > too small (though the price is nice), while the EP4CGX110 is far too big. The EP4CGX22 or 30 > would be more appropriate, if they existed. David, push your local Altera distributor for availability. My tame (reliable) Alera FAE has told me they are imminent (engineering silicon available now I think). Nial.Article: 150045
On 12/07/2010 04:11 AM, David Brown wrote: > On 06/12/2010 23:58, Tim Wescott wrote: >> On 12/06/2010 01:43 PM, d_s_klein wrote: >>> On Dec 6, 9:18 am, Tim Wescott<t...@seemywebsite.com> wrote: >>>> >>>> Could you please cite chapter and verse? >>>> -- >>>> >>>> Tim Wescott >>>> Wescott Design Serviceshttp://www.wescottdesign.com >>>> >>> >>> According to gnu.org: "Many people believe that the spirit of the GNU >>> Project is that you should not charge money for distributing copies of >>> software, or that you should charge as little as possible — just >>> enough to cover the cost. This is a misunderstanding." >>> >>> <http://www.gnu.org/philosophy/selling.html> >> >> I think you're correct in the details, but still off in the main point. >> You can sell me some GPL-ed software, but you can't keep me from turning >> around and posting it on my website for free. So, sooner or later, if >> there's much interest in the stuff at all, it'll turn up for free. >> > > It is perfectly legal to charge for GPL'ed software (though you can only > charge someone a reasonable handling fee for the source code once you > have sold/given them a binary). And once you have the software, you can > then give it away to anyone you want. That much is all true. > > But there may be additional issues in hand, such as trademarks. For > example, (almost) all of Red Hat Enterprise Linux is GPL'ed. You can buy > RHEL, and you can distribute the packages for free (or you can download > the packages for free from Red Hat). But you can't re-distribute the > entire system without infringing on Red Hat's trademarks. Thus CentOS > (and Oracle, and Scientific Linux) take RHEL, remove all Red Hat's > trademarks, perhaps make a few other minor changes, and distribute the > code. > > Most GPL'ed software that is popular is already given out for free - any > charges are typically for additional non-GPL software, documentation, > support services, etc. More specialised software, such as Wind River's > Linux packages, may well only be available for a fee. Once you've paid > the fee and got the binary and source code, you can then publish it for > free on your website. But would you do that, with software you've paid > good money for? And would anyone download it for you, rather than > getting up-to-date and supported packages from the original site? > > There are many people that make money from providing or selling GPL > software, and they do it by providing it as professional-level software > including documentation and support. It is almost invariably zero-price > software that has poor documentation - after all, few people /like/ > writing documentation, so they'll only do it if they get paid to do it. Well, that was my point -- if you're going to make money off of GPL'd software, you're going to sell services, and give the software away for free. The "value for money" proposition isn't a bunch of software with elaborate copy protection -- the "value for money" proposition is that when one of the customer's people calls needing help, he gets it _right now_. If you're going to _pay_ money for GPL'd software, the obvious obverse applies. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 150046
Hi, On 6 d=E9c, 18:23, "rupertlssm...@googlemail.com" <rupertlssm...@googlemail.com> wrote: > I could not get windrv to work, I think no one does. > Does any body have any experience of getting the libusb-driver to work? I= 'm > following the instructions here: > > http://git.zerfleddert.de/cgi-bin/gitweb.cgi/usb-driver?a=3Dblob_plain;..= . You don't need this hack with the recent version of the Xilinx tools. They support libusb directly. BTW, alternatives are xc3sprog and urJTAG which recently got added FPGA programming support, so you might want to do away with the proprietary, bloated, slow and buggy Xilinx programming tools completely. S.Article: 150047
On 6 d=E9c, 23:56, Gabor <ga...@alacron.com> wrote: >=A0Xilinx is already announcing Virtex 8 Really? Could not find a trace of said announcement. > while not shipping V7. And neither cheap and large quantities of S6 (maybe until recently).Article: 150048
On 7 d=E9c, 18:13, Tim Wescott <t...@seemywebsite.com> wrote: > Well, that was my point -- if you're going to make money off of GPL'd > software, you're going to sell services, and give the software away for > free. Which has the perverse effect of giving an incentive for free software service companies to write obscure and poorly documented code, so they can stay in business. See for example what Codesourcery does.Article: 150049
Rob Gaddi <rgaddi@technologyhighland.com> wrote: >On 12/6/2010 2:39 PM, Nico Coesel wrote: >> d_s_klein<d_s_klein@yahoo.com> wrote: >> >>> On Dec 6, 9:18=A0am, Tim Wescott<t...@seemywebsite.com> wrote: >>>> >>>> Could you please cite chapter and verse? >>>> -- >>>> >>>> Tim Wescott >>>> Wescott Design Serviceshttp://www.wescottdesign.com >>>> >>> >>> According to gnu.org: "Many people believe that the spirit of the GNU >>> Project is that you should not charge money for distributing copies of >>> software, or that you should charge as little as possible =97 just >>> enough to cover the cost. This is a misunderstanding." >>> >>> <http://www.gnu.org/philosophy/selling.html> >> >> The free market principle says that people will get something from the >> cheapest source. In this case: they download from internet. Tim >> Wescott's post is spot on! >> > >This assumes your time is free. Timesys, Montavista, Wind River, and >many others seem to stay entirely in business by convincing folks that >their time is worth more than the cost for their Linux ports/BSPs, etc. You could turn that around: if you know your limitations then you hire an expert. I'm also in the business of getting Linux going on embedded platforms. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
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