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On Apr 15, 2:58=A0pm, Rick <richardcort...@gmail.com> wrote: > On Apr 15, 1:35=A0am, Rick <richardcort...@gmail.com> wrote: > > > Still lost in the woods. > > > I came across the Simili download so I searched the newsgroup. Hasn't > > been a post in the newsgroup for 3 years. Is there a fatal flaw of > > some kind with this software that would make it something to be > > avoided? I kind of like the fact it is only a 9 meg zip as opposed to > > installing fistfuls of Webpack gigs. > > > I'm not needing anything beyond being able to program/debug stuff in > > the 22V10 range. > > > Rick > > OK, looks like you need to add the manufacturers definitions which > would have meant downloading gigs of info. If I have it right the > program looks on your hard drive for most of the popular manufacturers > installs and compiles from there. > > I finally backed off to WinCUPL from Atmel. Still only 20 megs and > seems beginner enough for me to use. Managed to get my first try > compiled and trying to learn the simulator now. > > Rick Cypress Warp =3D> 22V10's in VHDL or Verilog. Support dropped by Cypress, but it's still available on the grey market. RK.Article: 151551
The IEEE P1149.1.1 working group (http://standards.ieee.org/develop/ project/1149.1.1.html) is looking at standardizing test data register (TDR) interfaces. The group is looking for participation by FPGA vendors, and in particular people who are working on or who may be interested in the implementation of test data registers (TDR) in FPGA=92s that are connected to an IEEE 1149.1 compliant TAP in such devices.Article: 151552
On Apr 18, 6:08=A0am, Thomas Entner <thomas.entne...@gmail.com> wrote: > On 18 Apr., 00:00, rickman <gnu...@gmail.com> wrote:>=A0I don't think the= re is ANY other soft CPU under > > several thousand LUTs that has a C compiler. > > Please do not forget my ERIC5: About 300 LUTs, about ATMEL AVR > performance, with C-compiler. > > Regards, > > Thomas > > www.entner-electronics.com I should have included "32 bit" processor. That was what they wanted. One 32 bit processor architecture, one instruction set and many possible speed ranges. That is not my goal. I prefer to provide more customized CPUs which are optimized for the application which almost always require more speed, at least in bursts. RickArticle: 151553
"colin" <colin_toogood@yahoo.com> wrote in message news:89a1ef5f-ddbd-4be2-84e8-ce5f12d1f013@b13g2000prf.googlegroups.com... >I used the term "protocol analyser" in its loosest sense. If you want >to look at video use a CRT if that is all you can afford but a video >protocol analyser will tell you what is wrong fundamentally quicker >than hooking up a scope. I also meant hyperlynx simulation rather than Im not so sure that would work better than a monitor. Maybe on some types of errors, but having a moving image shown will reveal much of the REAL problems. We can accept for example pixel blip in 1 of 10000 frames, but errors that only occur at certain pixelrates and on certain patterns (revealing SSO issues) is better just to view. An analyzer would need to know far too much and would be equivalent complex as a sim testbench to set up. >modelsim. You said you wanted to look at DDR3 and gigabit stuff. If >you spend less than $2K on a probe the act of looking at the signal >will mess it up. I've designed DDR2 96bit wide stuff and never probed I'm not as digital as you. I can live with seing the signal 50% correct. There is still a lot of information in the pulse, but you have to know you are using a probe with low spec when you interpret the result. (I also use the cheapest soldering iron you can find to do very complex soldering; you don't HAVE to use the most expensive) >it, you can't because the chips are on both sides of the board and the >routing is on internal layers. The lousiest design on the planet will >work at 25 centigrade so you don't need a scope. Your welcome to hook >a scope up in an oven and see why it doesn't work at 55 or -5. Instead Our current design has 4 dimms of 72bits and its working without ever being probed, but many times in the process, I would like to probe it to rule out some issues we had, mostly on ck and ctrl bus. As an example I can tell there was a left shift in a color and I wanted to probe if it happened during read or write. It appeared to be a timing issue as we have laid out the pcb with inverted clk pair, and couldn't get the IP to cooperate with that. It got solved without probing in the end. >make darn sure your at 50 ohms and you have simulated and have >chipscope report all the timing parameters that the mig is using. If >none of the timings are at an end of their scale you have a design you >can build a thousand of. No problem, it runs at 533Mhz with two Spartan3 E110's (and a E50) :) I'ts a huge board and it was laid out on Cadsoft's Eagle(!), and worked on first rev (well, the memory did. We screwed up a couple of connector pinouts, but we got it running with some adapters). >hmm, sorry that was a bit of a rant but I'm not going to reword it :) I like ranting ;) It's an efficient way of communicating if its two-way and as long as nobody takes it personal.Article: 151554
On Apr 18, 1:25=A0pm, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Hello: > > >So I have a separate modules foo (with signals: foo_a, foo_b, foo_c) > >and have another module foo1 (with signals: foo_x, foo_y, foo_z) which > >instantiates foo within its module. > > >Now when I run a test on foo1, on ModelSim, the signals I can see to > >add are the foo_x, foo_y and foo_z only. How do I get to add foo_a, > >foo_b and foo_c signals to the wave, so that I could see what's going > >on inside. I'm guessing this has to be with the paths, need help! > >Thanks! > > RTFM. > > add wave foo_instance_name/foo* > > Or select the signals from the navigator window that is probably in the t= op > left of the GUI display, by clicking [+] icons to expand the instantiated > modules. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Also if you are running simulation (vsim) and then adding the waves, ModelSim by default logs signals only in the top level. To see the waveforms in entirety, you will have to log them before running the simulation . My ideal sequence of operation would be #compile the source files and the testbench vcom <files to compile> #load the design vsim -t ps work.toplevel #log all the signals in the design. The /* mean anything under root / root here is the top level design log -r /* #now run the design for specific time or forever run 100ns #OR run -aArticle: 151555
>On Apr 18, 1:25=A0pm, "RCIngham" ><robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >> >Hello: >> >> >So I have a separate modules foo (with signals: foo_a, foo_b, foo_c) >> >and have another module foo1 (with signals: foo_x, foo_y, foo_z) which >> >instantiates foo within its module. >> >> >Now when I run a test on foo1, on ModelSim, the signals I can see to >> >add are the foo_x, foo_y and foo_z only. How do I get to add foo_a, >> >foo_b and foo_c signals to the wave, so that I could see what's going >> >on inside. I'm guessing this has to be with the paths, need help! >> >Thanks! >> >> RTFM. >> >> add wave foo_instance_name/foo* >> >> Or select the signals from the navigator window that is probably in the t= >op >> left of the GUI display, by clicking [+] icons to expand the instantiated >> modules. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >Also if you are running simulation (vsim) and then adding the waves, >ModelSim by default logs signals only in the top level. To see the >waveforms in entirety, you will have to log them before running the >simulation . My ideal sequence of operation would be > >#compile the source files and the testbench >vcom <files to compile> > >#load the design >vsim -t ps work.toplevel > >#log all the signals in the design. The /* mean anything under root / >root here is the top level design >log -r /* > >#now run the design for specific time or forever >run 100ns > >#OR >run -a > I usually do the 'add wave' commands before any 'run' commands. This has the advantages of slightly increasing simulation speed, and saving some disk space for the logging file. The disadvantage is that if you suddenly realise you need to look at a particular signal that you hadn't added, you have to start the simulation again. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151556
Hello, i'm returned, maybe with better knowledges in verilg... my design
file is synthetizable and implementable. My question is how it is possible
that a 8x8 multiplier occupy 60 SLICES, synthetized alone, and all the
entire system, with 3 bigger multiplier occupy only 13 SLICES??
if you would try to synthetize this file...maybe it is a big example for
how a iir filter does not work...
What is wrong?
Best regards...
//ALL SYSTEM IN VERILOG
module multiplier_10x10(
out_dato,
x_1,
x_2//,
//clk
);
output [21:0] out_dato;
wire [21:0] out_dato;
input [10:0] x_1;
// input clk;
input [10:0] x_2;
// always @ (posedge clk) begin
assign out_dato = x_1*x_2;
// end
endmodule
module divisor_clock_codec( clk,
reset_in,
cinquanta_M,
venticinque_M,
dodiciecinque_M,
trepuntocentoventicinque_M,
quarantokappa_M);
// gen various clock for codec
input clk;
input reset_in;
output cinquanta_M;
output venticinque_M;
output dodiciecinque_M;
output trepuntocentoventicinque_M;
output quarantokappa_M;
reg [10:0] counter;
always @(posedge clk)
begin: COUNT_PLUS_ONE
counter <= counter+1;
end
assign cinquanta_M = clk;
assign venticinque_M = counter[1];
assign dodiciecinque_M = counter[2];
assign trepuntocentoventicinque_M = counter[3];
assign quarantokappa_M = counter[10];
endmodule
module sum11bit(
out_dato,
x_1,
x_2
);
input [10:0] x_1;
input [10:0] x_2;
output [10:0] out_dato;
assign out_dato=x_1+x_2;
endmodule
module sum22bit(
out_dato,
x_1,
x_2
);
input [21:0] x_1;
input [21:0] x_2;
output [21:0] out_dato;
assign out_dato=x_1+x_2;
endmodule
module binario_to_compl2_c(
par_in,
par_out
);
parameter WIDTH=11;
input [WIDTH-1:0] par_in;
output [WIDTH-1:0] par_out;
assign par_out=(~par_in)+1'd1;
endmodule
module ser_to_par( // converter serial-parallel
clk,
ser_in,
par_out
);
input clk;
input ser_in;
output [10:0] par_out;
reg [10:0] par_out;
reg indice_count=7'b0;
always @ (posedge clk)
begin : PILA_VALORI
if(indice_count<8) begin
par_out[indice_count]=ser_in;
indice_count<=indice_count+1;
end
else indice_count=7'b0;
end
endmodule
module par_to_ser( // converter parallel-serial
clk,
par_in,
ser_out
);
input clk;
input [21:0] par_in;
output ser_out;
reg indice_contat=16'b0;
reg ser_out;
always @ (posedge clk)
begin: SPILA_VALORI
if(indice_contat<16) begin
ser_out=par_in[indice_contat];
indice_contat<=indice_contat+1;
end
else indice_contat=16'b0;
end
endmodule
module filt_iir_lowpass(//filter kernel
clk,
alpha,
sample_in,
sample_out
);
input [10:0] alpha;
input clk;
input [10:0] sample_in;
output [21:0]sample_out;
wire [21:0] y_2_molt;
wire [21:0] y_1_molt;
//wire [15:0] x_1_molt;
wire [21:0] x_molt;
wire[21:0] y_tot;
reg [10:0] y_1;
reg [10:0] y_2;
//reg [7:0] x_1;
//reg [7:0] x_2;
multiplier_10x10 MOL1 (y_2_molt,y_2,8'd3);//,clk);
multiplier_10x10 MOL2(y_1_molt,y_1,alpha);//,clk);
multiplier_10x10 MOL3(x_molt,sample_in,8'd2);//,clk);
sum11bit SOM_Y(y_tot,y_1_molt,y_2_molt);
sum22bit SOM_FIN(sample_out,y_tot,x_molt);
always @(posedge clk)
begin
y_2=y_1;
y_1=sample_out;
end
endmodule
module total_sys(alpha, //implementazione moduli in intero sistema
clk_pad_in,
push_reset,
sdto_from_adc,
lrclk_to_dac,
mclk_to_dac,
sclk_to_dac,
sdti_to_dac);
input [10:0] alpha;
input clk_pad_in;
input push_reset;
input sdto_from_adc;
output lrclk_to_dac;
output mclk_to_dac;
output sclk_to_dac;
output sdti_to_dac;
wire [10:0] alpha_cin_compl2;
wire clock_global_to_all;
wire [10:0] dal_ser_par_al_filter_kernel;
wire [21:0] sample_da_serializ;
binario_to_compl2_c bin_to_2compl (.par_in(alpha[10:0]),
.par_out(alpha_cin_compl2[10:0]));
divisor_clock_codec clock_divisore (.clk(clk_pad_in),
reset_in(push_reset),
.cinquanta_M(clock_global_to_all),
.dodiciecinque_M(mclk_to_dac),
.quarantokappa_M(lrclk_to_dac),
.trepuntocentoventicinque_M(sclk_to_dac),
.venticinque_M());
filt_iir_lowpass filter_kernel (.alpha(alpha_cin_compl2[10:0]),
.clk(clock_global_to_all),
.sample_in(dal_ser_par_al_filter_kernel[10:0]),
.sample_out(sample_da_serializ[21:0]));
par_to_ser par_to_ser_conv (.clk(clock_global_to_all),
.par_in(sample_da_serializ[21:0]),
.ser_out(sdti_to_dac));
ser_to_par ser_to_par_conv (.clk(clock_global_to_all),
.ser_in(sdto_from_adc),
.par_out(dal_ser_par_al_filter_kernel[10:0]));
endmodule
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 151557Sorry, that is a problem with the Avnet Web. Your login has timed out, but the web page isn't handling it correctly. You need to either logout manually, or restart your browser. Then try again. Bryan On Apr 18, 4:14=A0pm, NeedCleverHandle <d_s_kl...@yahoo.com> wrote: > On Apr 18, 7:21=A0am, Bryan <bryan.fletc...@avnet.com> wrote: > > > > >http://www.em.avnet.com/virtex4mini --> Support Files & Downloads > > > Bryan > > That link goes to: > > =A0 =A0 A generic error has occurred. > =A0 =A0 The store is currently experiencing problems. Try again later. > > Cheers, > RKArticle: 151558
On 4/19/2011 7:20 AM, francesco_pincio wrote: > Hello, i'm returned, maybe with better knowledges in verilg... my design > file is synthetizable and implementable. My question is how it is possible > that a 8x8 multiplier occupy 60 SLICES, synthetized alone, and all the > entire system, with 3 bigger multiplier occupy only 13 SLICES?? > if you would try to synthetize this file...maybe it is a big example for > how a iir filter does not work... > > What is wrong? You might be best off looking at the PaR report. It will indicate what logic is being removed based on unused outputs. How many multipliers utilized in the design using (from PaR summary)? What device is this target for, I assume a Xilinx device since you are using the SLICE terminology. Chris FeltonArticle: 151559
>You might be best off looking at the PaR report. It will indicate what >logic is being removed based on unused outputs. > >How many multipliers utilized in the design using (from PaR summary)? >What device is this target for, I assume a Xilinx device since you are >using the SLICE terminology. > >Chris Felton > Hello Sir, yes i'm using Xilinx Spartan 2 con 50k gates on tq144package (x2s50-5tq144) on a Xess XSA-50 board: I attach : 1) Advanced HDL Synthesis Report Macro Statistics # Multipliers : 3 11x11-bit multiplier : 3 # Adders/Subtractors : 3 11-bit adder : 2 22-bit adder : 1 # Counters : 1 11-bit up counter : 1 # Registers : 27 Flip-Flops : 27 2) FROM PAR report seems no multiplier are removed...i don't understand Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:534 - The following XORCY(s) is/are demoted to LUTs because there is no MUXCY associated with them. Therefore, we cannot recognize the standard carry chain structure: XORCY symbol "filter_kernel/MOL1/Mmult_out_dato_Madd_xor<1>" (output signal=filter_kernel/y_2_molt<1>), XORCY symbol "filter_kernel/MOL2/Mmult_out_dato_Madd9_xor<1>" (output signal=filter_kernel/y_1_molt<1>), XORCY symbol "filter_kernel/SOM_FIN/Madd_out_dato_xor<1>" (output signal=sample_da_serializ<1>) INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away 11 Block(s) redundant Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC Redundant Block(s): TYPE BLOCK LUT1 clock_divisore/Mcount_counter_cy<1>_rt LUT1 clock_divisore/Mcount_counter_cy<2>_rt LUT1 clock_divisore/Mcount_counter_cy<3>_rt LUT1 clock_divisore/Mcount_counter_cy<4>_rt LUT1 clock_divisore/Mcount_counter_cy<5>_rt LUT1 clock_divisore/Mcount_counter_cy<6>_rt LUT1 clock_divisore/Mcount_counter_cy<7>_rt LUT1 clock_divisore/Mcount_counter_cy<8>_rt LUT1 clock_divisore/Mcount_counter_cy<9>_rt LUT1 clock_divisore/Mcount_counter_xor<10>_rt INV ser_to_par_conv/indice_count_0_not00001_INV_0 --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151560
Hi, i need to use an package counter to check how many packages are inside a dual port FIFO. The counter should increment the counter at the posedge of one port and decrement with posedge of another port, and a third port would stay at log state high if there are full packages inside the FIFO. I think the idea would be the same of the implementation of the Async FIFO, but i could not understand how the process works reading the article "Simulation and Synthesis Techniques for Asynchronous FIFO Design". Any one could give me a simple explanation on how implement that counter on Verilog? Thank you!Article: 151561
On Apr 18, 7:34=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > You really need to learn how to write verilog code correctly first. > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I could manage to solve the problem, a guy from edaboard pointed me the problem, i gorgot to latch the state at the FSM. The code is dirt becouse i was crazy trying to debug it, but where should i look for good pactices on writing verilog code? Thank you!Article: 151562
> > You need to learn some of the nuances of Verilog. =A0I also don't > believe this > simulates properly. > > First, the case statement that begins > =A0 =A0 always@(state_machine or r_counter or tx_b_1_int or tx_b_2_int or > =A0 =A0 =A0 =A0 write_done or int_ack_done or DATA_READY) > =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 tx_b_1_over =3D 1'b0; > =A0 =A0 =A0 =A0 tx_b_2_over =3D 1'b0; > =A0 =A0 =A0 =A0 rx_b_1_over =3D 1'b0; > =A0 =A0 =A0 =A0 rx_b_2_over =3D 1'b0; > =A0 =A0 =A0 =A0 case (state_machine) > =A0 =A0 =A0 =A0 WB_IDLE : > =A0 =A0 =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 if(r_counter > 32'h00000000) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 begin > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 next_state =3D WB_READING; > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end > =A0 =A0 =A0 =A0 =A0 =A0 end > will infer latches. =A0This is usually bad. =A0Look in the synthesis > report (.syr) to see > if latches are being inferred. =A0 Why is this happening? What logic > does the above > fragment need if r_counter =3D=3D 0? > > Second, ask yourself, "how does the state machine ever get to > WB_WRITING? > > You need to completely review your code and think about what h/w it > will create. > > Good luck! > > John Providenza John the WRITING state was not implemented yet, thats why it was over there but never got activated, Sorry for the horrible code. Thank you!Article: 151563
Jacko, > Supporting C, that's good, but designed for C is more marketing speak. > Considering C was designed to work on processors, I'd expect a stack > frame link instruction similar to the 68k at least... with word stride > multiplication for pointer arithmetic... but fair dues, it's not too bad, but > suffers from hype. I don't agree that it is just marketing speak - the instructions were selected to encode C programs as compactly as possible while still having a tiny implementation. The CRISP (sold as the AT&T Hobbit) was a much better C processor, but an FPGA implementation of that would be several times larger than the ZPU. The VAX was also a really great target for C, but couldn't perform as well as RISCs (neither can the ZPU). -- JecelArticle: 151564
I can see how it could be so, but why go for 16 local variable indexes? The= following development from the Nibz basis: http://code.google.com/p/scc-on-gcc/wiki/FBWT and the idea of an unroll n instructions instruction to extend the subrouti= ne factor cover to similar beginning but uncommon endings, should go real w= ell on OoO execution machines with speculative. The net reduction in MB/s t= raffic per MIPS, could more than offset the reduction because of threading = subroutines. The X7 is not my shiny shiny but my pet dog. And my dog's better than your = dog :) C compiler for Nibz... it might happen, but that was never the ultimate aim= . Cheers Jacko p.s. and if OS561 ever gets made, I will have failed in my purpose of not b= eing bound by backward compatibility limits, stopping future development.Article: 151565
On Apr 19, 10:42=A0pm, jacko <jackokr...@gmail.com> wrote: > I can see how it could be so, but why go for 16 local variable indexes? T= he following development from the Nibz basis: > > http://code.google.com/p/scc-on-gcc/wiki/FBWT > > and the idea of an unroll n instructions instruction to extend the subrou= tine factor cover to similar beginning but uncommon endings, should go real= well on OoO execution machines with speculative. The net reduction in MB/s= traffic per MIPS, could more than offset the reduction because of threadin= g subroutines. > > The X7 is not my shiny shiny but my pet dog. And my dog's better than you= r dog :) > > C compiler for Nibz... it might happen, but that was never the ultimate a= im. > > Cheers Jacko > > p.s. and if OS561 ever gets made, I will have failed in my purpose of not= being bound by backward compatibility limits, stopping future development. I don't know why you are comparing the ZPU to your processor in terms of performance and size. The ZPU is a 32 bit processor, yours is 16 no? RickArticle: 151566
Hi all, I've downloaded from the site in object a model of a usb3300 chip (usb2.0 otg transceiver) because I wanted to simulate the behaviour....I'm trying to develop an ulpi wrapper and have a behavioural model of the transceiver should save me a lot of time.... Unfortunately it seems not working at all...or I'm not compiling and simulating it in the right way. I use modelsim 6.5 se...I compiled using vhdl-93 and with vital2000 support...at least it should be.... Anyway...I'm forced to compile one file at time otherwise I get strange compilation errors and, when I start a simulation, I get a sigsegv on VitalPathDelay01Z...mmh I don't know where to start from....I'm considering to give up... :-( Any help will be very appreciated... If somebody want to try to use the package and verify.. it can be downloaded from http://www.freemodelfoundry.com/fmf_models/proc/usb3300_20081015.tar.gz a testebench is provided inside...it should be only compiled and simulated but for me became a black hole... Thanks in advance Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151567
>Hi, i need to use an package counter to check how many packages are >inside a dual port FIFO. The counter should increment the counter at >the posedge of one port and decrement with posedge of another port, >and a third port would stay at log state high if there are full >packages inside the FIFO. I think the idea would be the same of the >implementation of the Async FIFO, but i could not understand how the >process works reading the article "Simulation and Synthesis Techniques >for Asynchronous FIFO Design". Any one could give me a simple >explanation on how implement that counter on Verilog? > >Thank you! > The counter has to be in one clock domain or the other. I will assume that it will be in the first clock domain. Use the posedge of the first port to generate a 'count-up' strobe. Use the posedge of the second port, via a clock-domain-crossing pulse synchronizer, to generate a 'count_down' strobe. I don't quite understand what the third port is doing. Is it a "count not zero" indicator? The up/down counter should now be easy to code, using only one clock. The design of pulse synchronizer can be found in another of Cliff Cummings' excellent papers on the Sunburst website. I design in VHDL, so cannnot help you with Verilog codes. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151568
set the generic wide to 16, and it becomes 32 bit..Article: 151569
Nobody never used fmf models....please any help.... Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151570
On 20/04/11 09:45, jacko wrote: > set the generic wide to 16, and it becomes 32 bit.. Is your processor design as good as your ability to post linked messages?Article: 151571
Not for me to judge.Article: 151572
On Apr 20, 5:33=A0am, "RCIngham" <robert.ingham@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >Hi, i need to use an package counter to check how many packages are > >inside a dual port FIFO. The counter should increment the counter at > >the posedge of one port and decrement with posedge of another port, > >and a third port would stay at log state high if there are full > >packages inside the FIFO. I think the idea would be the same of the > >implementation of the Async FIFO, but i could not understand how the > >process works reading the article "Simulation and Synthesis Techniques > >for Asynchronous FIFO Design". Any one could give me a simple > >explanation on how implement that counter on Verilog? > > >Thank you! > > The counter has to be in one clock domain or the other. I will assume tha= t > it will be in the first clock domain. > > Use the posedge of the first port to generate a 'count-up' strobe. > Use the posedge of the second port, via a clock-domain-crossing pulse > synchronizer, to generate a 'count_down' strobe. > I don't quite understand what the third port is doing. Is it a "count not > zero" indicator? > The up/down counter should now be easy to code, using only one clock. > > The design of pulse synchronizer can be found in another of Cliff Cumming= s' > excellent papers on the Sunburst website. > > I design in VHDL, so cannnot help you with Verilog codes. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I dont know if it is possible, but the idea is to not have a clock domain. It is a counter with 3 ports. 2 inputs and one output. at every pulse at input 1 the counter goes up, at every pulse at the input 2 the counter goes down. If the counter is on 0 the output is 0, if the counter value is bigger than 0 the output is 1. But the pulses will be assinc generated. I will have a fifo, and i got to control how many full messages packages are inside, but the packages len is variable, so there is a module that parse the message at the input to pulse when a full message is inside and another to parse the output to check when a full message came out, to generae a pulse to the counter. Is that possible? Thank you!Article: 151573
On Apr 20, 4:45=A0am, jacko <jackokr...@gmail.com> wrote: > set the generic wide to 16, and it becomes 32 bit.. And it doubles in size and slows down as well, yes? RickArticle: 151574
Not doubles as the video and DAC and SPI hardware are all limited in size, but yes it gets bigger and slower. The memory data bus becomes 16 bit though. Cheers Jacko
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