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On Apr 20, 6:03=A0am, "carlob" <carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote: > Nobody never used fmf models....please any help.... > > Carlo =A0 =A0 =A0 If you want specific help, you should ask more specific questions. Simply saying things like 'I get strange compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of no help to anyone except the limited audience that may have used that specific part. What you describe though seems like something more general which if you were to list what error messages you actually get would be of more help. Most people do not want to do all your work for you. Somewhat coincidentally, I can say that I have compiled that particular model without any problems and have at least started a sim with a testbench that instantiates that model...whether or not it correctly models the part I can't say other than the clock output does work. Kevin JenningsArticle: 151576
Thank you for the reply....no..I don't want that someone do work in my place...I'm doing this in my spare time....but I'm not able to do it...probably because I don't understand the error... Anyway I know that is terribly difficul to help someone without having had exactly the same problem...that's why I searched for someone that used the component...thank you for your help... You told me that you were able to compile correctly...I can tell you steps that I have followed to accomplish a compilation and you can check if I'm right..ok?? I create a new library called fmf with the fmf library files (only two are needed conversions.vhd and gen_utils.vhd). I compile with -93 version of compiler...no problems here... Then I map this library for compiling all files in src directory (test_pkg.vhd test_code.vhd test_bfm.vhd usb3300.vhd testbench_usb3300_vhdl.vhd in this order always with -93). At first I receive errors because it claims that test_code.vhd and test_bfm.vhd cannot see package work.test_pkg... It is strange in my opinion...it is the first file I compiled, but I notice that, under library work, test_pkg is the only library actually compiled... From here (with test_pkg already compiled) start a new compilation...now everything is ok...all is compiled well...no error... Ii is correct??? In your opinion I'm doing something wrong?? That's first time I saw a thing like that... Another way that I found effective to accomplish a right compilation here is to compile each file individually..... Anyway everything is compiled now...but I'm not sure if I'm doing something wrong... Problems start when I try to simulate..... I had different problems on different tries...(if I remember well because I don't have modelsim here).... Yesterday night I first compiled the sdf with sdfcom then I tried to launch a simulation with -sdftyp /dut=path_to_compiled_sdf without luck... Modelsim complains that: Failed to find INSTANCE dut (that is present in testbench and in sdf with tag INSTANCE...file usb3300_vhdl.sdf line 15)...after that SIGSEGV....I checked also the modelsim user guide...for me I'm doing ok...but doesn't work...if you look at testbench_usb3300_vhdl.vhd and usb3300_vhdl.sdf you can confirm that dut is the instance to which sdf refers and it is the name of instance of component usb3300 in testbench... If I compile checking to ignore sdf warnings and to translate errors in warnings I can start the simulation (obviuosly) but when I run it I receive a SIGSEGV...on line 2042 of usb3300.vhd....VitalPathDelay01Z... I think that the error is mainly in parsing the sdf file....generics for vital are not recognized well and crash...but I'm not so expert in timing simulation.... I don't know if I'm doing well...probably you can tell me If you did the same or not.... Maybe...there could be also an issue with my installation of modelsim...even if I tried to simulate with other old project and everyting seems working fine... Tonight I will try again and I will be more precise... Thank you Carlo >On Apr 20, 6:03=A0am, "carlob" ><carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote: >> Nobody never used fmf models....please any help.... >> >> Carlo =A0 =A0 =A0 > >If you want specific help, you should ask more specific questions. >Simply saying things like 'I get strange >compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of >no help to anyone except the limited audience that may have used that >specific part. What you describe though seems like something more >general which if you were to list what error messages you actually get >would be of more help. Most people do not want to do all your work >for you. > >Somewhat coincidentally, I can say that I have compiled that >particular model without any problems and have at least started a sim >with a testbench that instantiates that model...whether or not it >correctly models the part I can't say other than the clock output does >work. > >Kevin Jennings > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151577
> >I dont know if it is possible, but the idea is to not have a clock >domain. FPGAs are intended for the implementation of synchronous logic, with a limited number of different clock domains. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151578
On 4/20/2011 10:55 AM, Jan Coombs wrote: > On 20/04/11 09:45, jacko wrote: >> set the generic wide to 16, and it becomes 32 bit.. > > Is your processor design as good as your ability to post linked messages? > > In other newsgroups the issue was attributed to the latest Google Groups interface. Some solved the issue by returning to the old interface.Article: 151579
Well, seems to be working now, but I know what you mean. For example, the c= urrent compile idea is taking small C the 8080 compiler, and adapting it to= compile under gcc (some reserved word collisions and some lack of forward = definitions, but leaving pointer and int casting warnings). Just need to co= mplete the code generation section, get it outputting 8080 assembly, and th= en get it to output Nibz code with some macros for common operations. Minim= ize the macro set, and then insert a code size optimizer. http://scc-on-gcc.googlecode.com Sometimes old, although not best is simpler to get working. Cheers JackoArticle: 151580
Hi all,
to be more precise:
create a new library work:
vlib work
vmap work work
Compile gen_utils.vhd and conversions.vhd (fmf library):
vcom -reportprogress 300 -work work {C:/usb3300/src/fmf/gen_utils.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/fmf/conversions.vhd}
in modelsim.ini I have set VHDL93 = 93
No problem till here....
Now start with usb3300:
change drectory to usb3300/src
create a new library work:
vlib work
vmap work work
map the previous library as fmf:
vmap fmf {C:/usb3300/src/fmf/work}
Compile files in src (in modelsim.ini I have set VHDL93 = 93):
vcom -reportprogress 300 -work work {C:/usb3300/src/test_pkg.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/test_code.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/test_bfm.vhd}
vcom -reportprogress 300 -work work {C:/usb3300/src/usb3300.vhd}
vcom -reportprogress 300 -work work
{C:/usb3300/src/testbench_usb3300_vhdl.vhd}
Till now...everything is fine....
Then I compiled usb3300_vhdl.sdf with sdfcom
sdfcom -typdelays usb3300_vhdl.sdf com_usb3300_vhdl.sdf
obtaining com_usb3300_vhdl.sdf
Start simulation:
vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
ERRORS:
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE
'dut'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving
instances from compiled SDF file(s).
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/d_out_pathdelay_gen__0/line__2042
File: C://usb3300/src/usb3300.vhd
# FATAL ERROR while loading design
Then I Tried:
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# Loading timing data from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/d_out_pathdelay_gen__0/line__2042
File: C:/usb3300/src/usb3300.vhd
# FATAL ERROR while loading design
As you can see now the instance is resolved but modelsim SIGSEGV again. The
same result if I use the sdf not previously compiled...
At the end I tried again by compiling after disabling all possible checks
and optimizations in modelsim.ini:
Explicit = 0 NoDebug = 0 CheckSynthesis = 0 NoVitalCheck = 1 Optimize_1164
= 0
NoVital = 1 Quiet = 0 Show_source = 0 DisableOpt = 0
Everything is fine....now the simulation...
Failed to find INSTANCE 'dut'as before..changing instance to / seems
ok...layout change to simulate
# vsim -sdftyp {/=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps -novopt
work.testbench_usb3300_vhdl
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading instances from C:/Documents and
Settings/Carlo/Desktop/USB/EVB3300/usb3300/src/com_usb3300_vhdl.sdf
# Loading timing data from C:/Documents and
Settings/Carlo/Desktop/USB/EVB3300/usb3300/src/com_usb3300_vhdl.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /testbench_usb3300_vhdl File:
C:/usb3300/src/testbench_usb3300_vhdl.vhd
but after run
run
# ** Note: -------------------------------------------------------------
# Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl
# ** Note: -------------POSITIVE, POWER UP------------------------------
# Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl
# ** Fatal: (SIGSEGV) Bad handle or reference.
# Time: 0 ps Iteration: 0 Process:
/testbench_usb3300_vhdl/dut/behavior/nxt_out_pathdelay File:
C:/usb3300/src/usb3300.vhd
# Fatal error in Process nxt_out_pathdelay at C:/usb3300/src/usb3300.vhd
line 2091
#
# HDL call sequence:
# Stopped at C:/usb3300/src/usb3300.vhd 2091 Process nxt_out_pathdelay
I'm still thinking that I'm using the sdf file in an uncorrect way...anyway
I don't find the right way...
I know t post is very long...I'm sorry....
Hope kevin or someone else can help me
Thank you very much
Carlo
>On Apr 20, 6:03=A0am, "carlob"
><carlo.beccia@n_o_s_p_a_m.n_o_s_p_a_m.libero.it> wrote:
>> Nobody never used fmf models....please any help....
>>
>> Carlo =A0 =A0 =A0
>
>If you want specific help, you should ask more specific questions.
>Simply saying things like 'I get strange
>compilation errors' or 'I get a sigsegv on VitalPathDelay01Z' are of
>no help to anyone except the limited audience that may have used that
>specific part. What you describe though seems like something more
>general which if you were to list what error messages you actually get
>would be of more help. Most people do not want to do all your work
>for you.
>
>Somewhat coincidentally, I can say that I have compiled that
>particular model without any problems and have at least started a sim
>with a testbench that instantiates that model...whether or not it
>correctly models the part I can't say other than the clock output does
>work.
>
>Kevin Jennings
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 151581
On Thu, 21 Apr 2011 16:08:06 -0500, "carlob" wrote:
>Start simulation:
>vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
> work.testbench_usb3300_vhdl
It seems very unlikely that the full hierarchical path
to the module is "/dut". Load the simulation without the SDF
option at all, and look in the GUI to see what ModelSim thinks
is the name of the DUT instance. It's probably something like
/testbench_usb3300_vhdl/dut (that appears in one of the error
messages). Put that into your -sdftyp option in place of /dut
and things will probably go better.
--
Jonathan Bromley
Article: 151582
Hi jonathan......thank you very much...(If I remember well I've read in the
user manual that is not ever needed to specify the top entity)...anyway
that's the result of a try....
vsim -sdftyp
{/testbench_usb3300_vhdl/dut=C:/usb330/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
# vsim -sdftyp
{/testbench_usb3300_vhdl/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
work.testbench_usb3300_vhdl
# Loading std.standard
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# ** INTERNAL ERROR: pkgref: export lookup failed.
# Loading ieee.std_logic_1164(body)
# Loading std.textio(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading fmf.gen_utils(body)
# Loading fmf.conversions(body)
# Loading work.test_pkg(body)
# Loading work.test_code(body)
# Loading work.ulpi_pkg(body)
# Loading work.usb_pkg(body)
# Loading work.testbench_usb3300_vhdl(vhdl_behavioral)
# Loading work.usb3300(vhdl_behavioral)
# Loading work.test_bfm(test_bfm_hdl)
# Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf
# ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE
'dut'.
# ** Error: (vsim-SDF-3894) : Errors occured in reading and resolving
instances from compiled SDF file(s).
# Error loading design
The only way to let it start is to specify -sdftyp /=sdf file name...but
then the simualtion SIGSEGV...and it is not correct...the right parameter
should be, as you suggest, /testbench_usb3300_vhdl/dut....
It seems impossible that for kevin the model worked without problems....
..any hint is welcome...
It's late now here..I'm going to sleep...if I will have more options I will
try again tomorrow night...
Thank you again
Carlo
>On Thu, 21 Apr 2011 16:08:06 -0500, "carlob" wrote:
>
>>Start simulation:
>>vsim -sdftyp {/dut=C:/usb3300/src/com_usb3300_vhdl.sdf} -t ps
>> work.testbench_usb3300_vhdl
>
>It seems very unlikely that the full hierarchical path
>to the module is "/dut". Load the simulation without the SDF
>option at all, and look in the GUI to see what ModelSim thinks
>is the name of the DUT instance. It's probably something like
>/testbench_usb3300_vhdl/dut (that appears in one of the error
>messages). Put that into your -sdftyp option in place of /dut
>and things will probably go better.
>--
>Jonathan Bromley
>
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 151583I just took delivery of an ML605, and tried out the demo to make sure the board was OK. The pre-built demo is supposed to allow you to load images, and view them on the DVI or VGA output, while optionally filtering the images. Both printed documents that ship with the system (Hardware and Demo Setup Guide, and Getting Started) say that the monitor should display a Xilinx splash screen initially. It doesn't. I've tried both the VGA out and DVI out, and gone over settings carefully (there are a couple of minor inconsistencies in the documentation, but I've tried a few variations.) I never got any video. Any suggestions? Do I just have a bad board, or am I overlooking something obvious? Thanks PeteArticle: 151584
On 21/04/11 14:45, Christopher Felton wrote: > On 4/20/2011 10:55 AM, Jan Coombs wrote: >> On 20/04/11 09:45, jacko wrote: >>> set the generic wide to 16, and it becomes 32 bit.. >> >> Is your processor design as good as your ability to post linked >> messages? >> >> > > In other newsgroups the issue was attributed to the latest Google > Groups interface. Some solved the issue by returning to the old > interface. Yes, I should have remembered that. But, the posts are also difficult to understand because of being very terse, and quoting no context, for example, this orphaned one posted to c.l.f, about 5 hours ago: : f1 ... DUP ; : f2 ... f1 ... ; : f3 ... DROP f1 ... ; Which leads to the idea of a NOP permutation generator.Article: 151585
On Apr 22, 7:30=A0am, Pete Fraser <pfra...@covad.net> wrote: > I just took delivery of an ML605, and tried out > the demo to make sure the board was OK. > The pre-built demo is supposed to allow you to > load images, and view them on the DVI or VGA > output, while optionally filtering the images. > > Both printed documents that ship with the system > (Hardware and Demo Setup Guide, and Getting Started) > say that the monitor should display a Xilinx splash > screen initially. It doesn't. I've tried both the > VGA out and DVI out, and gone over settings > carefully (there are a couple of minor > inconsistencies in the documentation, but I've > tried a few variations.) I never got any video. > > Any suggestions? Do I just have a bad board, > or am I overlooking something obvious? > > Thanks > > Pete Having just an overview of the problem, if I have to debug, I would see if there is an RTL given with the demo example. If so, you will find the display controller in the RTL. The display controller would basically have a data bus going into the display which is driven with data read out from the NAND flash or SPI Flash on the board with the documents that you talked about or the Xilinx Splash screen). I suggest disconnecting that data bus and tying it to RGB0,0,0 and RGB255,255,255 and check if you see white screen and the black screen which mean the display interfaces would be fine and only the data being read out may be an issue. If the display controller itself is an issue, then it might be the issue with the VGA DVI driver chips or the digital display controller in the RTL.Article: 151586
>"carlob" wrote in message >news:F-adnR6vhetVMi3QnZ2dnUVZ_h2dnZ2d@giganews.com... ># Loading std.standard ># ** INTERNAL ERROR: pkgref: export lookup failed. This looks like a Modelsim bug. I ran the design on DE 10.0a and it seems OKish. ># Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf ># ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE >'dut'. I get the same error, looks like the SDF file is not correct or not compatible with Modelsim. >The only way to let it start is to specify -sdftyp /=sdf file name...but >then the simualtion SIGSEGV...and it is not correct...the right parameter >should be, as you suggest, /testbench_usb3300_vhdl/dut.... >It seems impossible that for kevin the model worked without problems.... As Jonathan suggested try running it without the sdf file, you should get something like: run 10 ms # ** Note: ------------------------------------------------------------- # Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl # ** Note: -------------POSITIVE, POWER UP------------------------------ # Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl # ** Note: RECEIVED RX CMD = d"40" # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: -------------POWER UP DONE----------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: -------------TEST 1------------------------------------------ # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Note: POSITIVE, after power up, Link resets PHY by setting the reset bit in the Function control register. # Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl # ** Warning: *usb3300 HOLD High VIOLATION ON DIn(...) WITH RESPECT TO CLKOUT; # Expected := 1 ns; Observed := 0 ns; At : 3500274.33 ns # Time: 3500274330 ps Iteration: 3 Region: /testbench_usb3300_vhdl/DUT/Behavior # ** Warning: *usb3300: simulation may be inaccurate due to timing violations # Time: 3500274330 ps Iteration: 3 Region: /testbench_usb3300_vhdl/DUT/Behavior # ** Note: -------------END OF TEST 1----------------------------------- .. # ** Note: -------------END OF TEST 15----------------------------------- # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl # ** Note: ------------------------------------------------------------- # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl # ** Note: Test ended without errors # Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl I would try to contact the creator ( nporobic@hdldh.com?) and see if he can help you out. I am sure he would appreciate the feedback, Good luck, Hans www.ht-lab.com >..any hint is welcome... > >It's late now here..I'm going to sleep...if I will have more options I will >try again tomorrow night... > >Thank you again >Carlo >Article: 151587
Am 22.04.2011 04:30, schrieb Pete Fraser: > > Both printed documents that ship with the system > (Hardware and Demo Setup Guide, and Getting Started) > say that the monitor should display a Xilinx splash > screen initially. It doesn't. I've tried both the > VGA out and DVI out, and gone over settings > carefully (there are a couple of minor > inconsistencies in the documentation, but I've > tried a few variations.) I never got any video. > > Any suggestions? Do I just have a bad board, > or am I overlooking something obvious? I had something similar with a SP605 demo board. (only green & purple stripes on the screen) It turned out that the content of the flash card was broken. Really the flash was ok, but the embedded software could only deal with _one_ file in a certain directory or sth. like that. Erasing the flash & reprogramming it with the version from the USB stick made it work. Such a thing MUST NOT HAPPEN on a demo system regards, Gerhard who still doesn't have the USB download working under Linux :-(Article: 151588
Hi Hans, yes..I will try that too....at the moment I tried to contatct Richard Munden: munden@freemodelfoundry.com the author of the book: ASIC and FPGA Verification: A Guide to Component Modeling (Systems on Silicon)...he seems to be very involved in free model foundry...but without any luck...no answer... Maybe I want to try to reinstall modelsim...the error on pgref sounds bad to me and I've read on internet that someone with this kind of problems solved with a full reinstallation...otherwise is very strange.... Thank you anyway for reply.... > >I would try to contact the creator ( n�porobic@hdl�dh.com?) and see if he >can help you out. I am sure he would appreciate the feedback, > >Good luck, >Hans >www.ht-lab.com > > >>..any hint is welcome... >> >>It's late now here..I'm going to sleep...if I will have more options I will >>try again tomorrow night... >> >>Thank you again >>Carlo >> > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151589
Hi Hans, thank you again...I'm sorry but I haven't read the first part of the answer....ok I will try without the sdf...I don't remenber well but probably I've already tried with the same result as before.... A good modelsim reinstall is needed....I'm ever more convinced that is a tool problem.... Thank you again Carlo > >>"carlob" wrote in message >>news:F-adnR6vhetVMi3QnZ2dnUVZ_h2dnZ2d@giganews.com... >># Loading std.standard >># ** INTERNAL ERROR: pkgref: export lookup failed. > >This looks like a Modelsim bug. I ran the design on DE 10.0a and it seems >OKish. > >># Loading instances from C:/usb3300/src/com_usb3300_vhdl.sdf >># ** Error: (vsim-SDF-3250) usb3300_vhdl.sdf(17): Failed to find INSTANCE >>'dut'. > >I get the same error, looks like the SDF file is not correct or not >compatible with Modelsim. > >>The only way to let it start is to specify -sdftyp /=sdf file name...but >>then the simualtion SIGSEGV...and it is not correct...the right parameter >>should be, as you suggest, /testbench_usb3300_vhdl/dut.... >>It seems impossible that for kevin the model worked without problems.... > >As Jonathan suggested try running it without the sdf file, you should get >something like: > >run 10 ms ># ** Note: ------------------------------------------------------------- ># Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl ># ** Note: -------------POSITIVE, POWER UP------------------------------ ># Time: 0 ps Iteration: 0 Instance: /testbench_usb3300_vhdl ># ** Note: RECEIVED RX CMD = d"40" ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: -------------POWER UP DONE----------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: ------------------------------------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: ------------------------------------------------------------- ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: -------------TEST 1------------------------------------------ ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Note: POSITIVE, after power up, Link resets PHY by setting the reset >bit in the Function control register. ># Time: 3500091070 ps Iteration: 3 Instance: /testbench_usb3300_vhdl ># ** Warning: *usb3300 HOLD High VIOLATION ON DIn(...) WITH RESPECT TO >CLKOUT; ># Expected := 1 ns; Observed := 0 ns; At : 3500274.33 ns ># Time: 3500274330 ps Iteration: 3 Region: >/testbench_usb3300_vhdl/DUT/Behavior ># ** Warning: *usb3300: simulation may be inaccurate due to timing >violations ># Time: 3500274330 ps Iteration: 3 Region: >/testbench_usb3300_vhdl/DUT/Behavior ># ** Note: -------------END OF TEST 1----------------------------------- >.. ># ** Note: -------------END OF TEST 15----------------------------------- ># Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl ># ** Note: ------------------------------------------------------------- ># Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl ># ** Note: Test ended without errors ># Time: 17256729708 ps Iteration: 2 Instance: /testbench_usb3300_vhdl > >I would try to contact the creator ( n�porobic@hdl�dh.com?) and see if he >can help you out. I am sure he would appreciate the feedback, > >Good luck, >Hans >www.ht-lab.com > > >>..any hint is welcome... >> >>It's late now here..I'm going to sleep...if I will have more options I will >>try again tomorrow night... >> >>Thank you again >>Carlo >> > > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151590
shyam wrote: > On Apr 22, 7:30 am, Pete Fraser<pfra...@covad.net> wrote: >> I just took delivery of an ML605, and tried out >> the demo to make sure the board was OK. >> [...] >> Any suggestions? Do I just have a bad board, >> or am I overlooking something obvious? > > Having just an overview of the problem, if I have to debug, I would > see if there is an RTL given with the demo example. If so, you will > find the display controller in the RTL. I might have to do that, but my intent was just to do a quick functional check using the supplied demo. I just wanted to see that the board was working before I threw out the packing. I don't want to spend too long debugging if the board is dead. PeteArticle: 151591
On Apr 22, 5:51=A0am, Pete Fraser <pfra...@covad.net> wrote: > shyam wrote: > > On Apr 22, 7:30 am, Pete Fraser<pfra...@covad.net> =A0wrote: > >> I just took delivery of an ML605, and tried out > >> the demo to make sure the board was OK. > >> [...] > >> Any suggestions? Do I just have a bad board, > >> or am I overlooking something obvious? > > > Having just an overview of the problem, if I have to debug, I would > > see if there is an RTL given with the demo example. If so, you will > > find the display controller in the RTL. > > I might have to do that, but my intent was just to do > a quick functional check using the supplied demo. > I just wanted to see that the board was working > before I threw out the packing. I don't want to > spend too long debugging if the board is dead. > > Pete This page: <http://www.xilinx.com/products/boards/ml605/ reference_designs_12.4_archive.htm> has the instructions and data for re-imaging the CF module (they call it the Compact Flash Flash). I would start with that.Article: 151592
>On Apr 16, 7:38=A0am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.lirmm.fr> >wrote: >> Hello, >> >> I am dealing with some issues with timing >> delays.I would like to know how to implement >> timing constraints for combinatorial nets >> in a simple way. >> >> For example: >> an AND gate with two inputs: A and B >> and I want to force XST to guarantee that >> the signal A arrives before B. I precise that >> the AND gate is one element of a combinatorial >> path (A and B are not PADs). >> >> Any ideas? >> >> Thanks for your help. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >A synthesizer (XST in your case) cannot guarantee any timing it can >only provide estimates. The only way to determine if the timing is >identical would be after the entire path has been placed and routed. > >And then due to process variation with any IC the delays will never be >identical. > >Ed McGettigan >-- >Xilinx Inc. > Thanks for your answer. I was hoping there was a clever way to do that... like the hold violations which are managed by the synthesizer with extra buffers. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151593
Hi all, SOLVED!!!!!! I've simply uninstalled modelsim an reinstalled....now everything seems to work at least without using the sdf..... This is a really strange behaviour...but, as I understand from internet, I'm not the only one that experimented it.... I want to thank everyone who helped me and I hope that this indication would be useful for some others... Thank you again Carlo --------------------------------------- Posted through http://www.FPGARelated.comArticle: 151594
NeedCleverHandle wrote: > > This page:<http://www.xilinx.com/products/boards/ml605/ > reference_designs_12.4_archive.htm> has the instructions and data for > re-imaging the CF module (they call it the Compact Flash Flash). > > I would start with that. That was the problem. Thanks. When I looked at the CF card, the demo there was something called "CDMA Benchmark Graphing". It seems to run a small web server, and graphs something when I point my browser at the (hardcoded) ip address of the board. The demo seems to work OK, but is not designed to output anything from the board's video spigots. It's a mystery to my why Xilinx ships nicely printed color "getting started" guides with detailed instructions on running the supplied demo, then quietly substitute a _very_ different demo. PeteArticle: 151595
On Apr 23, 6:01=A0am, Pete Fraser <pfra...@covad.net> wrote: > NeedCleverHandle wrote: > > > This page:<http://www.xilinx.com/products/boards/ml605/ > > reference_designs_12.4_archive.htm> =A0has the instructions and data fo= r > > re-imaging the CF module (they call it the Compact Flash Flash). > > > I would start with that. > > That was the problem. Thanks. > > When I looked at the CF card, the demo there was > something called "CDMA Benchmark Graphing". > > It seems to run a small web server, and graphs > something when I point my browser at the > (hardcoded) ip address of the board. > > The demo seems to work OK, but is not designed > to output anything from the board's video spigots. > > It's a mystery to my why Xilinx ships nicely > printed color "getting started" guides with > detailed instructions on running the supplied demo, > then quietly substitute a _very_ different demo. > > Pete Going through comp.arch.fpga gets oneself a lot of information. Now I know Xilinx has thing thing of quietly substituting a different demo :-)Article: 151596
On Apr 23, 12:09=A0am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.n_o_s_p_a_m.lirmm.fr> wrote: > >On Apr 16, 7:38=3DA0am, "lyo34" <lyonel.barthe@n_o_s_p_a_m.lirmm.fr> > >wrote: > >> Hello, > > >> I am dealing with some issues with timing > >> delays.I would like to know how to implement > >> timing constraints for combinatorial nets > >> in a simple way. > > >> For example: > >> an AND gate with two inputs: A and B > >> and I want to force XST to guarantee that > >> the signal A arrives before B. I precise that > >> the AND gate is one element of a combinatorial > >> path (A and B are not PADs). > > >> Any ideas? > > >> Thanks for your help. > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >A synthesizer (XST in your case) cannot guarantee any timing it can > >only provide estimates. =A0The only way to determine if the timing is > >identical would be after the entire path has been placed and routed. > > >And then due to process variation with any IC the delays will never be > >identical. > > >Ed McGettigan > >-- > >Xilinx Inc. > > Thanks for your answer. > > I was hoping there was a clever way > to do that... like the hold violations > which are managed by the synthesizer > with extra buffers. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I am not sure if Xilinx fixed hold violations but vaguely remember it might have shown me hold violations. I am not really sure. But there should be a way to get the delay between flops where you know that the path is failing on hold. Ideally Xilinx flops should not fail on hold since the clock skew is much smaller. May be places where local routing for clocks are used and if the skew is more, these violations might happen. Either way the Xilinx Timing analyzer puts up a lot of information as far as timing is concerned and things can be fixed. Personally, I don't think Xilinx FPGAs fail on hold for internal flip flops. The pads story might be different. Thanks ShyamArticle: 151597
I often see people, especially hobbyists looking for inexpensive boards with a lot of non-dedicated I/O. These new boards from Lattice are pretty basic (no on-board RAM) but have a lot of break-out pins for projects that just need a lot of I/O on 0.1" centers for prototyping. Usually Lattice releases boards like this at a "kicker" price and then quietly raises the price later, so you may want to grab one while it's still $29.99 MachXO 2280 Breakout Board Evaluation Kit: http://www.latticesemi.com/products/developmenthardware/breakoutboardevalkits.cfm -- Gabor PS - I'm not connected to Lattice in any way. Just saw this on an e-mail and thought it might be of interest.Article: 151598
On Apr 22, 6:01=A0pm, Pete Fraser <pfra...@covad.net> wrote: > NeedCleverHandle wrote: > > > This page:<http://www.xilinx.com/products/boards/ml605/ > > reference_designs_12.4_archive.htm> =A0has the instructions and data fo= r > > re-imaging the CF module (they call it the Compact Flash Flash). > > > I would start with that. > > That was the problem. Thanks. > > When I looked at the CF card, the demo there was > something called "CDMA Benchmark Graphing". > > It seems to run a small web server, and graphs > something when I point my browser at the > (hardcoded) ip address of the board. > > The demo seems to work OK, but is not designed > to output anything from the board's video spigots. > > It's a mystery to my why Xilinx ships nicely > printed color "getting started" guides with > detailed instructions on running the supplied demo, > then quietly substitute a _very_ different demo. > > Pete There have been a couple of times were the wrong compact flash card was included with the kit as part of the final assembly step. Can you please confirm the full kit name that you ordered (should start with EK- or DK-) and the part # (should begin with 108) on the bag that the CF card came in so that I can try to figure out what happened? Thanks, Ed McGettigan -- Xilinx Inc.Article: 151599
Ed McGettigan wrote: > > There have been a couple of times were the wrong compact flash card > was included with the kit as part of the final assembly step. > > Can you please confirm the full kit name that you ordered (should > start with EK- or DK-) and the part # (should begin with 108) on the > bag that the CF card came in so that I can try to figure out what > happened? Unfortunately I threw the packing away. I think it was the right CF though. The memory stick that came with the system contains UG668 (v3.0), which is consistent with the CF. The printed documentation is UG730 (v1.1) and discusses the video demo. It also mentions software version 12.1. Perhaps they enclosed the wrong printed material. Strangely enough UG668 and UG730 both have the title: "Getting Started with the Virtex-6 FPGA ML605 Embedded Kit". The video demo would be of more interest to me, but perhaps it's not compatible with 13.1? I went back through the archives, but couldn't find it with the 12.1 release. I'm not sure where it is. Is there anywhere on the web site that gives a summary of the various demos that run on the ML605 platform, and where to find them? I'm really looking forward to the video demo that I saw at x-tech, but I understand that won't be available for a month or so. Thanks Pete
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