Messages from 148975

Article: 148975
Subject: Re: Preventing timing warnings
From: Muzaffer Kal <kal@dspia.com>
Date: Fri, 17 Sep 2010 01:27:14 -0700
Links: << >> << T >> << A >>

On Fri, 17 Sep 2010 02:56:22 -0500, "agb"
<andy.bradford@n_o_s_p_a_m.n_o_s_p_a_m.ultra-ccs.com> wrote:

>>"agb" <andy.bradford@n_o_s_p_a_m.ultra-ccs.com> wrote in message 
>>news:qM2dncyECLMdRg3RnZ2dnUVZ_qydnZ2d@giganews.com...
>>> I'm running some large ModelSim gate level timing simulations which
>>> simulate asynchronous inputs coming in through a metastability
>protected
>>> input. The simulation is giving large numbers of timing violation
>warnings
>>> for these inputs which are expected but unwanted for these input gate
>>> instances.
>>> Does anyone know how I can suppress timing set up and hold warnings for
>>> specific instances only?
>>
>>If you are running Modelsim SE or Questa you can use the 
>>tcheck_set/tcheck_status command (see Reference manual)
>>
>>Hans
>>www.ht-lab.com
>>
>>
>Thanks, but unfortunately I'm running ModelSim PE and implementing on an
>Actel ProAsic Plus FPGA

Then another  option is to edit the SDF file and zero out the
setup/hold values for the specific instances you have in mind.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 148976
Subject: Re: Question about OC PCI Cores
From: rickman <gnuarm@gmail.com>
Date: Fri, 17 Sep 2010 06:23:08 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 16, 10:25 am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> 1. The chip switch from Flex 20K to Virtex II occurs in 2003. At that
> time, I thought both were at the same level of technology. And I heard
> that the price of Virtex II -1000 was even lower than Flex 20K's at
> the time. Maybe there was a promotion selling scheme behind the door
> by Xilinx to encourage customers to switch to its products.

Chip prices are greatly affected by the process generation in two
ways.  One is that newer processes allow more chips off the same size
wafer so the cost per die goes down.  So they can charge less for the
newer generations per LUT.  But average selling price is very
important to them since this is the real determiner of profit.  That's
why they have to keep adding larger and larger parts with high prices
as part of their business model.

The other is that FPGA makers understand the value of design wins
early in the life cycle of a new chip family.  So they will go to
great lengths to get those wins when the chips are still warm from the
prototype ovens.  Once the chips are shipping in volume they already
know how successful their new line is going to be and they start
promoting the next generation.  Xilinx is even bigger at this than the
others.  They will cut prices on new families to the bone.  I once got
a 50,000 qty price on expected shipments of 1,000 per year on a new
part.  A few months later as the design was about to go to production,
I wanted to change to a new package with fewer pins and they would
only match the old price even though the new package would save them
lots of dough.

Between those two effects, I would expect to see nearly a two to one
difference in pricing on parts from different generations if
everything else is equal.  In fact, I am surprised the Altera folks
didn't push you into a newer part.  It's not just a matter of what is
best for the company, the salesmen get big incentives for design wins
on the newest product families.  You did speak with the salesmen from
both companies, right?

> 2. Running frequency is a lifeline: death or live. No matter how good
> your design is, when it fails to reach the specified running
> frequency, all is dead. When redesigning with a new military product,
> the LUT space usage in Virtex II was above 93%. At that time, one can
> imagine that if everything went well except the running frequency, the
> product board had to be redesigned, chips had to be reselected and
> deadline would be rescheduled and a big penalty was pending.
> fortuitously after several fine tuning of compilation parameters,
> using Xilinx ISE 8.x, it passed the 66.7MHz running frequency, but it
> never passed above 66.7MHz using Xlinx ISE 9.x when a colleague tried
> to confirm the running frequency using the latest version of ISE 9.x.

As you say, for some designs frequency is paramount.  But this is not
only a function of the silicon.  The software plays as large a role or
even larger.  That is why I seldom look at a family data sheet if I
want to consider speed.  If the software gives me an inefficient
implementation, the data sheet is useless.  At that time I believe the
older Altera parts were still being designed using MAX+PLUS II.  I can
personally verify that this software was a total dog for getting good
speed results.  They eventually switched all their parts over to
Quartus which gives much better results.  So if you want to make any
general statements comparing two FPGA families, make sure you have
used recent software.

> 3. The PCI legacy circuits from both Altera and Xilinx go into their
> advanced structures of their next generations, but the shortcoming
> with Altera handling PCI bus method doesn't go away as you claim. It
> costs a lot of route resources to get the 66MHz. When LUT space is
> being used up, the problem will pop up and goes after you.

Again, this is a software issue as well.  Unless you have tested your
design on current chips using current software, the comparison means
nothing.

Regards,

Rick

Article: 148977
Subject: Re: New release of HDLmaker
From: rickman <gnuarm@gmail.com>
Date: Fri, 17 Sep 2010 07:20:41 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 16, 8:40=A0pm, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:
> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
> > Hi,
>
> > It'd be very convenient to post the manual in PDF or HTML format online
> > instead of requiring tool installation.
>
> > Thanks,
> > Evgeni
>
> The manual is online. I admit that it's pretty mediocre, one of these
> days I'll take the time to rewrite it.
>
> http://www.polybus.com/hdlmaker/users_guide/id20.htm
>
> http://www.polybus.com/hdlmaker/users_guide/id18.htm

Rather than make me read a mediocre manual, can you briefly describe
this software?  What are the inputs to allow HDL to be generated?

Rick

Article: 148978
Subject: Re: New release of HDLmaker
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 17 Sep 2010 15:19:25 GMT
Links: << >> << T >> << A >>

On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:

> On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote:
>> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
>> > Hi,
>>
>> > It'd be very convenient to post the manual in PDF or HTML format
>> > online instead of requiring tool installation.
>>
>> > Thanks,
>> > Evgeni
>>
>> The manual is online. I admit that it's pretty mediocre, one of these
>> days I'll take the time to rewrite it.
>>
>> http://www.polybus.com/hdlmaker/users_guide/id20.htm
>>
>> http://www.polybus.com/hdlmaker/users_guide/id18.htm
> 
> Rather than make me read a mediocre manual, can you briefly describe
> this software?  What are the inputs to allow HDL to be generated?
> 
> Rick

HDLmaker sources are .top files which instantiate components and contains 
directives for various tools and the .pin file which specify ports as 
well as pin numbers, logic levels, io sets and resets, io registering, 
and timing constraints. HDLmaker has a C like language which allows you 
to calculate signal names, parameter values, conditional operations and 
loops. The output of HDLmaker is either Verilog or VHDL (depending on a 
switch). It has extensive support for Xilinx and Altera tools as well as 
Synplify. It generates Make files for Modelsim/Questa and filelists for 
NC and VCS. It generates UCF and SDC constraint files, Quartus Projects, 
XST scripts. It also has support for Xilinx floorplanning (you can 
generate floor plans using it's C like language.

Where ever possible it uses common directives that are portable across 
tools, for example the #clock command defines clocks, it generates the 
appropriate constraints and directives for Xilinx, Altera, Synplify and 
Precision. In addition to generic directives there are directives that 
are specific to a tool like XST or Quartus. A design that's written in 
HDLmaker is easily portable between tools and technologies and even 
languages.

One of it's main features is that it automatically connects ports as long 
as the port names are the same, i.e. port foo on modules X and Y will be 
connected without having to specify it in the code. If you want to 
connect a port to a different signal or bus then you use the connect 
statement. Signal names and numbers can be calculated if you want, 
HDlmaker does both integer and string arithmetic (for example "foo_a" + 2 
becomes foo_c in the generated code, concatenations and integer and 
string variables are also supported).

There are a number of examples on the web,

http://www.polybus.com/hdlmaker/users_guide/id25.htm

I think I'll add a few more examples in the next few weeks which 
illustrate some of HDLmakers newer features.

Article: 148979
Subject: Re: New release of HDLmaker
From: rickman <gnuarm@gmail.com>
Date: Fri, 17 Sep 2010 14:04:42 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:
> On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
> > On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com> wrote:
> >> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
> >> > Hi,
>
> >> > It'd be very convenient to post the manual in PDF or HTML format
> >> > online instead of requiring tool installation.
>
> >> > Thanks,
> >> > Evgeni
>
> >> The manual is online. I admit that it's pretty mediocre, one of these
> >> days I'll take the time to rewrite it.
>
> >>http://www.polybus.com/hdlmaker/users_guide/id20.htm
>
> >>http://www.polybus.com/hdlmaker/users_guide/id18.htm
>
> > Rather than make me read a mediocre manual, can you briefly describe
> > this software?  What are the inputs to allow HDL to be generated?
>
> > Rick
>
> HDLmaker sources are .top files which instantiate components and contains
> directives for various tools and the .pin file which specify ports as
> well as pin numbers, logic levels, io sets and resets, io registering,
> and timing constraints. HDLmaker has a C like language which allows you
> to calculate signal names, parameter values, conditional operations and
> loops. The output of HDLmaker is either Verilog or VHDL (depending on a
> switch). It has extensive support for Xilinx and Altera tools as well as
> Synplify. It generates Make files for Modelsim/Questa and filelists for
> NC and VCS. It generates UCF and SDC constraint files, Quartus Projects,
> XST scripts. It also has support for Xilinx floorplanning (you can
> generate floor plans using it's C like language.
>
> Where ever possible it uses common directives that are portable across
> tools, for example the #clock command defines clocks, it generates the
> appropriate constraints and directives for Xilinx, Altera, Synplify and
> Precision. In addition to generic directives there are directives that
> are specific to a tool like XST or Quartus. A design that's written in
> HDLmaker is easily portable between tools and technologies and even
> languages.
>
> One of it's main features is that it automatically connects ports as long
> as the port names are the same, i.e. port foo on modules X and Y will be
> connected without having to specify it in the code. If you want to
> connect a port to a different signal or bus then you use the connect
> statement. Signal names and numbers can be calculated if you want,
> HDlmaker does both integer and string arithmetic (for example "foo_a" + 2
> becomes foo_c in the generated code, concatenations and integer and
> string variables are also supported).
>
> There are a number of examples on the web,
>
> http://www.polybus.com/hdlmaker/users_guide/id25.htm
>
> I think I'll add a few more examples in the next few weeks which
> illustrate some of HDLmakers newer features.

So let me make sure I understand.  HDLmaker allows us to program in
its own special language that is C like and largely structural rather
than programming in HDL both structurally specifying logic and/or
inferring logic.

What is better about this than coding in HDL?  I don't get why you are
touting how your tool works with all brands.  HDL by design is vendor
and device and in fact, technology independent.  Most of what you list
above is not anything HDL doesn't do or that I would need to do.

Am I missing the point?

Rick

Article: 148980
Subject: Re: Question about OC PCI Cores
From: Sebastien Bourdeauducq <sebastien.bourdeauducq@gmail.com>
Date: Fri, 17 Sep 2010 15:32:18 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 10, 10:49=A0pm, Gabor <ga...@alacron.com> wrote:
> Xilinx cores make use of special features of certain pins on the
> device with names like IRDY and TRDY that have some built-in logic to spe=
ed up the
> combinatorial PCI requirements. =A0I don't think the synthesis tools supp=
ort these
> functions directly.

AFAIK this function is performed by a special logic cell in the FPGA
called PCILOGIC on Spartan 2 and PCILOGICSE on Spartan 3E/6, with
dedicated routing to the I/Os. To make the those cells appear in FPGA
Editor (they don't by default, apparently Xilinx don't want you to use
them), enter in the FPGA Editor command line (the white text box at
the bottom of the window):
select site *PCI*
add
I guess you can instantiate those primitives in the HDL and the P&R
tool will nicely use the dedicated I/O routing channels.

> =A0However the FPGA's have been getting faster, so you may not need
> the extra stunt hardware to meet PCI timing anymore.

Maybe, but then you have to properly use the UCF constraint system,
which is another evil =3D]

S.

Article: 148981
Subject: Re: Question about OC PCI Cores
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Fri, 17 Sep 2010 16:06:13 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 17, 3:32=A0pm, Sebastien Bourdeauducq
<sebastien.bourdeaud...@gmail.com> wrote:
> On Sep 10, 10:49=A0pm, Gabor <ga...@alacron.com> wrote:
>
> > Xilinx cores make use of special features of certain pins on the
> > device with names like IRDY and TRDY that have some built-in logic to s=
peed up the
> > combinatorial PCI requirements. =A0I don't think the synthesis tools su=
pport these
> > functions directly.
>
> AFAIK this function is performed by a special logic cell in the FPGA
> called PCILOGIC on Spartan 2 and PCILOGICSE on Spartan 3E/6, with
> dedicated routing to the I/Os. To make the those cells appear in FPGA
> Editor (they don't by default, apparently Xilinx don't want you to use
> them), enter in the FPGA Editor command line (the white text box at
> the bottom of the window):
> select site *PCI*
> add
> I guess you can instantiate those primitives in the HDL and the P&R
> tool will nicely use the dedicated I/O routing channels.
>
> > =A0However the FPGA's have been getting faster, so you may not need
> > the extra stunt hardware to meet PCI timing anymore.
>
> Maybe, but then you have to properly use the UCF constraint system,
> which is another evil =3D]
>
> S.

"At that time I believe the
older Altera parts were still being designed using MAX+PLUS II.  I
can
personally verify that this software was a total dog for getting good
speed results.  They eventually switched all their parts over to
Quartus which gives much better results. "

The claim is false. I used Quartus 4.x at that time.

"Do you mean Apex20K? That was released in 1998, I can't find the date
for
the Virtex II release but it was 2001/2002 I think which makes it the
next
generation of devices. "

Yes. Apex 20K. Virtex II release Document mentioned date: V1.1
December 6, 2000.

At the time both were top products for their companies.

Weng

Article: 148982
Subject: Re: New release of HDLmaker
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 18 Sep 2010 01:28:57 GMT
Links: << >> << T >> << A >>

On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:

> On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com>
> wrote:
>> On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
>> > On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com>
>> > wrote:
>> >> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
>> >> > Hi,
>>
>> >> > It'd be very convenient to post the manual in PDF or HTML format
>> >> > online instead of requiring tool installation.
>>
>> >> > Thanks,
>> >> > Evgeni
>>
>> >> The manual is online. I admit that it's pretty mediocre, one of
>> >> these days I'll take the time to rewrite it.
>>
>> >>http://www.polybus.com/hdlmaker/users_guide/id20.htm
>>
>> >>http://www.polybus.com/hdlmaker/users_guide/id18.htm
>>
>> > Rather than make me read a mediocre manual, can you briefly describe
>> > this software?  What are the inputs to allow HDL to be generated?
>>
>> > Rick
>>
>> HDLmaker sources are .top files which instantiate components and
>> contains directives for various tools and the .pin file which specify
>> ports as well as pin numbers, logic levels, io sets and resets, io
>> registering, and timing constraints. HDLmaker has a C like language
>> which allows you to calculate signal names, parameter values,
>> conditional operations and loops. The output of HDLmaker is either
>> Verilog or VHDL (depending on a switch). It has extensive support for
>> Xilinx and Altera tools as well as Synplify. It generates Make files
>> for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
>> SDC constraint files, Quartus Projects, XST scripts. It also has
>> support for Xilinx floorplanning (you can generate floor plans using
>> it's C like language.
>>
>> Where ever possible it uses common directives that are portable across
>> tools, for example the #clock command defines clocks, it generates the
>> appropriate constraints and directives for Xilinx, Altera, Synplify and
>> Precision. In addition to generic directives there are directives that
>> are specific to a tool like XST or Quartus. A design that's written in
>> HDLmaker is easily portable between tools and technologies and even
>> languages.
>>
>> One of it's main features is that it automatically connects ports as
>> long as the port names are the same, i.e. port foo on modules X and Y
>> will be connected without having to specify it in the code. If you want
>> to connect a port to a different signal or bus then you use the connect
>> statement. Signal names and numbers can be calculated if you want,
>> HDlmaker does both integer and string arithmetic (for example "foo_a" +
>> 2 becomes foo_c in the generated code, concatenations and integer and
>> string variables are also supported).
>>
>> There are a number of examples on the web,
>>
>> http://www.polybus.com/hdlmaker/users_guide/id25.htm
>>
>> I think I'll add a few more examples in the next few weeks which
>> illustrate some of HDLmakers newer features.
> 
> So let me make sure I understand.  HDLmaker allows us to program in its
> own special language that is C like and largely structural rather than
> programming in HDL both structurally specifying logic and/or inferring
> logic.
> 
> What is better about this than coding in HDL?  I don't get why you are
> touting how your tool works with all brands.  HDL by design is vendor
> and device and in fact, technology independent.  Most of what you list
> above is not anything HDL doesn't do or that I would need to do.
> 
> Am I missing the point?
> 
> Rick

When I started writing HDLmaker in the early 90's Verilog didn't have any 
generate capabilities and even today it's much less capable then HDLmaker. 
In addition to generating code HDLmaker does the following automatically,

1) It generates project files, scripts, make files and constraint files for lots of different 
tools. Once a design is in HDLmaker you can move from one tool to another 
in seconds.

2) It builds the structure with minimum coding. In the most extreme case 
where all of the ports on the leaf modules have corresponding names all 
you have to do is list the components, for example,

#insert "foo.v";

#insert "bar.v";

#insert "more.top";

3) You can parametrize a design

#for(i=0;i<num_lanes;i++)
{
	#assign vl = "_a" + i;
	#assign lane = "lane_a" + i;
	#assign credit = "credit_level" $ vl;

	#insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
	#parameter VIRTUAL_LANE = i,
	connect IB_CREDIT_LEVEL[12:0]		= #credit[12:0],
	connect IB_FLOW_CTRL_TIMEOUT		= IB_FLOW_CTRL_TIMEOUT[#i],
	connect IB_STAT_RX_ABR_ERR		= rx_abr_err[#i],
	connect IB_TX_CREDIT_AVAIL		= IB_TX_CREDIT_AVAIL[#i],
	connect IB_TX_CREDIT_OK			= IB_TX_CREDIT_OK[#i],
	connect flow_ctrl_violation		= flow_ctrl_violation[#i],
	connect high_priority_request		= high_priority_request[#i],
	connect lane[3:0]			= #lane[3:0],
	connect lane_operational		= lane_operational[#i],
	connect link_packet_ready		= link_packet_ready,
	connect link_packet_valid		= link_packet_valid,
	connect link_packet_vl[3:0]		= link_packet_vl[3:0],
	connect rx_abr[31:0]			= "rx_abr" $ vl[31:0],
	connect nxt_flow_ctrl_packet[31:0]	= "nxt_flow_ctrl_packet" $ vl[31:0],
	connect shadow_credit_near_empty	= shadow_credit_near_empty[#i];
}

4) It's really easy to create your entire structure up front. All you have to do
is define the pin files and the top files for each level. HDLmaker tells you if 
there are any undriven inputs or outputs or bus conflicts.

Here of a pin file. HDLmaker generates the ports of a module from this, including 
the comments.

#nopadring
#pins
IB_LINK_STATE[2:0]	type = in, comment = "Link State, see Vol 1, section 7.2 of the IBA spec
0 LINK_DOWN
1 LINK_INIT
2 LINK_ARM
3 LINK_ACTIVE
4 LINK_ACT_DEFER";

DLANE_OFFSET[2:0]	type = in,comment = "Base Virtual Lane";
IB_BUFFER_SIZE[11:0]	type = in, comment = "Buffer space in 64 byte credits";
IB_BUFFER_SIZE_REQ[3:0]	type = out,comment = "VL of the free space request";
IB_BUFFER_SIZE_REQ_VALID	type = out,comment = "Request free space in VL buffer";
IB_BUFFER_SIZE_VALID	type = in,comment = "Buffer size valud is valid";
IB_BUFFER_SIZE_VL[3:0]	type = in,comment = "VL of buffer space value";
#endpins

5) It generates both Verilog and VHDL code so you can reuse code in both environment.

6) For the top level of an FPGA you can specify all aspects of the pins in a single file.

#uselibrary
#pins
REF_CLK		type = in,logic = PASS,iostandard="1.4-V PCML",input_term = "OCT_100_ohms",comment = "625MHz reference 312",pin = [AL38];

SD_TX[3:0]		type = out,logic = "PASS",comment = "SerDes serial out",iostandard="1.4-V PCML",output_term="OCT 100 OHMS",pin=[AD36,AB36,T36,P36];
SD_RX[3:0]		type = in,logic = "PASS",comment = "SerDes Serial in",iostandard="1.4-V PCML",input_term="OCT 100 OHMS",pin=[AE38,AC38,U38,R38];
PARAM_SEL[7:0]		type = in,comment = "LSBs of the LID, from switches",pin= [AM26,AN26,AP26,AN27,AP27,AT27,AU27,AW27];
gblreset_l		type = in,comment = "Global Async reset",pin=AW18;
#endpins

This will generate not only the Verilog or VHDL for the top level module
and the pad ring module but it will also generate the constraint files
(ucf for Xilinx, the Quartus project file for Altera). 

7) Making changes are really easy, mostly all you have to do is make the changes in the leaf modules,
the structural code is generated by HDLmaker.

8) Coping tool directives from one project to another is easier because
you just have to copy a few lines from a text file. Here are the Quartus
directives from one of my projects,


#beneficial_skew_opt 1;
#combo_logic_for_area 1;
#equiv_logic_removal 0;
#fitter_aggressive_mode "automatically";
#gen_mif 1;
#hold_timing_min_tpd 1;
#mux_restructure 1;
#placement_effort 4;
#register_balancing "yes";
#register_duplication 1;
#remove_duplicate_logic 0;
#rom_recognition 1;
#router_effort 3;
#smart_recompile 0;
#verilog2001 "yes";
#timequest 1;
#signal_tap "demo.stp";
#derive_clocks;

Here is the Quartus project that HDLmaker generated for this design,

# Quartus project file, Generated by HDLmaker Rev 9.3.7
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "Sept 17, 2010"
set_global_assignment -name LAST_QUARTUS_VERSION "10.0"
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/fpga_defs.vh
set_global_assignment -name VERILOG_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625.v
set_global_assignment -name VERILOG_FILE ../../../unit_tests/aqdr_link_layer/common/v/aqdr_traffic_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/fpga/s4gx/v/s4gt_aqdr_link_625.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_10b.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/CRC16_D32.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_tx_crc32x128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_crc16x128.v
set_global_assignment -name VERILOG_FILE ../../../common/crc/v/pb_crc16x32.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/dregce_sr.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_10b.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux2x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_offset_reg.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_regmux2x1.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_async_fifo.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_cmux2x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_match_ab.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/buffer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux4x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_mux8x1.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_or_reduction.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_packet_packer.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_decode_wide_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_decode_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_comma_align.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_decode_8b10b.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_decode_8b10b_ctrl.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_encode_wide_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_base_x_encode_wide.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_encode_8b10b.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_igate.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_sd_qdr_625.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/pb_dreg.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_625_rom.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_wide_qdr_625.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gx_config_ctrl_4x.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gx_reconfig.v
set_global_assignment -name VERILOG_FILE ../../../common/s4gx/v/s4gt_clk_260_625_ref.v
set_global_assignment -name VERILOG_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625_pads.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/PB_IBUF.v
set_global_assignment -name VERILOG_FILE ../../../common/hdlmaker/v/PB_OBUF.v

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SAFE_STATE_MACHINE ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION AUTOMATICALLY
set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF
set_global_assignment -name PARALLEL_SYNTHESIS ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name AUTO_ROM_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION ON
set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
set_global_assignment -name MUX_RESTRUCTURE ON
set_global_assignment -name AUTO_RESOURCE_SHARING ON
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1517
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name FAMILY "STRATIX IV"
set_global_assignment -name TOP_LEVEL_ENTITY s4gt_demo_625
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF

# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_instance_assignment -name MAX_FANOUT "32" -to *
set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name DEVICE EP4S100G2F40i2
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name OPTIMIZE_TIMING "EXTRA EFFORT"
set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 3
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON

# -------------------
# start CLOCK(REF_CLK)

	set_global_assignment -name FMAX_REQUIREMENT "630 MHz" -section_id REF_CLK
	set_global_assignment -name DUTY_CYCLE 50 -section_id REF_CLK

# end CLOCK(REF_CLK)
# -----------------
set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_global_assignment -name ENABLE_CLOCK_LATENCY ON
set_global_assignment -name SMART_RECOMPILE OFF
set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
set_global_assignment -name IGNORE_LCELL_BUFFERS ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL COMPILATION"
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
set_global_assignment -name GENERATE_GXB_RECONFIG_MIF ON
set_global_assignment -name SAVE_DISK_SPACE ON
set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name SIGNALTAP_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "100 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation
set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS ON -section_id eda_simulation
set_location_assignment PIN_AW27 -to PARAM_SEL_pin[0]
set_location_assignment PIN_AU27 -to PARAM_SEL_pin[1]
set_location_assignment PIN_AT27 -to PARAM_SEL_pin[2]
set_location_assignment PIN_AP27 -to PARAM_SEL_pin[3]
set_location_assignment PIN_AN27 -to PARAM_SEL_pin[4]
set_location_assignment PIN_AP26 -to PARAM_SEL_pin[5]
set_location_assignment PIN_AN26 -to PARAM_SEL_pin[6]
set_location_assignment PIN_AM26 -to PARAM_SEL_pin[7]
set_location_assignment PIN_AL38 -to REF_CLK
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to REF_CLK
set_instance_assignment -name INPUT_TERMINATION "OCT_100_OHMS" -to REF_CLK
set_location_assignment PIN_R38 -to SD_RX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[0]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[0]
set_location_assignment PIN_U38 -to SD_RX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[1]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[1]
set_location_assignment PIN_AC38 -to SD_RX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[2]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[2]
set_location_assignment PIN_AE38 -to SD_RX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[3]
set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to SD_RX[3]
set_location_assignment PIN_P36 -to SD_TX[0]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[0]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[0]
set_location_assignment PIN_T36 -to SD_TX[1]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[1]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[1]
set_location_assignment PIN_AB36 -to SD_TX[2]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[2]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[2]
set_location_assignment PIN_AD36 -to SD_TX[3]
set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[3]
set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to SD_TX[3]
set_location_assignment PIN_AW18 -to gblreset_l_pin
set_location_assignment PIN_AN30 -to led_its_alive_pin
set_location_assignment PIN_AV29 -to led_link_active_pin
set_location_assignment PIN_AT29 -to led_link_ddr_pin
set_location_assignment PIN_AU29 -to led_link_qdr_pin
set_location_assignment PIN_AP30 -to led_link_rx_error_pin
set_location_assignment PIN_AW29 -to led_link_up_pin
set_location_assignment PIN_AW30 -to led_loopback_pin
set_location_assignment PIN_AT30 -to led_pass_pin

###############################################################
Here is the Modelsim Make file that HDLmaker generated for this project


VLOG_ARG_FILES = \
	 v/fpga.defs \
	 v/idle.defs



VLOG_ARGS = \
	-f v/fpga.defs \
	-f v/idle.defs


MODEL_OBJS =  \
	work/tcstat \
	work/ib_rxtbmux \
	work/par_gen \
	work/par_txlanemux \
	work/par_traffic_scheduler \
	work/par_scheduler \
	work/ib_idlegen \
	work/ib_idlemon1 \
	work/ib_idlemon \
	work/ib_lts \
	work/lts_timer \
	work/packet_gen \
	work/ib_fcgen \
	work/ib_linkgen \
	work/ib_txlanemux \
	work/ib_traffic_scheduler \
	work/ib_linkscheduler \
	work/ib_phygen \
	work/ib_lphygen \
	work/ib_scheduler \
	work/packet_mon \
	work/ib_phymon \
	work/ib_rxsm \
	work/tb_parameters \
	work/status_tb \
	work/pb_rmux2x1 \
	work/pb_mux4x1 \
	work/pb_mux2x1 \
	work/pb_dreg \
	work/pb_buffer \
	work/par_txbfm \
	work/par_rxbfm \
	work/par_tb \
	work/ib_txbfm \
	work/ib_rxbfm \
	work/ib_clkdivider \
	work/ib_tsmonall \
	work/ib_tsmon \
	work/ib_busphymon \
	work/ib_tb \
	work/glbl \
	work/delayline \
	work/ctrl_tb \
	work/clk_1000mhz \
	work/pcs_tx_input_ctrl \
	work/pcs_tx_ctrl \
	work/aqdr_pcs_tx_lane \
	work/pcs_tx_datapath_wide \
	work/pcs_tx_decode \
	work/pb_packet_packer \
	work/pb_or_reduction \
	work/pb_fifo_serializer4x1 \
	work/pb_async_fifo_early_wr \
	work/pcs_tx_buffer_wide \
	work/pb_mux8x1 \
	work/aqdr_pcs_tx_swap \
	work/aqdr_link_idle_gen \
	work/aqdr_pcs_tx_idle_gen_wide \
	work/pcs_tx_wide \
	work/buffer \
	work/pcs_rx_lpbk_ctrl \
	work/pb_match_ab \
	work/pb_cmux2x1 \
	work/pb_async_fifo \
	work/pcs_rx_loopback \
	work/pb_fifo_deserializer1x4 \
	work/aqdr_pcs_rx_training_lane_wide \
	work/aqdr_pcs_rx_training_ctrl \
	work/aqdr_pcs_rx_training_wide \
	work/pb_regmux2x1 \
	work/aqdr_pcs_rx_swap_ctrl \
	work/aqdr_pcs_rx_swap_wide \
	work/pb_offset_reg \
	work/aqdr_pcs_rx_ctrl \
	work/aqdr_pcs_alignment_buffer \
	work/aqdr_pcs_rx_align_wide \
	work/aqdr_pcs_rx_wide \
	work/aqdr_pcs_reset \
	work/aqdr_pcs_wide_8b \
	work/dregce_sr \
	work/aqdr_ib_link_xmit_status \
	work/aqdr_ib_link_xmit_ctrl \
	work/aqdr_ib_link_tx_mux \
	work/aqdr_ib_link_xmit_dpath \
	work/pb_crc16x32 \
	work/pb_crc16x128 \
	work/aqdr_ib_vcrc_ctrl \
	work/aqdr_ib_vcrc_generator_128 \
	work/pb_tx_crc32x128 \
	work/aqdr_ib_icrc_mask \
	work/aqdr_ib_icrc_generator_128 \
	work/aqdr_ib_link_xmit_crc_gen \
	work/aqdr_ib_link_transmitter \
	work/aqdr_ib_link_rx_status \
	work/aqdr_ib_link_rx_stage \
	work/aqdr_ib_link_rx_datapipe \
	work/aqdr_ib_link_rx_assembler \
	work/aqdr_ib_link_rx_datapath \
	work/aqdr_rx_crc16x128 \
	work/aqdr_rx_crc32x128 \
	work/aqdr_ib_rx_icrc_mask \
	work/aqdr_ib_rx_icrc_generator \
	work/aqdr_ib_link_rx_crc \
	work/aqdr_ib_link_receiver \
	work/aqdr_ib_link_ctrl_fctrl_lane \
	work/aqdr_ib_link_ctrl_fctrl_common \
	work/CRC16_D32 \
	work/aqdr_ib_link_multilane_fctrl \
	work/aqdr_ib_link_ctrl_state_machine \
	work/aqdr_ib_link_ctrl_init_training \
	work/aqdr_ib_link_clk_ctrl \
	work/aqdr_ib_link_control \
	work/aqdr_ib_link_layer \
	work/aqdr_pcs_link_fpga_8b \
	work/fpga_defs \
	work/ibtb_top \
	work/idle_defs \
	work 


all: $(MODEL_OBJS)


work:
	vlib work


clean:
	rm -Rf work
	vlib work


work/idle_defs: ../../fpga_qdr/v/idle_defs.vh  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../fpga_qdr/v/idle_defs.vh
	touch work/idle_defs

work/ibtb_top: ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
	touch work/ibtb_top

work/fpga_defs: ../../../../common/hdlmaker/v/fpga_defs.vh  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../common/hdlmaker/v/fpga_defs.vh
	touch work/fpga_defs

work/aqdr_pcs_link_fpga_8b: ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
	touch work/aqdr_pcs_link_fpga_8b

work/aqdr_ib_link_layer: ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
	touch work/aqdr_ib_link_layer

work/aqdr_ib_link_control: ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
	touch work/aqdr_ib_link_control

work/aqdr_ib_link_clk_ctrl: ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
	touch work/aqdr_ib_link_clk_ctrl

work/aqdr_ib_link_ctrl_init_training: ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
	touch work/aqdr_ib_link_ctrl_init_training

work/aqdr_ib_link_ctrl_state_machine: ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v  $(VLOG_ARG_FILES)
	vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
	touch work/aqdr_ib_link_ctrl_state_machine

###########################################

Here is the file list that it generated for NCsim,

../../fpga_qdr/v/idle_defs.vh
../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
../../../../common/hdlmaker/v/fpga_defs.vh
../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
../../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
../../../../common/crc/v/CRC16_D32.v
../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
../../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
../../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
../../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
../../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
../../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
../../../../common/crc/v/pb_tx_crc32x128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
../../../../common/crc/v/pb_crc16x128.v
../../../../common/crc/v/pb_crc16x32.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
../../../../common/hdlmaker/v/dregce_sr.v
../../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
../../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
../../../../common/hdlmaker/v/pb_offset_reg.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
../../../../common/hdlmaker/v/pb_regmux2x1.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
../../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
../../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
../../../../common/hdlmaker/v/pb_async_fifo.v
../../../../common/hdlmaker/v/pb_cmux2x1.v
../../../../common/hdlmaker/v/pb_match_ab.v
../../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
../../../../common/hdlmaker/v/buffer.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
../../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
../../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
../../../../common/hdlmaker/v/pb_mux8x1.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
../../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
../../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
../../../../common/hdlmaker/v/pb_or_reduction.v
../../../../common/hdlmaker/v/pb_packet_packer.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
../../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
../../../../common/hdlmaker/v/clk_1000mhz.v
../../../../testbench/qdr_link_layer/ctrl_tb/v/ctrl_tb.v
../../../../common/hdlmaker/v/delayline.v
../../../../common/hdlmaker/v/glbl.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tb.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_busphymon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmonall.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_clkdivider.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxbfm.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_txbfm.v
../../../../testbench/qdr_link_layer/par_tb/v/par_tb.v
../../../../testbench/qdr_link_layer/par_tb/v/par_rxbfm.v
../../../../testbench/qdr_link_layer/par_tb/v/par_txbfm.v
../../../../common/hdlmaker/v/pb_buffer.v
../../../../common/hdlmaker/v/pb_dreg.v
../../../../common/hdlmaker/v/pb_mux2x1.v
../../../../common/hdlmaker/v/pb_mux4x1.v
../../../../common/hdlmaker/v/pb_rmux2x1.v
../../../../testbench/qdr_link_layer/ibtb_top/v/status_tb.v
../../../../testbench/aqdr_link_layer/ibtb_top/v/tb_parameters.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxsm.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_phymon.v
../../../../testbench/qdr_link_layer/ib_tb/v/packet_mon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_scheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_lphygen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_phygen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkscheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_traffic_scheduler.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_txlanemux.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkgen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_fcgen.v
../../../../testbench/qdr_link_layer/ib_tb/v/packet_gen.v
../../../../testbench/qdr_link_layer/ib_tb/v/lts_timer.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_lts.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon1.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlegen.v
../../../../testbench/qdr_link_layer/par_tb/v/par_scheduler.v
../../../../testbench/qdr_link_layer/par_tb/v/par_traffic_scheduler.v
../../../../testbench/qdr_link_layer/par_tb/v/par_txlanemux.v
../../../../testbench/qdr_link_layer/par_tb/v/par_gen.v
../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxtbmux.v
../../../../testbench/qdr_link_layer/ibtb_top/v/tcstat.v
+incdir+../../fpga_qdr/in

Article: 148983
Subject: Re: New release of HDLmaker
From: nico@puntnl.niks (Nico Coesel)
Date: Sat, 18 Sep 2010 08:11:16 GMT
Links: << >> << T >> << A >>

General Schvantzkoph <schvantzkoph@yahoo.com> wrote:

>On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:
>
>> On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com>
>> wrote:
>>> On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
>>> > On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com>
>>> > wrote:
>>> >> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
>>> >> > Hi,
>>>
>>> >> > It'd be very convenient to post the manual in PDF or HTML format
>>> >> > online instead of requiring tool installation.
>>>
>>> >> > Thanks,
>>> >> > Evgeni
>>>
>>> >> The manual is online. I admit that it's pretty mediocre, one of
>>> >> these days I'll take the time to rewrite it.
>>>
>>> >>http://www.polybus.com/hdlmaker/users_guide/id20.htm
>>>
>>> >>http://www.polybus.com/hdlmaker/users_guide/id18.htm
>>>
>>> > Rather than make me read a mediocre manual, can you briefly describe
>>> > this software?  What are the inputs to allow HDL to be generated?
>>>
>>> > Rick
>>>
>>> HDLmaker sources are .top files which instantiate components and
>>> contains directives for various tools and the .pin file which specify
>>> ports as well as pin numbers, logic levels, io sets and resets, io
>>> registering, and timing constraints. HDLmaker has a C like language
>>> which allows you to calculate signal names, parameter values,
>>> conditional operations and loops. The output of HDLmaker is either
>>> Verilog or VHDL (depending on a switch). It has extensive support for
>>> Xilinx and Altera tools as well as Synplify. It generates Make files
>>> for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
>>> SDC constraint files, Quartus Projects, XST scripts. It also has
>>> support for Xilinx floorplanning (you can generate floor plans using
>>> it's C like language.
>>>
>>> Where ever possible it uses common directives that are portable across
>>> tools, for example the #clock command defines clocks, it generates the
>>> appropriate constraints and directives for Xilinx, Altera, Synplify and
>>> Precision. In addition to generic directives there are directives that
>>> are specific to a tool like XST or Quartus. A design that's written in
>>> HDLmaker is easily portable between tools and technologies and even
>>> languages.
>>>
>>> One of it's main features is that it automatically connects ports as
>>> long as the port names are the same, i.e. port foo on modules X and Y
>>> will be connected without having to specify it in the code. If you want
>>> to connect a port to a different signal or bus then you use the connect
>>> statement. Signal names and numbers can be calculated if you want,
>>> HDlmaker does both integer and string arithmetic (for example "foo_a" +
>>> 2 becomes foo_c in the generated code, concatenations and integer and
>>> string variables are also supported).
>>>
>>> There are a number of examples on the web,
>>>
>>> http://www.polybus.com/hdlmaker/users_guide/id25.htm
>>>
>>> I think I'll add a few more examples in the next few weeks which
>>> illustrate some of HDLmakers newer features.
>> 
>> So let me make sure I understand.  HDLmaker allows us to program in its
>> own special language that is C like and largely structural rather than
>> programming in HDL both structurally specifying logic and/or inferring
>> logic.
>> 
>> What is better about this than coding in HDL?  I don't get why you are
>> touting how your tool works with all brands.  HDL by design is vendor
>> and device and in fact, technology independent.  Most of what you list
>> above is not anything HDL doesn't do or that I would need to do.
>> 
>> Am I missing the point?
>> 
>> Rick
>
>When I started writing HDLmaker in the early 90's Verilog didn't have any 
>generate capabilities and even today it's much less capable then HDLmaker. 
>In addition to generating code HDLmaker does the following automatically,
>
>1) It generates project files, scripts, make files and constraint files for lots of different 
>tools. Once a design is in HDLmaker you can move from one tool to another 
>in seconds.
>
>2) It builds the structure with minimum coding. In the most extreme case 
>where all of the ports on the leaf modules have corresponding names all 
>you have to do is list the components, for example,
>
>#insert "foo.v";
>
>#insert "bar.v";
>
>#insert "more.top";
>
>3) You can parametrize a design
>
>#for(i=0;i<num_lanes;i++)
>{
>	#assign vl = "_a" + i;
>	#assign lane = "lane_a" + i;
>	#assign credit = "credit_level" $ vl;
>
>	#insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
>	#parameter VIRTUAL_LANE = i,
>	connect IB_CREDIT_LEVEL[12:0]		= #credit[12:0],
>	connect IB_FLOW_CTRL_TIMEOUT		= IB_FLOW_CTRL_TIMEOUT[#i],
>	connect IB_STAT_RX_ABR_ERR		= rx_abr_err[#i],
>	connect IB_TX_CREDIT_AVAIL		= IB_TX_CREDIT_AVAIL[#i],
>	connect IB_TX_CREDIT_OK			= IB_TX_CREDIT_OK[#i],
>	connect flow_ctrl_violation		= flow_ctrl_violation[#i],
>	connect high_priority_request		= high_priority_request[#i],
>	connect lane[3:0]			= #lane[3:0],
>	connect lane_operational		= lane_operational[#i],
>	connect link_packet_ready		= link_packet_ready,
>	connect link_packet_valid		= link_packet_valid,
>	connect link_packet_vl[3:0]		= link_packet_vl[3:0],
>	connect rx_abr[31:0]			= "rx_abr" $ vl[31:0],
>	connect nxt_flow_ctrl_packet[31:0]	= "nxt_flow_ctrl_packet" $ vl[31:0],
>	connect shadow_credit_near_empty	= shadow_credit_near_empty[#i];
>}
>
>4) It's really easy to create your entire structure up front. All you have to do
>is define the pin files and the top files for each level. HDLmaker tells you if 
>there are any undriven inputs or outputs or bus conflicts.
>
>Here of a pin file. HDLmaker generates the ports of a module from this, including 
>the comments.

This seems to me like an extension to Verilog. VHDL already has the
features you describe.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
nico@nctdevpuntnl (punt=.)
--------------------------------------------------------------

Article: 148984
Subject: Re: Question about OC PCI Cores
From: rickman <gnuarm@gmail.com>
Date: Sat, 18 Sep 2010 04:16:00 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 17, 7:06=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Sep 17, 3:32=A0pm, Sebastien Bourdeauducq
>
>
>
> <sebastien.bourdeaud...@gmail.com> wrote:
> > On Sep 10, 10:49=A0pm, Gabor <ga...@alacron.com> wrote:
>
> > > Xilinx cores make use of special features of certain pins on the
> > > device with names like IRDY and TRDY that have some built-in logic to=
 speed up the
> > > combinatorial PCI requirements. =A0I don't think the synthesis tools =
support these
> > > functions directly.
>
> > AFAIK this function is performed by a special logic cell in the FPGA
> > called PCILOGIC on Spartan 2 and PCILOGICSE on Spartan 3E/6, with
> > dedicated routing to the I/Os. To make the those cells appear in FPGA
> > Editor (they don't by default, apparently Xilinx don't want you to use
> > them), enter in the FPGA Editor command line (the white text box at
> > the bottom of the window):
> > select site *PCI*
> > add
> > I guess you can instantiate those primitives in the HDL and the P&R
> > tool will nicely use the dedicated I/O routing channels.
>
> > > =A0However the FPGA's have been getting faster, so you may not need
> > > the extra stunt hardware to meet PCI timing anymore.
>
> > Maybe, but then you have to properly use the UCF constraint system,
> > which is another evil =3D]
>
> > S.
>
> "At that time I believe the
> older Altera parts were still being designed using MAX+PLUS II. =A0I
> can
> personally verify that this software was a total dog for getting good
> speed results. =A0They eventually switched all their parts over to
> Quartus which gives much better results. "
>
> The claim is false. I used Quartus 4.x at that time.
>
> "Do you mean Apex20K? That was released in 1998, I can't find the date
> for
> the Virtex II release but it was 2001/2002 I think which makes it the
> next
> generation of devices. "
>
> Yes. Apex 20K. Virtex II release Document mentioned date: V1.1
> December 6, 2000.
>
> At the time both were top products for their companies.
>
> Weng

Ok, but the fact remains that you are judging these two companies on
products that are multiple generations old using software that is a
decade old.  You are aware that technology advances, right?

Rick

Article: 148985
Subject: Re: New release of HDLmaker
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sat, 18 Sep 2010 17:32:48 -0700
Links: << >> << T >> << A >>

Designing across language barriers sounds good.
Perhaps you should give us a simpler example.
What does a D Flipflop look like in your language.
What does the Verilog and VHDL look like after
it compiles(?).

"General Schvantzkoph" <schvantzkoph@yahoo.com> wrote in message 
news:8fiiupF4btU3@mid.individual.net...
> On Fri, 17 Sep 2010 14:04:42 -0700, rickman wrote:
>
>> On Sep 17, 11:19 am, General Schvantzkoph <schvantzk...@yahoo.com>
>> wrote:
>>> On Fri, 17 Sep 2010 07:20:41 -0700, rickman wrote:
>>> > On Sep 16, 8:40 pm, General Schvantzkoph <schvantzk...@yahoo.com>
>>> > wrote:
>>> >> On Thu, 16 Sep 2010 17:25:26 -0700, OutputLogic wrote:
>>> >> > Hi,
>>>
>>> >> > It'd be very convenient to post the manual in PDF or HTML format
>>> >> > online instead of requiring tool installation.
>>>
>>> >> > Thanks,
>>> >> > Evgeni
>>>
>>> >> The manual is online. I admit that it's pretty mediocre, one of
>>> >> these days I'll take the time to rewrite it.
>>>
>>> >>http://www.polybus.com/hdlmaker/users_guide/id20.htm
>>>
>>> >>http://www.polybus.com/hdlmaker/users_guide/id18.htm
>>>
>>> > Rather than make me read a mediocre manual, can you briefly describe
>>> > this software?  What are the inputs to allow HDL to be generated?
>>>
>>> > Rick
>>>
>>> HDLmaker sources are .top files which instantiate components and
>>> contains directives for various tools and the .pin file which specify
>>> ports as well as pin numbers, logic levels, io sets and resets, io
>>> registering, and timing constraints. HDLmaker has a C like language
>>> which allows you to calculate signal names, parameter values,
>>> conditional operations and loops. The output of HDLmaker is either
>>> Verilog or VHDL (depending on a switch). It has extensive support for
>>> Xilinx and Altera tools as well as Synplify. It generates Make files
>>> for Modelsim/Questa and filelists for NC and VCS. It generates UCF and
>>> SDC constraint files, Quartus Projects, XST scripts. It also has
>>> support for Xilinx floorplanning (you can generate floor plans using
>>> it's C like language.
>>>
>>> Where ever possible it uses common directives that are portable across
>>> tools, for example the #clock command defines clocks, it generates the
>>> appropriate constraints and directives for Xilinx, Altera, Synplify and
>>> Precision. In addition to generic directives there are directives that
>>> are specific to a tool like XST or Quartus. A design that's written in
>>> HDLmaker is easily portable between tools and technologies and even
>>> languages.
>>>
>>> One of it's main features is that it automatically connects ports as
>>> long as the port names are the same, i.e. port foo on modules X and Y
>>> will be connected without having to specify it in the code. If you want
>>> to connect a port to a different signal or bus then you use the connect
>>> statement. Signal names and numbers can be calculated if you want,
>>> HDlmaker does both integer and string arithmetic (for example "foo_a" +
>>> 2 becomes foo_c in the generated code, concatenations and integer and
>>> string variables are also supported).
>>>
>>> There are a number of examples on the web,
>>>
>>> http://www.polybus.com/hdlmaker/users_guide/id25.htm
>>>
>>> I think I'll add a few more examples in the next few weeks which
>>> illustrate some of HDLmakers newer features.
>>
>> So let me make sure I understand.  HDLmaker allows us to program in its
>> own special language that is C like and largely structural rather than
>> programming in HDL both structurally specifying logic and/or inferring
>> logic.
>>
>> What is better about this than coding in HDL?  I don't get why you are
>> touting how your tool works with all brands.  HDL by design is vendor
>> and device and in fact, technology independent.  Most of what you list
>> above is not anything HDL doesn't do or that I would need to do.
>>
>> Am I missing the point?
>>
>> Rick
>
> When I started writing HDLmaker in the early 90's Verilog didn't have any
> generate capabilities and even today it's much less capable then HDLmaker.
> In addition to generating code HDLmaker does the following automatically,
>
> 1) It generates project files, scripts, make files and constraint files 
> for lots of different
> tools. Once a design is in HDLmaker you can move from one tool to another
> in seconds.
>
> 2) It builds the structure with minimum coding. In the most extreme case
> where all of the ports on the leaf modules have corresponding names all
> you have to do is list the components, for example,
>
> #insert "foo.v";
>
> #insert "bar.v";
>
> #insert "more.top";
>
> 3) You can parametrize a design
>
> #for(i=0;i<num_lanes;i++)
> {
> #assign vl = "_a" + i;
> #assign lane = "lane_a" + i;
> #assign credit = "credit_level" $ vl;
>
> #insert "ib_link_ctrl_fctrl_lane.v",name = "fctrl_lane_",
> #parameter VIRTUAL_LANE = i,
> connect IB_CREDIT_LEVEL[12:0] = #credit[12:0],
> connect IB_FLOW_CTRL_TIMEOUT = IB_FLOW_CTRL_TIMEOUT[#i],
> connect IB_STAT_RX_ABR_ERR = rx_abr_err[#i],
> connect IB_TX_CREDIT_AVAIL = IB_TX_CREDIT_AVAIL[#i],
> connect IB_TX_CREDIT_OK = IB_TX_CREDIT_OK[#i],
> connect flow_ctrl_violation = flow_ctrl_violation[#i],
> connect high_priority_request = high_priority_request[#i],
> connect lane[3:0] = #lane[3:0],
> connect lane_operational = lane_operational[#i],
> connect link_packet_ready = link_packet_ready,
> connect link_packet_valid = link_packet_valid,
> connect link_packet_vl[3:0] = link_packet_vl[3:0],
> connect rx_abr[31:0] = "rx_abr" $ vl[31:0],
> connect nxt_flow_ctrl_packet[31:0] = "nxt_flow_ctrl_packet" $ vl[31:0],
> connect shadow_credit_near_empty = shadow_credit_near_empty[#i];
> }
>
> 4) It's really easy to create your entire structure up front. All you have 
> to do
> is define the pin files and the top files for each level. HDLmaker tells 
> you if
> there are any undriven inputs or outputs or bus conflicts.
>
> Here of a pin file. HDLmaker generates the ports of a module from this, 
> including
> the comments.
>
> #nopadring
> #pins
> IB_LINK_STATE[2:0] type = in, comment = "Link State, see Vol 1, section 
> 7.2 of the IBA spec
> 0 LINK_DOWN
> 1 LINK_INIT
> 2 LINK_ARM
> 3 LINK_ACTIVE
> 4 LINK_ACT_DEFER";
>
> DLANE_OFFSET[2:0] type = in,comment = "Base Virtual Lane";
> IB_BUFFER_SIZE[11:0] type = in, comment = "Buffer space in 64 byte 
> credits";
> IB_BUFFER_SIZE_REQ[3:0] type = out,comment = "VL of the free space 
> request";
> IB_BUFFER_SIZE_REQ_VALID type = out,comment = "Request free space in VL 
> buffer";
> IB_BUFFER_SIZE_VALID type = in,comment = "Buffer size valud is valid";
> IB_BUFFER_SIZE_VL[3:0] type = in,comment = "VL of buffer space value";
> #endpins
>
> 5) It generates both Verilog and VHDL code so you can reuse code in both 
> environment.
>
> 6) For the top level of an FPGA you can specify all aspects of the pins in 
> a single file.
>
> #uselibrary
> #pins
> REF_CLK type = in,logic = PASS,iostandard="1.4-V PCML",input_term = 
> "OCT_100_ohms",comment = "625MHz reference 312",pin = [AL38];
>
> SD_TX[3:0] type = out,logic = "PASS",comment = "SerDes serial 
> out",iostandard="1.4-V PCML",output_term="OCT 100 
> OHMS",pin=[AD36,AB36,T36,P36];
> SD_RX[3:0] type = in,logic = "PASS",comment = "SerDes Serial 
> in",iostandard="1.4-V PCML",input_term="OCT 100 
> OHMS",pin=[AE38,AC38,U38,R38];
> PARAM_SEL[7:0] type = in,comment = "LSBs of the LID, from switches",pin= 
> [AM26,AN26,AP26,AN27,AP27,AT27,AU27,AW27];
> gblreset_l type = in,comment = "Global Async reset",pin=AW18;
> #endpins
>
> This will generate not only the Verilog or VHDL for the top level module
> and the pad ring module but it will also generate the constraint files
> (ucf for Xilinx, the Quartus project file for Altera).
>
> 7) Making changes are really easy, mostly all you have to do is make the 
> changes in the leaf modules,
> the structural code is generated by HDLmaker.
>
> 8) Coping tool directives from one project to another is easier because
> you just have to copy a few lines from a text file. Here are the Quartus
> directives from one of my projects,
>
>
> #beneficial_skew_opt 1;
> #combo_logic_for_area 1;
> #equiv_logic_removal 0;
> #fitter_aggressive_mode "automatically";
> #gen_mif 1;
> #hold_timing_min_tpd 1;
> #mux_restructure 1;
> #placement_effort 4;
> #register_balancing "yes";
> #register_duplication 1;
> #remove_duplicate_logic 0;
> #rom_recognition 1;
> #router_effort 3;
> #smart_recompile 0;
> #verilog2001 "yes";
> #timequest 1;
> #signal_tap "demo.stp";
> #derive_clocks;
>
> Here is the Quartus project that HDLmaker generated for this design,
>
> # Quartus project file, Generated by HDLmaker Rev 9.3.7
> # Project-Wide Assignments
> # ========================
> set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0"
> set_global_assignment -name PROJECT_CREATION_TIME_DATE "Sept 17, 2010"
> set_global_assignment -name LAST_QUARTUS_VERSION "10.0"
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/fpga_defs.vh
> set_global_assignment -name VERILOG_FILE 
> ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625.v
> set_global_assignment -name VERILOG_FILE 
> ../../../unit_tests/aqdr_link_layer/common/v/aqdr_traffic_gen.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/fpga/s4gx/v/s4gt_aqdr_link_625.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_10b.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
> set_global_assignment -name VERILOG_FILE ../../../common/crc/v/CRC16_D32.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/crc/v/pb_tx_crc32x128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/crc/v/pb_crc16x128.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/crc/v/pb_crc16x32.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/dregce_sr.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_10b.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_mux2x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_offset_reg.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_regmux2x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_async_fifo.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_cmux2x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_match_ab.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/buffer.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_mux4x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_mux8x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_or_reduction.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_packet_packer.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_base_x_decode_wide_4x.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_base_x_decode_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_comma_align.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_decode_8b10b.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_decode_8b10b_ctrl.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_base_x_encode_wide_4x.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_base_x_encode_wide.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_encode_8b10b.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_igate.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gt_sd_qdr_625.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/pb_dreg.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gt_625_rom.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gt_wide_qdr_625.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gx_config_ctrl_4x.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gx_reconfig.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/s4gx/v/s4gt_clk_260_625_ref.v
> set_global_assignment -name VERILOG_FILE 
> ../../../reference_designs/aqdr_link_layer/altera/s4gx/v/s4gt_demo_625_pads.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/PB_IBUF.v
> set_global_assignment -name VERILOG_FILE 
> ../../../common/hdlmaker/v/PB_OBUF.v
>
> # Analysis & Synthesis Assignments
> # ================================
> set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
> set_global_assignment -name REMOVE_DUPLICATE_REGISTERS OFF
> set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
> set_global_assignment -name SAFE_STATE_MACHINE ON
> set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
> set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
> set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 
> AUTOMATICALLY
> set_global_assignment -name REMOVE_DUPLICATE_LOGIC OFF
> set_global_assignment -name PARALLEL_SYNTHESIS ON
> set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
> set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT ON
> set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
> set_global_assignment -name AUTO_ROM_RECOGNITION ON
> set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
> set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
> set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 
> ON
> set_global_assignment -name STATE_MACHINE_PROCESSING AUTO
> set_global_assignment -name MUX_RESTRUCTURE ON
> set_global_assignment -name AUTO_RESOURCE_SHARING ON
> set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1517
> set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 2
> set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
> set_global_assignment -name FAMILY "STRATIX IV"
> set_global_assignment -name TOP_LEVEL_ENTITY s4gt_demo_625
> set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
>
> # Fitter Assignments
> # ==================
> set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING ON
> set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
> set_instance_assignment -name MAX_FANOUT "32" -to *
> set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
> set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
> set_global_assignment -name DEVICE EP4S100G2F40i2
> set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
> set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
> set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
> set_global_assignment -name OPTIMIZE_TIMING "EXTRA EFFORT"
> set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
> set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
> set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
> set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 3
> set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4
> set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME ON
>
> # -------------------
> # start CLOCK(REF_CLK)
>
> set_global_assignment -name FMAX_REQUIREMENT "630 MHz" -section_id REF_CLK
> set_global_assignment -name DUTY_CYCLE 50 -section_id REF_CLK
>
> # end CLOCK(REF_CLK)
> # -----------------
> set_global_assignment -name ENABLE_DRC_SETTINGS ON
> set_global_assignment -name ENABLE_CLOCK_LATENCY ON
> set_global_assignment -name SMART_RECOMPILE OFF
> set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
> set_global_assignment -name IGNORE_LCELL_BUFFERS ON
> set_global_assignment -name 
> PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
> set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF
> set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "NORMAL 
> COMPILATION"
> set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
> set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
> set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
> set_global_assignment -name SDC_FILE ../constraints/s4gt_demo_625.sdc
> set_global_assignment -name GENERATE_GXB_RECONFIG_MIF ON
> set_global_assignment -name SAVE_DISK_SPACE ON
> set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS OFF
> set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD 
> PATHS"
> set_global_assignment -name SIGNALTAP_FILE 
> ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
> set_global_assignment -name ENABLE_SIGNALTAP ON
> set_global_assignment -name USE_SIGNALTAP_FILE 
> ../../../reference_designs/aqdr_link_layer/altera/s4gx/constraints/demo.stp
> set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
> set_global_assignment -name EDA_SIMULATION_TOOL "NC-Verilog (Verilog)"
> set_global_assignment -name EDA_TIME_SCALE "100 ps" -section_id 
> eda_simulation
> set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG 
> HDL" -section_id eda_simulation
> set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id 
> eda_simulation
> set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS ON -section_id 
> eda_simulation
> set_location_assignment PIN_AW27 -to PARAM_SEL_pin[0]
> set_location_assignment PIN_AU27 -to PARAM_SEL_pin[1]
> set_location_assignment PIN_AT27 -to PARAM_SEL_pin[2]
> set_location_assignment PIN_AP27 -to PARAM_SEL_pin[3]
> set_location_assignment PIN_AN27 -to PARAM_SEL_pin[4]
> set_location_assignment PIN_AP26 -to PARAM_SEL_pin[5]
> set_location_assignment PIN_AN26 -to PARAM_SEL_pin[6]
> set_location_assignment PIN_AM26 -to PARAM_SEL_pin[7]
> set_location_assignment PIN_AL38 -to REF_CLK
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to REF_CLK
> set_instance_assignment -name INPUT_TERMINATION "OCT_100_OHMS" -to REF_CLK
> set_location_assignment PIN_R38 -to SD_RX[0]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[0]
> set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_RX[0]
> set_location_assignment PIN_U38 -to SD_RX[1]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[1]
> set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_RX[1]
> set_location_assignment PIN_AC38 -to SD_RX[2]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[2]
> set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_RX[2]
> set_location_assignment PIN_AE38 -to SD_RX[3]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_RX[3]
> set_instance_assignment -name INPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_RX[3]
> set_location_assignment PIN_P36 -to SD_TX[0]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[0]
> set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_TX[0]
> set_location_assignment PIN_T36 -to SD_TX[1]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[1]
> set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_TX[1]
> set_location_assignment PIN_AB36 -to SD_TX[2]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[2]
> set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_TX[2]
> set_location_assignment PIN_AD36 -to SD_TX[3]
> set_instance_assignment -name IO_STANDARD "1.4-V PCML" -to SD_TX[3]
> set_instance_assignment -name OUTPUT_TERMINATION "OCT 100 OHMS" -to 
> SD_TX[3]
> set_location_assignment PIN_AW18 -to gblreset_l_pin
> set_location_assignment PIN_AN30 -to led_its_alive_pin
> set_location_assignment PIN_AV29 -to led_link_active_pin
> set_location_assignment PIN_AT29 -to led_link_ddr_pin
> set_location_assignment PIN_AU29 -to led_link_qdr_pin
> set_location_assignment PIN_AP30 -to led_link_rx_error_pin
> set_location_assignment PIN_AW29 -to led_link_up_pin
> set_location_assignment PIN_AW30 -to led_loopback_pin
> set_location_assignment PIN_AT30 -to led_pass_pin
>
> ###############################################################
> Here is the Modelsim Make file that HDLmaker generated for this project
>
>
> VLOG_ARG_FILES = \
> v/fpga.defs \
> v/idle.defs
>
>
>
> VLOG_ARGS = \
> -f v/fpga.defs \
> -f v/idle.defs
>
>
> MODEL_OBJS =  \
> work/tcstat \
> work/ib_rxtbmux \
> work/par_gen \
> work/par_txlanemux \
> work/par_traffic_scheduler \
> work/par_scheduler \
> work/ib_idlegen \
> work/ib_idlemon1 \
> work/ib_idlemon \
> work/ib_lts \
> work/lts_timer \
> work/packet_gen \
> work/ib_fcgen \
> work/ib_linkgen \
> work/ib_txlanemux \
> work/ib_traffic_scheduler \
> work/ib_linkscheduler \
> work/ib_phygen \
> work/ib_lphygen \
> work/ib_scheduler \
> work/packet_mon \
> work/ib_phymon \
> work/ib_rxsm \
> work/tb_parameters \
> work/status_tb \
> work/pb_rmux2x1 \
> work/pb_mux4x1 \
> work/pb_mux2x1 \
> work/pb_dreg \
> work/pb_buffer \
> work/par_txbfm \
> work/par_rxbfm \
> work/par_tb \
> work/ib_txbfm \
> work/ib_rxbfm \
> work/ib_clkdivider \
> work/ib_tsmonall \
> work/ib_tsmon \
> work/ib_busphymon \
> work/ib_tb \
> work/glbl \
> work/delayline \
> work/ctrl_tb \
> work/clk_1000mhz \
> work/pcs_tx_input_ctrl \
> work/pcs_tx_ctrl \
> work/aqdr_pcs_tx_lane \
> work/pcs_tx_datapath_wide \
> work/pcs_tx_decode \
> work/pb_packet_packer \
> work/pb_or_reduction \
> work/pb_fifo_serializer4x1 \
> work/pb_async_fifo_early_wr \
> work/pcs_tx_buffer_wide \
> work/pb_mux8x1 \
> work/aqdr_pcs_tx_swap \
> work/aqdr_link_idle_gen \
> work/aqdr_pcs_tx_idle_gen_wide \
> work/pcs_tx_wide \
> work/buffer \
> work/pcs_rx_lpbk_ctrl \
> work/pb_match_ab \
> work/pb_cmux2x1 \
> work/pb_async_fifo \
> work/pcs_rx_loopback \
> work/pb_fifo_deserializer1x4 \
> work/aqdr_pcs_rx_training_lane_wide \
> work/aqdr_pcs_rx_training_ctrl \
> work/aqdr_pcs_rx_training_wide \
> work/pb_regmux2x1 \
> work/aqdr_pcs_rx_swap_ctrl \
> work/aqdr_pcs_rx_swap_wide \
> work/pb_offset_reg \
> work/aqdr_pcs_rx_ctrl \
> work/aqdr_pcs_alignment_buffer \
> work/aqdr_pcs_rx_align_wide \
> work/aqdr_pcs_rx_wide \
> work/aqdr_pcs_reset \
> work/aqdr_pcs_wide_8b \
> work/dregce_sr \
> work/aqdr_ib_link_xmit_status \
> work/aqdr_ib_link_xmit_ctrl \
> work/aqdr_ib_link_tx_mux \
> work/aqdr_ib_link_xmit_dpath \
> work/pb_crc16x32 \
> work/pb_crc16x128 \
> work/aqdr_ib_vcrc_ctrl \
> work/aqdr_ib_vcrc_generator_128 \
> work/pb_tx_crc32x128 \
> work/aqdr_ib_icrc_mask \
> work/aqdr_ib_icrc_generator_128 \
> work/aqdr_ib_link_xmit_crc_gen \
> work/aqdr_ib_link_transmitter \
> work/aqdr_ib_link_rx_status \
> work/aqdr_ib_link_rx_stage \
> work/aqdr_ib_link_rx_datapipe \
> work/aqdr_ib_link_rx_assembler \
> work/aqdr_ib_link_rx_datapath \
> work/aqdr_rx_crc16x128 \
> work/aqdr_rx_crc32x128 \
> work/aqdr_ib_rx_icrc_mask \
> work/aqdr_ib_rx_icrc_generator \
> work/aqdr_ib_link_rx_crc \
> work/aqdr_ib_link_receiver \
> work/aqdr_ib_link_ctrl_fctrl_lane \
> work/aqdr_ib_link_ctrl_fctrl_common \
> work/CRC16_D32 \
> work/aqdr_ib_link_multilane_fctrl \
> work/aqdr_ib_link_ctrl_state_machine \
> work/aqdr_ib_link_ctrl_init_training \
> work/aqdr_ib_link_clk_ctrl \
> work/aqdr_ib_link_control \
> work/aqdr_ib_link_layer \
> work/aqdr_pcs_link_fpga_8b \
> work/fpga_defs \
> work/ibtb_top \
> work/idle_defs \
> work
>
>
> all: $(MODEL_OBJS)
>
>
> work:
> vlib work
>
>
> clean:
> rm -Rf work
> vlib work
>
>
> work/idle_defs: ../../fpga_qdr/v/idle_defs.vh  $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../fpga_qdr/v/idle_defs.vh
> touch work/idle_defs
>
> work/ibtb_top: ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
> touch work/ibtb_top
>
> work/fpga_defs: ../../../../common/hdlmaker/v/fpga_defs.vh 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../common/hdlmaker/v/fpga_defs.vh
> touch work/fpga_defs
>
> work/aqdr_pcs_link_fpga_8b: 
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
> touch work/aqdr_pcs_link_fpga_8b
>
> work/aqdr_ib_link_layer: 
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
> touch work/aqdr_ib_link_layer
>
> work/aqdr_ib_link_control: 
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
> touch work/aqdr_ib_link_control
>
> work/aqdr_ib_link_clk_ctrl: 
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
> touch work/aqdr_ib_link_clk_ctrl
>
> work/aqdr_ib_link_ctrl_init_training: 
> ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
> touch work/aqdr_ib_link_ctrl_init_training
>
> work/aqdr_ib_link_ctrl_state_machine: 
> ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v 
> $(VLOG_ARG_FILES)
> vlog -vlog01compat -vopt -O4 -work work $(VLOG_ARGS) 
> ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
> touch work/aqdr_ib_link_ctrl_state_machine
>
> ###########################################
>
> Here is the file list that it generated for NCsim,
>
> ../../fpga_qdr/v/idle_defs.vh
> ../../../../testbench/aqdr_link_layer/fpga_qdr/v/ibtb_top.v
> ../../../../common/hdlmaker/v/fpga_defs.vh
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_pcs_link_fpga_8b.v
> ../../../../cores/aqdr_link_layer/top_level/v/aqdr_ib_link_layer.v
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_control.v
> ../../../../cores/aqdr_link_layer/control/control_top/v/aqdr_ib_link_clk_ctrl.v
> ../../../../cores/aqdr_link_layer/control/init_and_training/v/aqdr_ib_link_ctrl_init_training.v
> ../../../../cores/aqdr_link_layer/control/link_state/v/aqdr_ib_link_ctrl_state_machine.v
> ../../../../cores/aqdr_link_layer/flow_control/vlanes_8/v/aqdr_ib_link_multilane_fctrl.v
> ../../../../common/crc/v/CRC16_D32.v
> ../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_common.v
> ../../../../cores/aqdr_link_layer/flow_control/common/v/aqdr_ib_link_ctrl_fctrl_lane.v
> ../../../../cores/aqdr_link_layer/receiver/common/v/aqdr_ib_link_receiver.v
> ../../../../cores/aqdr_link_layer/receiver/crc/v/aqdr_ib_link_rx_crc.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_generator.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_rx_icrc_mask.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc32x128.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_rx_crc16x128.v
> ../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapath.v
> ../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_assembler.v
> ../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_datapipe.v
> ../../../../cores/aqdr_link_layer/receiver/datapath/v/aqdr_ib_link_rx_stage.v
> ../../../../cores/aqdr_link_layer/receiver/status/v/aqdr_ib_link_rx_status.v
> ../../../../cores/aqdr_link_layer/transmitter/common/v/aqdr_ib_link_transmitter.v
> ../../../../cores/aqdr_link_layer/transmitter/crc/v/aqdr_ib_link_xmit_crc_gen.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_generator_128.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_icrc_mask.v
> ../../../../common/crc/v/pb_tx_crc32x128.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_generator_128.v
> ../../../../cores/aqdr_link_layer/crc/v/aqdr_ib_vcrc_ctrl.v
> ../../../../common/crc/v/pb_crc16x128.v
> ../../../../common/crc/v/pb_crc16x32.v
> ../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_dpath.v
> ../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_tx_mux.v
> ../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_ctrl.v
> ../../../../cores/aqdr_link_layer/transmitter/datapath/v/aqdr_ib_link_xmit_status.v
> ../../../../common/hdlmaker/v/dregce_sr.v
> ../../../../cores/pcs_layer/top_level/v/aqdr_pcs_wide_8b.v
> ../../../../cores/pcs_layer/top_level/v/aqdr_pcs_reset.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_wide.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_align_wide.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_alignment_buffer.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_ctrl.v
> ../../../../common/hdlmaker/v/pb_offset_reg.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_wide.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_swap_ctrl.v
> ../../../../common/hdlmaker/v/pb_regmux2x1.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_wide.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_ctrl.v
> ../../../../cores/pcs_layer/receiver/v/aqdr_pcs_rx_training_lane_wide.v
> ../../../../common/hdlmaker/v/pb_fifo_deserializer1x4.v
> ../../../../cores/pcs_layer/receiver/v/pcs_rx_loopback.v
> ../../../../common/hdlmaker/v/pb_async_fifo.v
> ../../../../common/hdlmaker/v/pb_cmux2x1.v
> ../../../../common/hdlmaker/v/pb_match_ab.v
> ../../../../cores/pcs_layer/receiver/v/pcs_rx_lpbk_ctrl.v
> ../../../../common/hdlmaker/v/buffer.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_wide.v
> ../../../../cores/aqdr_link_layer/pcs/v/aqdr_pcs_tx_idle_gen_wide.v
> ../../../../cores/aqdr_link_layer/pcs/v/aqdr_link_idle_gen.v
> ../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_swap.v
> ../../../../common/hdlmaker/v/pb_mux8x1.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_buffer_wide.v
> ../../../../common/hdlmaker/v/pb_async_fifo_early_wr.v
> ../../../../common/hdlmaker/v/pb_fifo_serializer4x1.v
> ../../../../common/hdlmaker/v/pb_or_reduction.v
> ../../../../common/hdlmaker/v/pb_packet_packer.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_decode.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_datapath_wide.v
> ../../../../cores/pcs_layer/transmitter/v/aqdr_pcs_tx_lane.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_ctrl.v
> ../../../../cores/pcs_layer/transmitter/v/pcs_tx_input_ctrl.v
> ../../../../common/hdlmaker/v/clk_1000mhz.v
> ../../../../testbench/qdr_link_layer/ctrl_tb/v/ctrl_tb.v
> ../../../../common/hdlmaker/v/delayline.v
> ../../../../common/hdlmaker/v/glbl.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_tb.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_busphymon.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmon.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_tsmonall.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_clkdivider.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxbfm.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_txbfm.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_tb.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_rxbfm.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_txbfm.v
> ../../../../common/hdlmaker/v/pb_buffer.v
> ../../../../common/hdlmaker/v/pb_dreg.v
> ../../../../common/hdlmaker/v/pb_mux2x1.v
> ../../../../common/hdlmaker/v/pb_mux4x1.v
> ../../../../common/hdlmaker/v/pb_rmux2x1.v
> ../../../../testbench/qdr_link_layer/ibtb_top/v/status_tb.v
> ../../../../testbench/aqdr_link_layer/ibtb_top/v/tb_parameters.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxsm.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_phymon.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/packet_mon.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_scheduler.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_lphygen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_phygen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkscheduler.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_traffic_scheduler.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_txlanemux.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_linkgen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_fcgen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/packet_gen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/lts_timer.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_lts.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlemon1.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_idlegen.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_scheduler.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_traffic_scheduler.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_txlanemux.v
> ../../../../testbench/qdr_link_layer/par_tb/v/par_gen.v
> ../../../../testbench/qdr_link_layer/ib_tb/v/ib_rxtbmux.v
> ../../../../testbench/qdr_link_layer/ibtb_top/v/tcstat.v
> +incdir+../../fpga_qdr/in
>
>
>

Article: 148986
Subject: Re: New release of HDLmaker
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 19 Sep 2010 01:59:56 GMT
Links: << >> << T >> << A >>

On Sat, 18 Sep 2010 17:32:48 -0700, Brad Smallridge wrote:

> Designing across language barriers sounds good. Perhaps you should give
> us a simpler example. What does a D Flipflop look like in your language.
> What does the Verilog and VHDL look like after it compiles(?).

HDLmaker builds structural code, you still have to write the leaf cells. 
What it does is hook everything together for you. In addition it creates 
the project, constraint, script and make files for all of the most common 
tools. It has other capabilities also, for example it will convert the MIF 
files that Quartus generates in to Verilog code.

Article: 148987
Subject: Re: interrupt handler arguments
From: Michael Karas <mkaras@carouselDASHdesign.com>
Date: Sat, 18 Sep 2010 22:55:26 -0700
Links: << >> << T >> << A >>

In article <6016bdb3-2ece-44d4-8945-
cb442b57d55b@t11g2000vbc.googlegroups.com>, jmariano65@gmail.com says...
> 
> Hi everybody,
> 
> 
> Sorry if this is a basic question.
> 
> I'm trying to implement a interrupt handler for the UARTLite in my
> mBlaze system. The chain is: mBlaze->IntCtrl->Uart. The IntCtrl is to
> add future interrupt sources.  I'm using as an example the code from
> XAPP808 - FPGA Motor Control Reference Design by Craig Hackney.
> 
> 
> What I don't understand is the actual handler structure. It looks like
> this:
> 
> void serialCommRecv (void *param, unsigned int byteCount)
> {
>    do
>    {
>       // do something
>    } while ((byteCount = XUartLite_Recv(( XUartLite *  ) param,
> charBuffer, 1)));
> }
> 
> I don't understand what are the handler function arguments values when
> the function is called and what is the purpose of using arguments in a
> handler? Can anyone explain that to me?
> 
> 
> Tanks,
> 
> mariano

You are correct in questioning the routine you posted. This must be 
called from some other code that loads up the calling parameter 
arguments. A direct interrupt handler would not have any parameters.

-- 

Michael Karas
Carousel Design Solutions
http://www.carousel-design.com

Article: 148988
Subject: Stack Exchange site for programmable logic and FPGA design
From: saar drimer <saardrimer@gmail.com>
Date: Sun, 19 Sep 2010 10:17:41 -0700 (PDT)
Links: << >> << T >> << A >>

Hello comp.arch.fpga,

tl;dr first: I created a proposal for a Stack Exchange site for
"programmable logic and FPGA design"; if you'd like to support it,
(register and then) "follow" it:

  http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2

I'm a long time comp.arch.fpga lurker (about 10 years) with a grand
track record of very few actual posts. Over the years, and recently,
alternatives to this place on usenet were discussed. I think it is
fair to say that the "community" can do better than what usenet
currently has to offer compared to community-support sites for other
topics. I've spent quite a few cycles thinking and researching what's
the best way to get a vendor-independent community-based-and-moderated
support site that will bring us to modern times.

The best I could come up with will give us what I think we need --
*but*, it will take some patience and a bit of effort.

"Stack Exchange" (SE; http://stackexchange.com/) is a set of sites
that allow users to ask technical questions and receive answers from
experts, whose only rewards is ranking, not money. The idea in the
open source community is that once you achieve a certain status
(rank), you'd convert it into contracting gigs or a better job;
basically, you become more visible to the people who may want to hire
you. I think this can work for the people on comp.arch.fpga quite
well. Here's one of the sites, Stack Overflow:

  http://stackoverflow.com/

SE creators have authored a framework that is hard to imitate (there
are OSS clones out there), and they've now chosen an unorthodox usage-
model for it. It's called "area 51":

  http://area51.stackexchange.com/

Basically, people propose themes for an SE sites, then in the
"definition" phase people have to "follow" it and define what are good
and bad topics; then in the "commitment" stage people commit to
contribute; then there's a public beta, and then it becomes an
official site that is "forever" hosted by SE. Their FAQ is here:

  http://area51.stackexchange.com/faq

I created a proposal for "programmable logic and FPGA design" SE site
here:

  http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2

I want people's feedback, and support if they think this is a good
idea -- just register if you need to, "follow" and suggest questions
if you feel like it. If you have reputation on the SE network your
commitment will eventually count for more (a slight problem of the
scheme, imo). In presentation, the site appears as "question and
answers" place, though there is no reason not to use it for discussion
as well -- I hope that once the site reaches the final stage it could
be customized a little bit.

Just to be absolutely clear, I have no affiliation with SE, and
frankly I don't care much for their usage model, though as community-
based-and-moderated support sites go, I think they have a pretty good
thing going.

cheers,
saar.

http://www.saardrimer.com

Article: 148989
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Sun, 19 Sep 2010 17:35:31 -0500
Links: << >> << T >> << A >>

>Hello comp.arch.fpga,

>
>I'm a long time comp.arch.fpga lurker (about 10 years) with a grand
>track record of very few actual posts. Over the years, and recently,
>alternatives to this place on usenet were discussed. I think it is
>fair to say that the "community" can do better than what usenet
>currently has to offer compared to community-support sites for other
>topics. I've spent quite a few cycles thinking and researching what's
>the best way to get a vendor-independent community-based-and-moderated
>support site that will bring us to modern times.
>
>The best I could come up with will give us what I think we need --
>*but*, it will take some patience and a bit of effort.
>
---------------------------------------------------------------------------

I think this could work. My main question is who are these guys and are
they in it for the long haul? Usenet is the ultimate long haul champion and
I wouldn't like it if they flaked out in a couple of years.

The main advantage of  usenet is that everyone knows about it and its a
good place for beginners to start. We would need a group effort to boycott
comp.arch.fpga and respond to any question by asking them to repost it on
stack exchange. Assuming that anyone with internet access could join and
that someone would take to time to make sure that everyone gets a good
answer on that forum then we could pull this off.

I have been on usenet since the 80's and it is sad to see the cesspool that
it has become. I'm all for putting it out of it's misery.

John Eaton 


	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148990
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: Muzaffer Kal <kal@dspia.com>
Date: Sun, 19 Sep 2010 15:57:28 -0700
Links: << >> << T >> << A >>

On Sun, 19 Sep 2010 17:35:31 -0500, "jt_eaton"
<z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> My main question is who are these guys and are
>they in it for the long haul? Usenet is the ultimate long haul champion and
>I wouldn't like it if they flaked out in a couple of years.

My guess would be advertising revenue and/or selling the answers. If
one can convince a competent group of enthusiasts to generate quality
content for free then it's very easy to monetize this. There are many
sites where an internet search hits a question they have listed and to
see the answer someone posted you need to pay and of course the author
of the post was not compensated at all or with "ranking and not
money".
When you post, you transfer a lot of rights to the site and
cumulatively these rights have value which they utilize. Also they get
to keep the collection copyrights so if they go bust in a couple of
years, all of the accumulated posts disappear with them as no one has
the right to copy all of it anymore.
Usenet may have a lot of problems but at least it's still open.

-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Article: 148991
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Sun, 19 Sep 2010 20:54:37 -0500
Links: << >> << T >> << A >>


>When you post, you transfer a lot of rights to the site and
>cumulatively these rights have value which they utilize. Also they get
>to keep the collection copyrights so if they go bust in a couple of
>years, all of the accumulated posts disappear with them as no one has
>the right to copy all of it anymore.
>Usenet may have a lot of problems but at least it's still open.
>
>-- 
>Muzaffer Kal
>
>

The site lists a creative commons copyright for all user supplied input.
That  doesn't look bad. My worry is that everything is free until they
build up enough users then they decide to change the rules.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148992
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Sun, 19 Sep 2010 22:58:47 -0500
Links: << >> << T >> << A >>

Is it my imagination of did all the spam on this newsgroup suddenly
disappear?
I checked google groups and the last piece I saw was dated 10 Aug. I was
sure that there were some more recent stuff.

 	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148993
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: "HT-Lab" <hans64@ht-lab.com>
Date: Mon, 20 Sep 2010 08:51:50 +0100
Links: << >> << T >> << A >>


"saar drimer" <saardrimer@gmail.com> wrote in message 
news:f6ceec28-a5c9-4dea-b0dd-ad4fabde5056@g18g2000vbn.googlegroups.com...
> Hello comp.arch.fpga,
>
> tl;dr first: I created a proposal for a Stack Exchange site for
> "programmable logic and FPGA design"; if you'd like to support it,
> (register and then) "follow" it:
>
> 
> http://area51.stackexchange.com/proposals/20632/programmable-logic-and-fpga-design?referrer=YmxhQ2OJUo-FAaI1gMp5oQ2
>
> I'm a long time comp.arch.fpga lurker (about 10 years) with a grand
> track record of very few actual posts. Over the years, and recently,
> alternatives to this place on usenet were discussed. I think it is
> fair to say that the "community" can do better than what usenet
> currently has to offer

No they can't. There has been many attempts to lure users away to EDA vendor 
specific newsgroups, Twitter streams, Linkin Groups, blogger sites etc etc but 
the simple matter is that Usenet works and is not controlled by somebody with an 
interest.

If you get lots of spam, changes news server, if you get annoyed by somebody get 
a proper newsreader and block them out.

Long live usenet!

Hans
www.ht-lab.com

Article: 148994
Subject: Cant launch ModelSim from Xilin ISE 12.1
From: "muhammad_umer" <muhammad_umer@n_o_s_p_a_m.n_o_s_p_a_m.comsats.edu.pk>
Date: Mon, 20 Sep 2010 03:11:21 -0500
Links: << >> << T >> << A >>

Hi, 
I am developing a design using xilinx ISE 12.1. I have selected ModelSim
6.5 SE for simulations. When i run behavioral simulation following error
comes:


 ----------------------------------------------------------------------------
 * udo file already exist (pie_tb.udo). It will not be re-generated.
 * creating main do file (pie_tb.fdo) for Behavioral Simulation...
    > executing 'D:/modeltech_6.5/win32/vsim.exe -version' to get the
mti_se version...
    > Modelsim version is 6.5
 * determining pre-compiled simulation library path information...
   > using mapping file set by MODELSIM env (D:\modeltech_6.5)...

ERROR: Unable to read the "D:\modeltech_6.5" file.
Reason: couldn't open "D:\modeltech_6.5": permission denied

INFO: Simulation process aborted!
----------------------------------------------------------------------------

any one can please help me and tell me why this problem arise. I am using
administrator account and i also give full rights to modelsim folder. Also
my integrated tools option is set correctly point towards modelsim exe
file.
please guide me how to remove this error.
Thanks in advance	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148995
Subject: Re: Stack Exchange site for programmable logic and FPGA design
From: saar drimer <saardrimer@gmail.com>
Date: Mon, 20 Sep 2010 03:30:57 -0700 (PDT)
Links: << >> << T >> << A >>

HT-Lab:
> No they can't. There has been many attempts to lure users away to EDA vendor
> specific newsgroups, Twitter streams, Linkin Groups, blogger sites etc etc but
> the simple matter is that Usenet works and is not controlled by somebody with an
> interest.

> If you get lots of spam, changes news server, if you get annoyed by somebody get
> a proper newsreader and block them out.

Let's not make this a religious war -- usenet is good for what it is,
but there are other/more efficient ways of sharing information within
a community of people (for me, this isn't about the spam).

> Long live usenet!

It will live long, with or without an SE site.

Some other points that came up:

The content of the SE sites is licensed under the creative commons
with attribution required

  http://creativecommons.org/licenses/by-sa/2.5/
  http://blog.stackoverflow.com/2009/06/attribution-required/

which means that content can be re-hosted, but it has to say where it
came from. They also provide the a data dump of the content

  http://blog.stackoverflow.com/2009/06/stack-overflow-creative-commons-data-dump/

Here's the history of the framework:

  http://en.wikipedia.org/wiki/Stack_Exchange

They have funding and promise to have all sites run for free; I saw
some ads on stackoverflow.com (after disabling ad-block), but not on
the beta sites. And yes, there's always a chance that they will
vaporize in a while, or they turn evil.

cheers,
saar.

Article: 148996
Subject: Re: interrupt handler arguments
From: jmariano <jmariano65@gmail.com>
Date: Mon, 20 Sep 2010 07:32:15 -0700 (PDT)
Links: << >> << T >> << A >>

On Sep 19, 6:55=A0am, Michael Karas <mka...@carouselDASHdesign.com>
wrote:
> In article <6016bdb3-2ece-44d4-8945-
> cb442b57d...@t11g2000vbc.googlegroups.com>, jmarian...@gmail.com says...
>
>
>
>
>
> > Hi everybody,
>
> > Sorry if this is a basic question.
>
> > I'm trying to implement a interrupt handler for the UARTLite in my
> > mBlaze system. The chain is: mBlaze->IntCtrl->Uart. The IntCtrl is to
> > add future interrupt sources. =A0I'm using as an example the code from
> > XAPP808 - FPGA Motor Control Reference Design by Craig Hackney.
>
> > What I don't understand is the actual handler structure. It looks like
> > this:
>
> > void serialCommRecv (void *param, unsigned int byteCount)
> > {
> > =A0 =A0do
> > =A0 =A0{
> > =A0 =A0 =A0 // do something
> > =A0 =A0} while ((byteCount =3D XUartLite_Recv(( XUartLite * =A0) param,
> > charBuffer, 1)));
> > }
>
> > I don't understand what are the handler function arguments values when
> > the function is called and what is the purpose of using arguments in a
> > handler? Can anyone explain that to me?
>
> > Tanks,
>
> > mariano
>
> You are correct in questioning the routine you posted. This must be
> called from some other code that loads up the calling parameter
> arguments. A direct interrupt handler would not have any parameters.
>
> --
>
> Michael Karas
> Carousel Design Solutionshttp://www.carousel-design.com

OK Michael, Tanks. I'm not used to program enbeded systens, hence my
question.
regards,

mariano

Article: 148997
Subject: xilinx FFT core simulation
From: "parvathi69" <parvathi69@n_o_s_p_a_m.gmail.com>
Date: Mon, 20 Sep 2010 09:50:10 -0500
Links: << >> << T >> << A >>

Hi all,

    I am trying to simulate xilinx fft core. I have calculated the bin
size. But i do not know how to view that bin number in Modelsim.

    For example, If my input signal frequency is 10Hz, Sampling rate is 50,
and FFT point is 1024,my Bin size is 204.8. How do i see this with
Modelsim. Please guide me.

    Thanks in advance
    Parvathi

	   
					
---------------------------------------		
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Article: 148998
Subject: Xilinx XST and a State Machine - A Mystery
From: Darol Klawetter <darol.klawetter@l-3com.com>
Date: Mon, 20 Sep 2010 08:52:16 -0700 (PDT)
Links: << >> << T >> << A >>

I recently fixed a problem with one of my state machines, and I think
that the cause could be a bug in Xilinx XST. Below is the code that
produced the failure. The state-machine worked most of the time,
though occasionally the 'phaseRamWE' signal would be stuck low, even
though I could see 'phaseRamReadAdr' and 'phaseRamWriteAdr'
incrementing.  I fixed it by explicitly declaring the desired value of
'phaseRamWE' in every state. Notice that all states are defined so it
should recover from any conditions introduced by asynchronous inputs.

Have any of you seen similar behavior? Appears to be an XST bug to me.



parameter [3:0]
    S1 = 4'b0000,
    S2 = 4'b0001,
    S3 = 4'b0010,
    S4 = 4'b0011,
    S5 = 4'b0100,
    S6 = 4'b0101,
    S7 = 4'b0110,
    S8 = 4'b0111,
    S9 = 4'b1000,
    S10 = 4'b1001,
    S11 = 4'b1010,
    S12 = 4'b1011,
    S13 = 4'b1100,
    S14 = 4'b1101,
    S15 = 4'b1110,
    S16 = 4'b1111;

always @(posedge rst or posedge clk)
begin
   if (rst)                                       // 'rst' is asserted
and deasserted synchronously to 'clk'
   begin
      rfd <= 1'b0;
      phaseRamWE <= 1'b0;
      phaseRamWriteAdr <= 0;
      phaseRamReadAdr <= 0;
      phaseAccum <= 0;
      state <= S1;
   end
   else
   begin
      case (state)
         S1:
         begin
            if (pipeFill == 1'b1)                     // 'pipeFill' is
asynchronous to 'clk'
            begin
               phaseRamWE <= 1'b1;
               state <= S2;
            end
         end

         S2:
         begin
            phaseRamReadAdr <= phaseRamReadAdr + 1;
            state <= S3;
         end


         S3:
         begin
            phaseRamReadAdr <= phaseRamReadAdr + 1;
            state <= S4;
         end

         S4:
         begin
            phaseRamWriteAdr <= phaseRamWriteAdr + 1;
            phaseRamReadAdr <= phaseRamReadAdr + 1;
            state <= S5;
         end

         S5:
         begin
            phaseRamWriteAdr <= phaseRamWriteAdr + 1;
            phaseRamReadAdr <= phaseRamReadAdr + 1;
            state <= S6;
         end

         S6:
         begin
            rfd <= 1'b1;
            phaseRamReadAdr <= phaseRamReadAdr + 1;
            phaseRamWriteAdr <= phaseRamWriteAdr + 1;
            if (start == 1'b0)                        // 'start' is
synchronous
            begin
               state <= S7;
            end
            else
            begin
               state <= S8;
            end
         end


         S7:
         begin
            if (start == 1'b0)                   // 'start' is
synchronous
            begin
               state <= S7;
            end
            else
            begin
               state <= S8;
               phaseRamReadAdr <= phaseRamReadAdr + 1;
               phaseRamWriteAdr <= phaseRamWriteAdr + 1;
            end
         end


         S8:
         begin
            if (start == 1'b0)                      // 'start' is
synchronous
            begin
               state <= S9;
               phaseRamWE <= 1'b0;
               phaseAccum <= 0;
               rfd <= 1'b0;
               phaseRamReadAdr <= 0;
               phaseRamWriteAdr <= 0;
            end
            else
            begin
               state <= S8;
               phaseRamReadAdr <= phaseRamReadAdr + 1;
               phaseRamWriteAdr <= phaseRamWriteAdr + 1;
            end
         end

         S9: state <= S10;
         S10: state <= S11;
         S11: state <= S12;
         S12: state <= S13;
         S13: state <= S14;
         S14: state <= S15;
         S15: state <= S16;
         S16: state <= S1;

      endcase

   end
end

Article: 148999
Subject: Re: Xilinx XST and a State Machine - A Mystery
From: Frank Buss <fb@frank-buss.de>
Date: Mon, 20 Sep 2010 18:00:05 +0200
Links: << >> << T >> << A >>

Darol Klawetter wrote:

> I recently fixed a problem with one of my state machines, and I think
> that the cause could be a bug in Xilinx XST. Below is the code that
> produced the failure. The state-machine worked most of the time,
> though occasionally the 'phaseRamWE' signal would be stuck low, even
> though I could see 'phaseRamReadAdr' and 'phaseRamWriteAdr'
> incrementing.  I fixed it by explicitly declaring the desired value of
> 'phaseRamWE' in every state. Notice that all states are defined so it
> should recover from any conditions introduced by asynchronous inputs.
> 
> Have any of you seen similar behavior? Appears to be an XST bug to me.

I have seen similar behaviour with Altera Quartus. It was the same problem:
asynchronous inputs changed the state machine and sometimes it hangs. I
think it is possible that the state machine is internally implemented with
some more bits and it is possible that it hangs, if there are some timing
violations or meta stability conditions, because then there is an invalid
state encoded and everything can happen with optimized gates. The fix was
easy: Creating an input latch (or even two, if you are paranoid) for each
asynchronous signal to make it synchronous.

-- 
Frank Buss, http://www.frank-buss.de
piano and more: http://www.youtube.com/user/frankbuss

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