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On 01/07/2011 11:49 AM, Chris Maryan wrote: > A coworker and I were debating what do the likes of Intel, IBM and AMD do differently that allows them to design circuits at 3GHz+. In contrast with FPGAs which for the most part run on a similar process node (i.e. 65 or 40nm), but where even the major static blocks (i.e. DSP blocks) are only capable of around 500Mhz performance. Also compare to the fastest ARM chips, graphics chips, most ASICs and other chips which may get up to 1.5GHz, but rarely faster (yes, faster chips do exist, but they are the exception rather than the rule). > Well, one of the differences is that the CPUs are predetermined logic. They only have one "configuration" to get timing closure on, not an infinitely variable number of possibilities. I think that makes a HUGE difference. When they complete the design of some particular functional block, they can know EVERYTHING about it, such as setup and hold times, clock loading, clock skew within the module, etc. With an FPGA, there are a number of variables that add a large 'fuzz factor" to the timing margins and make it a lot harder to operate every FF at the maximum rate. FPGAs are designed to WORK correctly, but are clearly not completely optimized for speed. if you want max speed, you may need a custom part. because the CPU has only one config, they can optimize the speed to the utmost. This only explains part of the difference, of course. JonArticle: 150276
On 01/07/2011 10:19 AM, salimbaba wrote: > > so what can be the problem here?Is is possible that some bank is not > getting proper voltages and while mapping the logic in FPGA, xilinx maps it > to that area, is that possible ? > I am not sure about Spartan 3, but I believe on earlier Spartans this CAn happen. I thought that the symptom would be a failure to program, ie. DONE would stay low, but can't be sure. But, anyway, check ALL power pins to be sure they are getting a valid supply voltage, and that it is compatible with the specified voltage for that bank in your config setup. Also, if any of the banks need a Vref then make sure that is working, too. (I don't think this would affect the ability to program, but it would certainly stop the IO from working.) JonArticle: 150277
On Jan 7, 8:19=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am facing a problem, i stuffed a new FPGA spartan 3 xc3s1000 on a custo= m > board and it is not getting programmed. It gets detected correctly, all t= he > JTAG pins are in the correct state i.e. Pulled up to 2.5v. When i program > the FPGA, xilinx ISE 12.1 says program succeeded but i do not see any > functionality of the FPGA.I am only running a counter in the code on the > incoming clock and viewing it on chipscope. > Chipscope detects the core but does not trigger and gives a message > "waiting for core to be armed" or something like that. > So i changed the clock pin of FPGA assuming that the pin may have been le= ft > dry sold but still the same problem.And yes the clock is coming as i saw = it > on oscilloscope. > > So, i started probing all the signals i.e. DONE, Prog_B and INIT_B to vie= w > their proper behaviour. DONE was going high when xilinx said program > succeeded, INIT_B always goes low at the start of programming sequence. B= ut > Prog_B never goes low :s It should go low to clear the configuration memo= ry > but it doesn't. So, does it have anything to do with the dysfunctional FP= GA > ? > > And i also checked the power rails, before and after programming and they > were stable. > > so what can be the problem here?Is is possible that some bank is not > getting proper voltages and while mapping the logic in FPGA, xilinx maps = it > to that area, is that possible ? > > kindly give me pointers to debug the issue. > > regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Are you sure that the counter has not been optimized away? If there are no outputs the logic reduction may have removed it - bring the MSB of the counter out to a physical pin to ensure this doesn;t happen. kevinArticle: 150278
On Jan 8, 3:48=A0am, JB <jb.dubois....@gmail.com> wrote: > > At least it is not specified by Actel, and as the project targets a > secure aeronautical function, I can't justify the design just by > saying "I tried it a few times, it seems to be working..." > > Do one of you know anything about FF power up level on flash (or > antifuse) FPGA which may not be specified by actel but still true? I'd step back a little, as even if the silicon does have a rudimentary POR, those do NOT correctly register a brown out event. So you need a proper Vcc driven reset device, and that can easily set a 'Hard POR' signature, FF, which is later changed by SW to a Soft- boot state. - especially in a 'secure aeronautical function', you should be avoiding any possible brownout operation. -jgArticle: 150279
On 7 Jan., 18:49, Chris Maryan <kmar...@gmail.com> wrote: > A coworker and I were debating what do the likes of Intel, IBM and AMD do= differently that allows them to design circuits at 3GHz+. In contrast with= FPGAs which for the most part run on a similar process node (i.e. 65 or 40= nm), but where even the major static blocks (i.e. DSP blocks) are only capa= ble of around 500Mhz performance. Also compare to the fastest ARM chips, gr= aphics chips, most ASICs and other chips which may get up to 1.5GHz, but ra= rely faster (yes, faster chips do exist, but they are the exception rather = than the rule). > > So we had some theories about the cause of the difference: > - Intel/IBM are way ahead in their technology development over the likes = of TSMC and UMC. Doesn't AMD use UMC? > - The 3.5GHz logic (i.e. the execution unit pipeline) in an Intel CPU doe= sn't actually run at 3.5GHz. There is a 3.5G clock, but it turns into a mes= s clock enables and logic effectively running at a much slower rate. Though= effective 3GHz performance is still achieved through parallelism. > - The difference is dynamic logic/domino logic/etc. Most common logic des= igns (ASICs, FPGAs, ARM processors) use static logic - a mess of convention= al CMOS gates separated by flops. High performance chips use dynamic logic,= lots of latches and similar tricks to avoid the overhead of static logic. = This idea may not stand up to scrutiny as I understand that the latest Inte= l architectures (Nehalem) are fully static. > - The designers of ASICs/GPUs/FPGAs knowingly make the tradeoff to lower = speeds to reduce power consumption. That is you could get a 3.5GHz ARM proc= essor, but it'd be 100W. > > Anyone have any ideas or knowledge to clarify the issue? Why can Intel, A= MD, and IBM create 3-4GHz chips, when most other chips seem to be limited t= o somewhere between 500MHz-1.5GHz. > > Chris The same question came to my mind a few days ago... For sure they are really running basically on the mentioned clock-rate. And of course the difference to an FPGA is clear (DSP blocks with 2GHz would simply make no sense when the logic fabric is not fast enough). But why is Intel faster than e.g. ARM in terms of maximum clock rate? Better RTL- design (i.e. fewer gates between the flip-flops)? Better process technology? Better use of dynamic logic? Prefering speed over power in the process? Something else? My guess is that it is a little bit of all... I have crossposted this to comp.arch, as we may get there a better answer. ThomasArticle: 150280
Allan The problem with doing boards with DIMM sockets is the I/O count needed is not far off 100 I/O. Cheaper end boards tend to have FPGAs with 100-300 I/O. This leads to a board with limited other features so there usually isn't a lot of logic in doing a dev board with these restrictions for most manufacturers. As soon as you go into boards based on FPGAs that have 300+ I/O they tend to based on the expensive end of Spartan/Cyclone etc or worse still based on the performance families like Virtex or Stratix. I would ask why you want to use a DDR DIMM. You could get the same performance with DDR2 or DDR3 running at faster rates but a narrower interface and that is the concept behind many of our FPGA development boards. If it's size then the DIMM does tend to win although we have some single chip DDR3 designs coming that will give 256 Mbyte and later on 512 Mbyte densities. John Adair Enterpoint Ltd. - Home of Raggedstone3. The Cyclone IV GX Development Board. On Jan 7, 5:09=A0am, Allan Wang <alla...@gmail.com> wrote: > I'm looking for a cheap Altera dev board with DDR RAM and an LVDS > compatible connector. However, it seems like the cheapest one is the > $1000 "Cyclone III FPGA Development Kit". > > I initially thought that the $200 "Cyclone III FPGA Starter Kit" would > work since it has HSMC, but the manual states that it is only intended > for CMOS signals and has no provisions for differential pairs. > > So does there exist a board that meets my requirements that is less > than $500? I know Xilinx does (the Digilent Atlys, which has great > specs), but I'd like to develop for the Cyclone 3/4 because they > support DDR DIMM's while the Spartans do not. If there doesn't exist > such a dev board, it seems to me like there's a huge gap in their line- > up. > > What I want to do is make a daughtercard board for an 11-bit ADC, at > 200MHz DDR. I need twelve LVDS pairs. Perhaps I could just try using > the starter kit board and see if the non-differential pair routing > will still work, but I don't want to just toss $200 away either.Article: 150281
For starters it should be DONE that is used to clear the config memory. Check the configuratin signals by doing a STATUS read using JTAG. THis will tell you losts including if your mode pins are wrong (bad joint elimination). If it is configured check you have a clock and not held in reset (if implemented in your logic). John Adair Enterpoint Ltd. - Home of Drigmorn4. The Spartan-6 Development Board. On Jan 7, 4:19=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am facing a problem, i stuffed a new FPGA spartan 3 xc3s1000 on a custo= m > board and it is not getting programmed. It gets detected correctly, all t= he > JTAG pins are in the correct state i.e. Pulled up to 2.5v. When i program > the FPGA, xilinx ISE 12.1 says program succeeded but i do not see any > functionality of the FPGA.I am only running a counter in the code on the > incoming clock and viewing it on chipscope. > Chipscope detects the core but does not trigger and gives a message > "waiting for core to be armed" or something like that. > So i changed the clock pin of FPGA assuming that the pin may have been le= ft > dry sold but still the same problem.And yes the clock is coming as i saw = it > on oscilloscope. > > So, i started probing all the signals i.e. DONE, Prog_B and INIT_B to vie= w > their proper behaviour. DONE was going high when xilinx said program > succeeded, INIT_B always goes low at the start of programming sequence. B= ut > Prog_B never goes low :s It should go low to clear the configuration memo= ry > but it doesn't. So, does it have anything to do with the dysfunctional FP= GA > ? > > And i also checked the power rails, before and after programming and they > were stable. > > so what can be the problem here?Is is possible that some bank is not > getting proper voltages and while mapping the logic in FPGA, xilinx maps = it > to that area, is that possible ? > > kindly give me pointers to debug the issue. > > regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150282
For starters it should be INIT that is used to clear the config memory. Check the configuratin signals by doing a STATUS read using JTAG. THis will tell you losts including if your mode pins are wrong (bad joint elimination). If it is configured check you have a clock and not held in reset (if implemented in your logic). John Adair Enterpoint Ltd. - Home of Drigmorn4. The Spartan-6 Development Board. On Jan 7, 4:19=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am facing a problem, i stuffed a new FPGA spartan 3 xc3s1000 on a custo= m > board and it is not getting programmed. It gets detected correctly, all t= he > JTAG pins are in the correct state i.e. Pulled up to 2.5v. When i program > the FPGA, xilinx ISE 12.1 says program succeeded but i do not see any > functionality of the FPGA.I am only running a counter in the code on the > incoming clock and viewing it on chipscope. > Chipscope detects the core but does not trigger and gives a message > "waiting for core to be armed" or something like that. > So i changed the clock pin of FPGA assuming that the pin may have been le= ft > dry sold but still the same problem.And yes the clock is coming as i saw = it > on oscilloscope. > > So, i started probing all the signals i.e. DONE, Prog_B and INIT_B to vie= w > their proper behaviour. DONE was going high when xilinx said program > succeeded, INIT_B always goes low at the start of programming sequence. B= ut > Prog_B never goes low :s It should go low to clear the configuration memo= ry > but it doesn't. So, does it have anything to do with the dysfunctional FP= GA > ? > > And i also checked the power rails, before and after programming and they > were stable. > > so what can be the problem here?Is is possible that some bank is not > getting proper voltages and while mapping the logic in FPGA, xilinx maps = it > to that area, is that possible ? > > kindly give me pointers to debug the issue. > > regards > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comArticle: 150283
Is there no demand for an inexpensive dev board with DIMM sockets for the purpose of having large memory? (say, two DIMMs for 4GB total). Does the higher initial dev cost, and higher pin count FPGA really justify these boards being at least $1500+? The 780-pin count Cyclone is around $100 and seems to have enough IO to interface with a DIMM and have plenty of pins left over. On Jan 7, 6:16=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > Allan > > The problem with doing boards with DIMM sockets is the I/O count > needed is not far off 100 I/O. Cheaper end boards tend to have FPGAs > with 100-300 I/O. This leads to a board with limited other features so > there usually isn't a lot of logic in doing a dev board with these > restrictions for most manufacturers. As soon as you go into boards > based on FPGAs that have 300+ I/O they tend to based on the expensive > end of Spartan/Cyclone etc or worse still based on the performance > families like Virtex or Stratix. > > I would ask why you want to use a DDR DIMM. You could get the same > performance with DDR2 or DDR3 running at faster rates but a narrower > interface and that is the concept behind many of our FPGA development > boards. If it's size then the DIMM does tend to win although we have > some single chip DDR3 designs coming that will give 256 Mbyte and > later on 512 Mbyte densities. > > John Adair > Enterpoint Ltd. - Home of Raggedstone3. The Cyclone IV GX Development > Board. > > On Jan 7, 5:09=A0am, Allan Wang <alla...@gmail.com> wrote: > > > > > > > > > I'm looking for a cheap Altera dev board with DDR RAM and an LVDS > > compatible connector. However, it seems like the cheapest one is the > > $1000 "Cyclone III FPGA Development Kit". > > > I initially thought that the $200 "Cyclone III FPGA Starter Kit" would > > work since it has HSMC, but the manual states that it is only intended > > for CMOS signals and has no provisions for differential pairs. > > > So does there exist a board that meets my requirements that is less > > than $500? I know Xilinx does (the Digilent Atlys, which has great > > specs), but I'd like to develop for the Cyclone 3/4 because they > > support DDR DIMM's while the Spartans do not. If there doesn't exist > > such a dev board, it seems to me like there's a huge gap in their line- > > up. > > > What I want to do is make a daughtercard board for an 11-bit ADC, at > > 200MHz DDR. I need twelve LVDS pairs. Perhaps I could just try using > > the starter kit board and see if the non-differential pair routing > > will still work, but I don't want to just toss $200 away either.Article: 150284
On Jan 7, 6:03=A0pm, Thomas Entner <thomas.entne...@gmail.com> wrote: > On 7 Jan., 18:49, Chris Maryan <kmar...@gmail.com> wrote: > > > A coworker and I were debating what do the likes of Intel, IBM and AMD = do differently that allows them to design circuits at 3GHz+. In contrast wi= th FPGAs which for the most part run on a similar process node (i.e. 65 or = 40nm), but where even the major static blocks (i.e. DSP blocks) are only ca= pable of around 500Mhz performance. Also compare to the fastest ARM chips, = graphics chips, most ASICs and other chips which may get up to 1.5GHz, but = rarely faster (yes, faster chips do exist, but they are the exception rathe= r than the rule). > > > So we had some theories about the cause of the difference: > > - Intel/IBM are way ahead in their technology development over the like= s of TSMC and UMC. Doesn't AMD use UMC? > > - The 3.5GHz logic (i.e. the execution unit pipeline) in an Intel CPU d= oesn't actually run at 3.5GHz. There is a 3.5G clock, but it turns into a m= ess clock enables and logic effectively running at a much slower rate. Thou= gh effective 3GHz performance is still achieved through parallelism. > > - The difference is dynamic logic/domino logic/etc. Most common logic d= esigns (ASICs, FPGAs, ARM processors) use static logic - a mess of conventi= onal CMOS gates separated by flops. High performance chips use dynamic logi= c, lots of latches and similar tricks to avoid the overhead of static logic= . This idea may not stand up to scrutiny as I understand that the latest In= tel architectures (Nehalem) are fully static. > > - The designers of ASICs/GPUs/FPGAs knowingly make the tradeoff to lowe= r speeds to reduce power consumption. That is you could get a 3.5GHz ARM pr= ocessor, but it'd be 100W. > > > Anyone have any ideas or knowledge to clarify the issue? Why can Intel,= AMD, and IBM create 3-4GHz chips, when most other chips seem to be limited= to somewhere between 500MHz-1.5GHz. > > > Chris > > The same question came to my mind a few days ago... For sure they are > really running basically on the mentioned clock-rate. And of course > the difference to an FPGA is clear (DSP blocks with 2GHz would simply > make no sense when the logic fabric is not fast enough). But why is > Intel faster than e.g. ARM in terms of maximum clock rate? Better RTL- > design (i.e. fewer gates between the flip-flops)? Better process > technology? Better use of dynamic logic? Prefering speed over power in > the process? Something else? My guess is that it is a little bit of > all... > > I have crossposted this to comp.arch, as we may get there a better > answer. > > Thomas Whip out your Virtex-6 datasheet to find some answers. In the FPGA, the logic cells, slices, whatever you want to call them are pretty fast. Internal time values may be sub 100 ps for clock to Q or setup. All of this is completely swamped by the multi nanosecond routing delays in the same architecture. It's a bit like a miniature version of a PC board full of tiny ASICs. Every time you leave an ASIC, you get hit with big IO buffer delays and board routing delays. Clearly the same process can do quite well timing-wise when you insert "hard" blocks like power PC processors or PCIe endpoint blocks. Altera is touting 25 Gb/s SERDES on their latest process. So really the big culprit is fabric interconnect. You pay a big price for programmability, and a bigger price for finer grain programmability. -- GaborArticle: 150285
In comp.arch.fpga Thomas Entner <thomas.entner99@gmail.com> wrote: (snip) > The same question came to my mind a few days ago... For sure they are > really running basically on the mentioned clock-rate. And of course > the difference to an FPGA is clear (DSP blocks with 2GHz would simply > make no sense when the logic fabric is not fast enough). The FPGA routing fabric is slower than direct wiring, and that comes through to the final speed. But if you do things in parallel, you can get enough done in a given time. > But why is Intel faster than e.g. ARM in terms of maximum clock rate? Clock rate is not a good measure of processor speed. You have to also see how much gets done each clock cycle. For a pipelined design, clock rate is determined by the logic between pipeline registers, and faster is usually better. The tradeoffs are not easy, though, and sometimes the slower clock gets more done. > Better RTL- > design (i.e. fewer gates between the flip-flops)? Better process > technology? Better use of dynamic logic? Prefering speed over power in > the process? Something else? My guess is that it is a little bit of > all... > I have crossposted this to comp.arch, as we may get there a better > answer. -- glenArticle: 150286
On Jan 7, 4:07=A0am, "Morten Leikvoll" <mleik...@yahoo.nospam> wrote:
> >> The code below is some tested and implemented code I found on my drive=
.
>
> NO, ieee.std_logic_arith.all was not in my code. Did you try it?
>
Yes, I did...apparently you did not, even though you called it "tested
and implemented code I found on my drive".
Quartus 10.0 SP1 reports the following error on the statement
"testcnt<=3Dtestcnt+"1"; "
Error (10327): VHDL error at Junk.vhd(341): can't determine definition
of operator ""+"" -- found 0 possible definitions
Modelsim 6.4 reports the following (as I mentioned in the first post)
No feasible entries for infix operator "+".
But before you get those errors, you'll have to clean up another error
because you used the name 'test' as the name of the entity and as a
signal.
architecture rtl of test is
...
test<=3D'0';
As I suggested in my first post, you might want to try out your code
first before posting.
KJ
Article: 150287> The FPGA routing fabric is slower than direct wiring, and that > comes through to the final speed. =A0But if you do things in parallel, > you can get enough done in a given time. As the OP wrote, the question is a little bit off-topic for comp.arch.fpga: I think it is clear to all that an ASIC will always be faster than a FPGA for various reasons in the same process. > > > But why is Intel faster than e.g. ARM in terms of maximum clock rate? > > Clock rate is not a good measure of processor speed. =A0You have to > also see how much gets done each clock cycle. =A0For a pipelined > design, clock rate is determined by the logic between pipeline > registers, and faster is usually better. =A0The tradeoffs are not > easy, though, and sometimes the slower clock gets more done. > But to my knowledge, modern x86-CPUs, with all their out-of-order- stuff, etc. are still more complex than the latest ARM-CPUs. Still they achieve higher clock-rates... ThomasArticle: 150288
On 1/7/2011 3:03 PM, Thomas Entner wrote:
> On 7 Jan., 18:49, Chris Maryan<kmar...@gmail.com> wrote:
>> A coworker and I were debating what do the likes of Intel, IBM and AMD do differently that allows them to design circuits at 3GHz+. In contrast with FPGAs which for the most part run on a similar process node (i.e. 65 or 40nm), but where even the major static blocks (i.e. DSP blocks) are only capable of around 500Mhz performance. Also compare to the fastest ARM chips, graphics chips, most ASICs and other chips which may get up to 1.5GHz, but rarely faster (yes, faster chips do exist, but they are the exception rather than the rule).
>>
>> So we had some theories about the cause of the difference:
>> - Intel/IBM are way ahead in their technology development over the likes of TSMC and UMC. Doesn't AMD use UMC?
>> - The 3.5GHz logic (i.e. the execution unit pipeline) in an Intel CPU doesn't actually run at 3.5GHz. There is a 3.5G clock, but it turns into a mess clock enables and logic effectively running at a much slower rate. Though effective 3GHz performance is still achieved through parallelism.
>> - The difference is dynamic logic/domino logic/etc. Most common logic designs (ASICs, FPGAs, ARM processors) use static logic - a mess of conventional CMOS gates separated by flops. High performance chips use dynamic logic, lots of latches and similar tricks to avoid the overhead of static logic. This idea may not stand up to scrutiny as I understand that the latest Intel architectures (Nehalem) are fully static.
>> - The designers of ASICs/GPUs/FPGAs knowingly make the tradeoff to lower speeds to reduce power consumption. That is you could get a 3.5GHz ARM processor, but it'd be 100W.
>>
>> Anyone have any ideas or knowledge to clarify the issue? Why can Intel, AMD, and IBM create 3-4GHz chips, when most other chips seem to be limited to somewhere between 500MHz-1.5GHz.
>>
>> Chris
>
> The same question came to my mind a few days ago... For sure they are
> really running basically on the mentioned clock-rate. And of course
> the difference to an FPGA is clear (DSP blocks with 2GHz would simply
> make no sense when the logic fabric is not fast enough). But why is
> Intel faster than e.g. ARM in terms of maximum clock rate? Better RTL-
> design (i.e. fewer gates between the flip-flops)? Better process
> technology? Better use of dynamic logic? Prefering speed over power in
> the process? Something else? My guess is that it is a little bit of
> all...
>
> I have crossposted this to comp.arch, as we may get there a better
> answer.
>
> Thomas
The main difference: full custom VLSI is faster than ASIC cell based
design is faster than FPGA design.
I am often amazed the other way, at how fast FPGAs are: every time I
look at FPGAs from first principles, I see them as 10X to 16X slower
than full custom design. Yet they are actually closer than that.
Ditto ASIC cell based design. Now, Intel and AMD both do cell based
design, but not necessarily everywhere, and/or are quite willing to
rework the cell library in critical areas. You can often see the
difference on a cell photo: the sort of stack of boxes and then routing
that is typical of cell based design, versus the really dense datapaths
typical of full custom.
Other differences: Intel's big design teams. There's a lot more manual
work at Intel than at many other places. It's worth it, given Intel's
manufacturing runs, to spend a lot of money to make the chip 10%
smaller, but that almost directly translates to profit.
Other points from the original poster and crossposter.
>> - Intel/IBM are way ahead in their technology development over the
likes of TSMC and UMC. Doesn't AMD use UMC?
Intel fabs are often ahead of TSMC and UMC and GF. But this doesn't
explain the whole difference, not by a long shot, especially given AMD's
situation.
By the way, an interesting conversation is why IBM is above 5GHz,
whereas Intel is not.
>> - The 3.5GHz logic (i.e. the execution unit pipeline) in an Intel
CPU doesn't actually run at 3.5GHz. There is a 3.5G clock, but it turns
into a mess clock enables and logic effectively running at a much slower
rate. Though effective 3GHz performance is still achieved through
parallelism.
While certainly this trick should be in every designer's toolbox, it is
not overall true. Large parts of the CPUs run at the above 3 GHz frequency.
(Way back in Willamette, the important parts of the chip ran at 2X the
published frequency. Not so much any more.)
>> - The difference is dynamic logic/domino logic/etc. Most common
logic designs (ASICs, FPGAs, ARM processors) use static logic - a mess
of conventional CMOS gates separated by flops. High performance chips
use dynamic logic, lots of latches and similar tricks to avoid the
overhead of static logic. This idea may not stand up to scrutiny as I
understand that the latest Intel architectures (Nehalem) are fully static.
Again, while domino, etc., are an option for every project, many recent
Intel projects have been full static.
E.g. googling "intel nehalem static cmos"
IDF: Inside Nehalem - HotHardware
Aug 22, 2008 ... Another way Intel managed to keep the power
requirements for Nehalem relatively low (130 watts TDP) was by using
static CMOS for all of the ...
hothardware.com/Articles/IDF-Inside-Nehalem/?page=3
[PDF] Intel and Core i7 (Nehalem) Dynamic Power Management
File Format: PDF/Adobe Acrobat - Quick View
hungry. To save power, Intel circuit designers decided to switch
from domino logic to static CMOS based logic circuits when
implementing Nehalem. ...
cs466.andersonje.com/public/pm.pdf - Similar
(I haven't found similarly clear statements for Intel Sandybridge, Atom,
or AMD. But I haven't bothered to look at ISSCC papers. Yet.)
Article: 150289Dear my valuable friends > actually i want to design the SRAM IP core for FPGA , i have one SRAM cel= l schematic and layout for different technology 90nm,.. first i need to gen= erate benchmark for that or if find available bench mark to use this cell i= nstead current cell then can verify my sram and then should be generate ip = core for this module , i search in internet but could not find useful infor= mation to how to do that or this way is correct or not , so could you pleas= e help me even introduce the good references or the software requirement fo= r this problem > > i looking forward your helps friend > > > best regardsArticle: 150290
I routed the signal to an external debug pin and observed the signal on scope but no success. Counter being optimized away can happen, but even if it is getting optimized away, chipscope should trigger. It doesnt get triggered so, anything else ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150291
Allan The problem is that there is limited demand but for that exact configuration that you want so the market is very small. Typically it might cost $30K to launch even a simple board like this for a manufacturer like us. So if you only think you might sell only 100 in the product lifetime that is $300 you have to recover off every board you sell on top of the manufacture, profit, and risk costs. Suddenly you have a board that is heading to sell at $500+. Obviously if the numbers change and you think you can sell 1000 boards the launch cost per board then drops to $30 and you might have a $300-$400 sell price. Going to the $1500 boards these typically will have an even higher development cost and market will not be enormous. Typically if you think that a normal customer doing a development will only buy one or two development boards and then will either design their own based on the dev boards schematics, or even come to a company like us to produce a derived design, the overall numbers are very low. If all that we did here was development boards I doubt Enterpoint would be operating today never mind heading for another record year. In numbers our standard development boards are a tiny percentage of the boards we design and manufacture now. Aside from the narrow market a large percentage of dev boards are also designed and manufactured by distributors and they usually want to add as many of there other line products onto their boards thereby facilitating sales of those products. Boards done by Xilinx and Altera are usually a combination of features asked for by customers and internal customers (FAE and Apps guys) so these are usually not lightweight boards for that reason. We don't have these problems and it allows us to be more flexible but even then we always have to consider the market size on standard boards. As always there is the odd exception to the rule so you might find someone doing what you want if you look hard enough. John Adair Enterpoint Ltd. On Jan 7, 11:44=A0pm, Allan Wang <alla...@gmail.com> wrote: > Is there no demand for an inexpensive dev board with DIMM sockets for > the purpose of having large memory? (say, two DIMMs for 4GB total). > Does the higher initial dev cost, and higher pin count FPGA really > justify these boards being at least $1500+? > > The 780-pin count Cyclone is around $100 and seems to have enough IO > to interface with a DIMM and have plenty of pins left over. > > On Jan 7, 6:16=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > > > Allan > > > The problem with doing boards with DIMM sockets is the I/O count > > needed is not far off 100 I/O. Cheaper end boards tend to have FPGAs > > with 100-300 I/O. This leads to a board with limited other features so > > there usually isn't a lot of logic in doing a dev board with these > > restrictions for most manufacturers. As soon as you go into boards > > based on FPGAs that have 300+ I/O they tend to based on the expensive > > end of Spartan/Cyclone etc or worse still based on the performance > > families like Virtex or Stratix. > > > I would ask why you want to use a DDR DIMM. You could get the same > > performance with DDR2 or DDR3 running at faster rates but a narrower > > interface and that is the concept behind many of our FPGA development > > boards. If it's size then the DIMM does tend to win although we have > > some single chip DDR3 designs coming that will give 256 Mbyte and > > later on 512 Mbyte densities. > > > John Adair > > Enterpoint Ltd. - Home of Raggedstone3. The Cyclone IV GX Development > > Board. > > > On Jan 7, 5:09=A0am, Allan Wang <alla...@gmail.com> wrote: > > > > I'm looking for a cheap Altera dev board with DDR RAM and an LVDS > > > compatible connector. However, it seems like the cheapest one is the > > > $1000 "Cyclone III FPGA Development Kit". > > > > I initially thought that the $200 "Cyclone III FPGA Starter Kit" woul= d > > > work since it has HSMC, but the manual states that it is only intende= d > > > for CMOS signals and has no provisions for differential pairs. > > > > So does there exist a board that meets my requirements that is less > > > than $500? I know Xilinx does (the Digilent Atlys, which has great > > > specs), but I'd like to develop for the Cyclone 3/4 because they > > > support DDR DIMM's while the Spartans do not. If there doesn't exist > > > such a dev board, it seems to me like there's a huge gap in their lin= e- > > > up. > > > > What I want to do is make a daughtercard board for an 11-bit ADC, at > > > 200MHz DDR. I need twelve LVDS pairs. Perhaps I could just try using > > > the starter kit board and see if the non-differential pair routing > > > will still work, but I don't want to just toss $200 away either.Article: 150292
Benjamin Couillard <benjamin.couillard@gmail.com> wrote: >On Jan 4, 3:42=A0pm, n...@puntnl.niks (Nico Coesel) wrote: >> Benjamin Couillard <benjamin.couill...@gmail.com> wrote: >> >Hi everyone, I've got a question. >> >> >Let's say I have a PLL that generates a 100 MHz clock and a 200 MHz >> >clock. The clocks are in phase, i.e. a rising edge on the 100 MHz >> >occurs at the same time as a rising edge 200 MHz clock. >> >> >. In my application I =A0want to process the data @ 200 MHz to reduce >> >filter complexity, i.e. my filters would use only half of the >> >multipliers compared to running the filters @ 100 MHz. However, the >> >effective sampling rate would remain the same i.e. 100 MHz. =A0I need to >> >obtain a data valid signal enabled 50% of the time, since there would >> >be a new data 1 cycle out of 2 on the 200 MHz clock. >> >> >I could use an asynchronous FIFO to get the data valid @ 200 MHz, but >> >I think this solution is overkill since both clocks are in phase-lock. >> >> >What would you do? I want the data valid to be enabled 50% of the >> >time, and I want the data_valid to be '1' when my 16 bits data sample >> >change. >> >> I'd use a timing constrain. If the tools know about the clocks coming >> from inside the FPGA the tools might create the timing constraints >> automatically based on the input clock. I know the XIlinx tools create >> such contraints automatically. >> -------------------------------------------------------------- > >The first thing I tried is this > > > >DATA_VAL_200M <=3D DATA_VAL_100M and CLK_100M. > >Then I use this signal as a data_valid signal for my filter core >running @ 200 MHz but with a sample rate of 100 MHz. > >It seems to work fine in synthesis i.e. Xilinx doesn't complain and >does not output a warming, however in simulation I get some >"glitches", basically I sometimes see a small red line at transitions. >I think this is related to "delta cycles" in VHDL but I could be >mistaken. You probably get some glitches due to the AND operation. If the signal meets setup and hold there is no problem. However I would implement an edge detector in the 200MHz domain. Using the clock in an equation is something Xilinx FPGAs don't like. There are few elements which allow the clock to travel from a global clock net into a routing net. You might end up using a lot of fast routing resources. AFAIK there is an appnote on that subject. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150293
> Dear my friends > actually i want to design the SRAM IP core for FPGA , i have one SRAM cell schematic and layout for different technology 90nm,.. first i need to generate benchmark for that or if find available bench mark to use this cell instead current cell then can verify my sram and then should be generate ip core for this module , i search in internet but could not find useful information to how to do that or this way is correct or not , so could you please help me even introduce the good references or the software requirement for this problem > > i looking forward your helps > > > best regardsArticle: 150294
On 1/8/2011 12:33 AM, salimbaba wrote:
> I routed the signal to an external debug pin and observed the signal on
> scope but no success. Counter being optimized away can happen, but even if
> it is getting optimized away, chipscope should trigger. It doesnt get
> triggered so, anything else ?
Have a look at your counter on the rtl viewer.
If synthesis were happening correctly,
you would have seen something on the scope.
Post the hdl code for the counter.
-- Mike Treseler
Article: 150295On Sat, 08 Jan 2011 02:33:42 -0600, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >I routed the signal to an external debug pin and observed the signal on >scope but no success. It's not clear to me whether you were able to see the incoming clock (not dcm output etc.) on the debug pin. If you're able to see the clock on the debug pin, then there is an issue with the rest of your design. Did you simulate your RTL? One way to prevent it being optimized out is to 'or' your counter output vector and send it out to the same debug pin. The simulate the design in RTL, do P&R, check timing carefully and/or simulate gate level netlist. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 150296
On Jan 7, 8:38=A0pm, "Andy \"Krazy\" Glew" <a...@SPAM.comp-arch.net> wrote: > Intel fabs are =A0often ahead of TSMC and UMC and GF. =A0But this doesn't > explain the whole difference, not by a long shot, especially given AMD's > situation. When I was at AMD and AMD still owned the Dresden FABs, we would look at the process technologies from (say) TSMC,... and find that if we dumped our chips in that FAB they woud run about 1/2 as fast. So, there is about a factor of 2X in the FAB techology. > By the way, an interesting conversation is why IBM is above 5GHz, > whereas Intel is not. The market limits Intel to 100 Watt air cooled envelope, IBM is not so limited. > =A0>> - The difference is dynamic logic/domino logic/etc. Most common > logic designs (ASICs, FPGAs, ARM processors) use static logic - a mess > of conventional CMOS gates separated by flops. High performance chips > use dynamic logic, lots of latches and similar tricks to avoid the > overhead of static logic. This idea may not stand up to scrutiny as I > understand that the latest Intel architectures (Nehalem) are fully static= . Note: excepting for RAMs and ROMs, there is almost no dynamic logic in one of the x86 manufactures products. Dynamic logic is hard and takes a lot more designers to get right (some of them in the FAB.) Dynamic logic is sensitive to the process window swings. In many cases, dynamic logic is not really faster once you consider not being able to use the logic in the other 1/2 of the clock cycle and the added skew on the falling edge of the clock. > E.g. googling "intel nehalem static cmos" > > =A0 =A0 IDF: Inside Nehalem - HotHardware > =A0 =A0 Aug 22, 2008 ... Another way Intel managed to keep the power > =A0 =A0 requirements for Nehalem relatively low (130 watts TDP) was by us= ing > =A0 =A0 static CMOS for all of the ... > =A0 =A0 hothardware.com/Articles/IDF-Inside-Nehalem/?page=3D3 > > =A0 =A0 [PDF] Intel and Core i7 (Nehalem) Dynamic Power Management > =A0 =A0 File Format: PDF/Adobe Acrobat - Quick View > =A0 =A0 hungry. To save power, Intel circuit designers decided to switch > =A0 =A0 from domino logic to static CMOS based logic circuits when > =A0 =A0 implementing Nehalem. ... > =A0 =A0 cs466.andersonje.com/public/pm.pdf - Similar A good decision based on the power envelope not letting the speed of dynamic logic to be utilized to its fullest. MtichArticle: 150297
On Jan 8, 3:33 am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > I routed the signal to an external debug pin and observed the signal on > scope but no success. Counter being optimized away can happen, but even if > it is getting optimized away, chipscope should trigger. It doesnt get > triggered so, anything else ? No, if the counter is optimized away, chipscope won't have anything to trigger on. But I would expect an error from chipscope when it tries to hook into the design and finds the signals missing. I'm a little unclear on what you are saying about the config pins. If you were using the config interface to load the device, you would drive the PROG pin low to start the configuration. The FPGA then pulls DONE low and INIT low. After some time INIT goes high. You can hold INIT low if you want to delay the start of configuration. Once INIT goes high the configuration proceeds and when complete DONE goes high. Like INIT, DONE is bidirectional and can be forced low to delay startup of the FPGA. After the device finished configuration, the INIT pin will go low if there is a CRC error in the data stream. To the best of my knowledge, when programmed through JTAG, the INIT and DONE pins still toggle normally, but the PROG pin is input only. So I would expect PROG to remain high at all times and INIT and DONE will do what they normally do, that is to go low and end up high at the end. As to your design, I suggest that you bring all of the counter bits along with the clock out to I/O pins and observe them with a scope. That will tell you much more than chipscope ever will at this stage of the game. RickArticle: 150298
In comp.arch.fpga MitchAlsup <MitchAlsup@aol.com> wrote: > On Jan 7, 8:38 pm, "Andy \"Krazy\" Glew" <a...@SPAM.comp-arch.net> > wrote: >> Intel fabs are often ahead of TSMC and UMC and GF. But this doesn't >> explain the whole difference, not by a long shot, especially given AMD's >> situation. (snip) > Note: excepting for RAMs and ROMs, there is almost no dynamic logic in > one of the x86 manufactures products. Dynamic logic is hard and takes > a lot more designers to get right (some of them in the FAB.) Dynamic > logic is sensitive to the process window swings. In many cases, > dynamic logic is not really faster once you consider not being able to > use the logic in the other 1/2 of the clock cycle and the added skew > on the falling edge of the clock. The 8080 and 8086 used dynamic logic. (Possibly only for registers.) One reason the Z80 became more popular than the 8080 was its use of static logic, and the ability to debug with a slow clock. The processors with built-in PLL can't be slow clocked, even if the logic is static. -- glenArticle: 150299
On Sat, 8 Jan 2011 22:08:03 +0000 (UTC), glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >In comp.arch.fpga MitchAlsup <MitchAlsup@aol.com> wrote: >> On Jan 7, 8:38 pm, "Andy \"Krazy\" Glew" <a...@SPAM.comp-arch.net> >> wrote: >>> Intel fabs are often ahead of TSMC and UMC and GF. But this doesn't >>> explain the whole difference, not by a long shot, especially given AMD's >>> situation. >(snip) > >> Note: excepting for RAMs and ROMs, there is almost no dynamic logic in >> one of the x86 manufactures products. Dynamic logic is hard and takes >> a lot more designers to get right (some of them in the FAB.) Dynamic >> logic is sensitive to the process window swings. In many cases, >> dynamic logic is not really faster once you consider not being able to >> use the logic in the other 1/2 of the clock cycle and the added skew >> on the falling edge of the clock. > >The 8080 and 8086 used dynamic logic. (Possibly only for registers.) > >One reason the Z80 became more popular than the 8080 was its use >of static logic, and the ability to debug with a slow clock. > >The processors with built-in PLL can't be slow clocked, even if >the logic is static. What if the PLL is programmable and can be told to generate a slow clock? -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
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