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1) Why the spec calls out negative number for input holding time ? eg. TphDCM = - 0.26 ns 2) What does that means when they say "When the hold time is negative, it is possible to change the data before the clock's active edge" ---------------------------------------------------------- What I read out from the above is that, the device does not require the hold time at all ...Am I correct or...?Article: 152101
On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote: > 1) Why the spec calls out negative number for input holding time ? eg. > TphDCM = - 0.26 ns > > 2) What does that means when they say > > "When the hold time is negative, it is possible to change the data > before the clock's active edge" > > ---------------------------------------------------------- > > What I read out from the above is that, the device does not require the > hold time at all ...Am I correct or...? It means that the data can change no more than 0.26ns before the clock edge -- and that means that the data must be _valid_ at that point, not already meandering across the thresholds. It _doesn't_ mean that there's no hold time requirement at all -- just that the hold time requirement is a bit weird. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 152102
Well i selected the Verilog thing and it generated user_logic in Verilog.
But now what i want to write to one register and read after adding a
constant value to it. (I have used to registers).
What do i do with the sample code. Should i delete or modify it. But How
kindly guide.
i can post the code if it helps:
//----------------------------------------------------------------------------
// user_logic.v - module
//----------------------------------------------------------------------------
//
//
***************************************************************************
// ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
**
// **
**
// ** Xilinx, Inc.
**
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
**
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
**
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
**
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
**
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
**
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
**
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
**
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
**
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
**
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
**
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
**
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
**
// ** FOR A PARTICULAR PURPOSE.
**
// **
**
//
***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.v
// Version: 1.00.a
// Description: User logic module.
// Date: Wed Jul 06 11:20:21 2011 (by Create and Import
Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
Bus2IP_RdCE, // Bus to IP read chip enable
Bus2IP_WrCE, // Bus to IP write chip enable
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer
acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer
acknowledgement
IP2Bus_Error // IP to Bus error response
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 2;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_REG-1] Bus2IP_RdCE;
input [0 : C_NUM_REG-1] Bus2IP_WrCE;
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg0;
reg [0 : C_SLV_DWIDTH-1] slv_reg1;
wire [0 : 1] slv_reg_write_sel;
wire [0 : 1] slv_reg_read_sel;
reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// --USER logic implementation added here
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible
registers
//
// Note:
// The example code presented here is to show you one way of
reading/writing
// software accessible registers implemented in the user logic slave
model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
// to one software accessible register by the top level template. For
example,
// if you have four 32 bit software accessible registers in the user
logic,
// you are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_sel = Bus2IP_WrCE[0:1],
slv_reg_read_sel = Bus2IP_RdCE[0:1],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
end
else
case ( slv_reg_write_sel )
2'b10 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1;
byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <=
byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
2'b01 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1;
byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <=
byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_sel )
2'b10 : slv_ip2bus_data <= slv_reg0;
2'b01 : slv_ip2bus_data <= slv_reg1;
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_WrAck = slv_write_ack;
assign IP2Bus_RdAck = slv_read_ack;
assign IP2Bus_Error = 0;
endmodule
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 152103To help us keep accurate statistics, are you a lazy student or a clueless would-be hobbyist? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152104
You need to first understand how the IPIF works. You can't just expect someone to learn it for you. Once you have the knowledge then it is simple to write your code in Verilog or VHDL. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152105
>To help us keep accurate statistics, are you a lazy student or a clueless >would-be hobbyist? > > >--------------------------------------- >Posted through http://www.FPGARelated.com > Neither a lazy student nor a hobbyist I am a student. It is easier to critique than to help some one. It was a easy question. I have not asked you to write down a code for me just asked "Will I be requiring the sample code or can i replace it with my own like in Usual verilog codes". I want really appreciate some help here. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152106
Thank you Jon i will read about the IPIF for both PLB/OPB which ever i can use.If i face any problem i will ask. Thanks again --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152107
For our 5Gsps PCIe Digitizers we use a Virtex-5 to read ADC-Data at 1.25Gbps per pin. We can see that we still have a few hundred ps of sampling window, so 1.5Gbps probably would work as well. Virtex-6 or Virtex-6 should be able to do higher rates. See xapp860.pdf and xapp855.pdf for more. Kolja Sulimma cronologic On Jun 30, 12:43=A0pm, "jgk2004" <john.kauffman@n_o_s_p_a_m.n_o_s_p_a_m.uni-ulm.de> wrote: > When you say that LVDS on the virtex 5 could easily be handled at 250MHz > would I then need a core clock at above 250MHz? =A0Also what is hte max L= VDS > could be used on the virtex 5 without the rocket IOs? Can i use LVDS at > 1GHz?Article: 152108
On Jul 7, 12:11=A0am, Tim <t...@seemywebsite.please> wrote: > On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote: > > 1) Why the spec calls out negative number for input holding time ? eg. > > TphDCM =3D - 0.26 ns > > > 2) What does that means when they say > > > "When the hold time is negative, it is possible to change the data > > before the clock's active edge" > > > =A0---------------------------------------------------------- > > > What I read out from the above is that, the device does not require the > > hold time at all ...Am I correct or...? > > It means that the data can change no more than 0.26ns before the clock > edge -- and that means that the data must be _valid_ at that point, not > already meandering across the thresholds. =A0It _doesn't_ mean that there= 's > no hold time requirement at all -- just that the hold time requirement is > a bit weird. > > -- > Tim Wescott > Control system and signal processing consultingwww.wescottdesign.com But then, that sounds very the same as the traditional setup time ??? Now its really weird & confuse. We have now two names to describe the same thing? and the same paper calls out 2 different numbers for the same thing hmmm ???Article: 152109
On Thu, 07 Jul 2011 10:18:00 -0700, Mawa_fugo wrote: > On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote: >> On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote: >> > 1) Why the spec calls out negative number for input holding time ? >> > eg. TphDCM = - 0.26 ns >> >> > 2) What does that means when they say >> >> > "When the hold time is negative, it is possible to change the data >> > before the clock's active edge" >> >> > ---------------------------------------------------------- >> >> > What I read out from the above is that, the device does not require >> > the hold time at all ...Am I correct or...? >> >> It means that the data can change no more than 0.26ns before the clock >> edge -- and that means that the data must be _valid_ at that point, not >> already meandering across the thresholds. It _doesn't_ mean that >> there's no hold time requirement at all -- just that the hold time >> requirement is a bit weird. >> >> -- >> Tim Wescott >> Control system and signal processing consultingwww.wescottdesign.com > > But then, that sounds very the same as the traditional setup time ??? No. You may change the data before, but not after, the setup time. You may change the data after the hold time, but not before it (i.e. not between the setup and hold time). A small negative hold time can result from a delay internal to the FF on the data input, which is greater than any similar delay on the clock input. There will be a window before this hold time (but after the setup time) during which you cannot change the data. SO if the hold time is -0.25ns, there will be a setup time of greater than 0.25ns, (e.g. 0.5ns) and a window between 0.5 and 0.25ns before the clock edge when the data must be stable. This can be a deliberate design feature to guarantee that pipelines will avoid races in the presence of small amounts of clock skew, without having to specify minimum routing delays between pipe stages. (Timing analysis will still have to guarantee maximum delays, for a particular clock frequency) - BrianArticle: 152110
Mawa_fugo wrote: > On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote: >> On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote: >>> 1) Why the spec calls out negative number for input holding time ? eg. >>> TphDCM = - 0.26 ns >>> 2) What does that means when they say >>> "When the hold time is negative, it is possible to change the data >>> before the clock's active edge" >>> ---------------------------------------------------------- >>> What I read out from the above is that, the device does not require the >>> hold time at all ...Am I correct or...? >> It means that the data can change no more than 0.26ns before the clock >> edge -- and that means that the data must be _valid_ at that point, not >> already meandering across the thresholds. It _doesn't_ mean that there's >> no hold time requirement at all -- just that the hold time requirement is >> a bit weird. >> >> -- >> Tim Wescott >> Control system and signal processing consultingwww.wescottdesign.com > > But then, that sounds very the same as the traditional setup time ??? > > Now its really weird & confuse. We have now two names to describe > the same thing? and the same paper calls out 2 different numbers for > the same thing > > hmmm > ??? > > > > > To be a little clearer, hold time is different from setup in that it defines the end of the data sampling window, while set defines the start of the window. What Tim meant by "no more than 0.26ns before the clock" is that the end of the valid window must not come *sooner* than 0.26 ns before the clock. So if the data is stable until 0.26 ns before the clock and *then* starts to change, you will sample the data in its stable state. Negative numbers are a little perplexing because the definition of setup and hold are referenced in a different direction, based on the outdated assumption that a flip-flop's sampling window includes the clock edge. So for that case both setup and hold would be positive. For FPGA's, the actual data sampling window of a filp-flop is tiny, and the bulk of the setup and hold requirements are due to the delays in routing the signal and clock to the flip-flop's D and CLK inputs. Since either the clock or the data signal can have a longer routing delay, it's quite easy to end up with either negative set or negative hold times. So think of it this way: The clock arrives at time T. Data must be stable from time (T - setup) until time (T + hold). If setup is positive and hold is negative, then the stable window will be entirely before the clock edge: CLK --------T----------- Data xx<===>xxxxxxxxxxxxx If hold is positive and setup is negative, the stable window will be entirely after the clock edge. CLK --------T----------- Data xxxxxxxxxxxx<===>xxx If both setup and hold are positive, then the stable window includes the clock edge. CLK --------T----------- Data xxxxxx<===>xxxxxxxxx HTH, GaborArticle: 152111
On 07/07/2011 02:40 PM, Gabor wrote: > > > Mawa_fugo wrote: >> On Jul 7, 12:11 am, Tim <t...@seemywebsite.please> wrote: >>> On Wed, 06 Jul 2011 08:13:52 -0700, Mawa_fugo wrote: >>>> 1) Why the spec calls out negative number for input holding time ? eg. >>>> TphDCM = - 0.26 ns >>>> 2) What does that means when they say >>>> "When the hold time is negative, it is possible to change the data >>>> before the clock's active edge" >>>> ---------------------------------------------------------- >>>> What I read out from the above is that, the device does not require the >>>> hold time at all ...Am I correct or...? >>> It means that the data can change no more than 0.26ns before the clock >>> edge -- and that means that the data must be _valid_ at that point, not >>> already meandering across the thresholds. It _doesn't_ mean that there's >>> no hold time requirement at all -- just that the hold time >>> requirement is >>> a bit weird. >>> >>> -- >>> Tim Wescott >>> Control system and signal processing consultingwww.wescottdesign.com >> >> But then, that sounds very the same as the traditional setup time ??? >> >> Now its really weird & confuse. We have now two names to describe >> the same thing? and the same paper calls out 2 different numbers for >> the same thing >> >> hmmm >> ??? >> >> >> >> >> > To be a little clearer, hold time is different from setup in that it > defines the end of the data sampling window, while set defines the > start of the window. What Tim meant by "no more than 0.26ns before > the clock" is that the end of the valid window must not come *sooner* > than 0.26 ns before the clock. So if the data is stable until 0.26 > ns before the clock and *then* starts to change, you will sample the > data in its stable state. > > Negative numbers are a little perplexing because the definition of > setup and hold are referenced in a different direction, based on > the outdated assumption that a flip-flop's sampling window includes > the clock edge. So for that case both setup and hold would be positive. > For FPGA's, the actual data sampling window of a filp-flop is tiny, > and the bulk of the setup and hold requirements are due to the > delays in routing the signal and clock to the flip-flop's D > and CLK inputs. Since either the clock or the data signal can > have a longer routing delay, it's quite easy to end up with > either negative set or negative hold times. > > So think of it this way: > > The clock arrives at time T. > Data must be stable from time (T - setup) until time (T + hold). > If setup is positive and hold is negative, then the stable window > will be entirely before the clock edge: > CLK --------T----------- > Data xx<===>xxxxxxxxxxxxx > If hold is positive and setup is negative, the stable window will > be entirely after the clock edge. > CLK --------T----------- > Data xxxxxxxxxxxx<===>xxx > If both setup and hold are positive, then the stable window includes > the clock edge. > CLK --------T----------- > Data xxxxxx<===>xxxxxxxxx Now, a chip that had both setup and hold times that were negative -- that would be astounding. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152112
>On 07/07/2011 02:40 PM, Gabor wrote: >> > >Now, a chip that had both setup and hold times that were negative -- >that would be astounding. > >-- Kind of like precognitive sram. You get the data before you give it the address. I've used asic libraries that were "0-Hold" time and all they do is tweak the timing with more delay in the D path than the C path. It's nice in that you don't have to fix hold times but most paths will have enough delay that a hold time fix is not needed. You then have to deal with the loss of setup time that affects all flops and this makes it harder to meet timing. John --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152113
On Jul 8, 9:21=A0am, "jt_eaton" <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > >On 07/07/2011 02:40 PM, Gabor wrote: > > >Now, a chip that had both setup and hold times that were negative -- > >that would be astounding. > > >-- > > Kind of like precognitive sram. You get the data before you give it the > address. > > I've used asic libraries that were "0-Hold" time and all they do is tweak > the > timing with more delay in the D path than the C path. It's nice in that y= ou > don't have to fix hold times but most paths will have enough delay that a > hold time fix is not needed. You then have to deal with the loss of setup > time that affects all flops and this makes it harder to meet timing. > > John =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Sounds like everybody knows this but me... but now I think I can joint the group Thank you all very much, all the sudden I'm enlightenment, but please correct me if I'm still in darkness :-))) This "negative hold time" (new to me) or whatever quantity, and the setup time the two points will define a time window, in which data can't be changed !Article: 152114
On Jul 8, 10:46=A0am, Mawa_fugo <cco...@netscape.net> wrote: > On Jul 8, 9:21=A0am, "jt_eaton" > > > > <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: > > >On 07/07/2011 02:40 PM, Gabor wrote: > > > >Now, a chip that had both setup and hold times that were negative -- > > >that would be astounding. > > > >-- > > > Kind of like precognitive sram. You get the data before you give it the > > address. > > > I've used asic libraries that were "0-Hold" time and all they do is twe= ak > > the > > timing with more delay in the D path than the C path. It's nice in that= you > > don't have to fix hold times but most paths will have enough delay that= a > > hold time fix is not needed. You then have to deal with the loss of set= up > > time that affects all flops and this makes it harder to meet timing. > > > John =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > Sounds like everybody knows this but me... but now I think I can joint > the group > Thank you all very much, all the sudden I'm enlightenment, but please > correct me if I'm still in darkness :-))) > > This "negative hold time" (new to me) or whatever quantity, and the > setup time the two points will define a time window, in which data > can't be changed ! But the concept "you get the data before you give the memory the address" is - not in my imaginationArticle: 152115
Hello, all, I am trying to make a counter follow the value of a value sent from another device. The value coming in is a bidirectional counter that can rollover in either direction. The value is sampled so it is not necessarily monotonic, but should not change greatly between samples. I want to either increment or decrement the counter in my VHDL module so it tracks the value coming in, and it always needs to go the "shortest" way around the counter. I got it working on the rollover from -1 to 0 both ways, but then was confounded that it went the "wrong way" at the half-rollover, from 011111 to 100000, for instance. It seems like there must be a proper way to treat this so it can be done with a simple less-than or greater-than comparison, without having to compare the high two bits with a bunch of special case ors. Anybody know what I'm mising here? Thanks much, JonArticle: 152116
On 07/08/2011 08:51 AM, Mawa_fugo wrote: > On Jul 8, 10:46 am, Mawa_fugo<cco...@netscape.net> wrote: >> On Jul 8, 9:21 am, "jt_eaton" >> >> >> >> <z3qmtr45@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >>>> On 07/07/2011 02:40 PM, Gabor wrote: >> >>>> Now, a chip that had both setup and hold times that were negative -- >>>> that would be astounding. >> >>>> -- >> >>> Kind of like precognitive sram. You get the data before you give it the >>> address. >> >>> I've used asic libraries that were "0-Hold" time and all they do is tweak >>> the >>> timing with more delay in the D path than the C path. It's nice in that you >>> don't have to fix hold times but most paths will have enough delay that a >>> hold time fix is not needed. You then have to deal with the loss of setup >>> time that affects all flops and this makes it harder to meet timing. >> >>> John >> >>> --------------------------------------- >>> Posted throughhttp://www.FPGARelated.com >> >> Sounds like everybody knows this but me... but now I think I can joint >> the group >> Thank you all very much, all the sudden I'm enlightenment, but please >> correct me if I'm still in darkness :-))) >> >> This "negative hold time" (new to me) or whatever quantity, and the >> setup time the two points will define a time window, in which data >> can't be changed ! Correct. > But the concept "you get the data before you give the memory the > address" is - not in my imagination It's a joke. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152117
On Sat, 09 Jul 2011 22:20:35 -0500, Jon Elson wrote: > Hello, all, > > I am trying to make a counter follow the value of a value sent from > another device. The value coming in is a bidirectional counter that can > rollover in either direction. The value is sampled so it is not > necessarily monotonic, but should not change greatly between samples. > > I want to either increment or decrement the counter in my VHDL module so > it tracks the value coming in, and it always needs to go the "shortest" > way around the counter. I got it working on the rollover from -1 to 0 > both ways, but then was confounded that it went the "wrong way" at the > half-rollover, from 011111 to 100000, for instance. > > It seems like there must be a proper way to treat this so it can be done > with a simple less-than or greater-than comparison, without having to > compare the high two bits with a bunch of special case ors. > > Anybody know what I'm missing here? Can you use up an adder? If so it's as simple as c = a - b. If you take c as 2's compliment, then the magnitude of c is the amount that you need to change a so that it matches b; the sign of c is the direction. It will automagically be the shortest distance when interpreted in this manner. -- Tim Wescott Control system and signal processing consulting www.wescottdesign.comArticle: 152118
On Jul 10, 3:20=A0pm, Jon Elson <el...@pico-systems.com> wrote: > It seems like there must be a proper way to treat this so it can be done > with a simple less-than or greater-than comparison, without having to > compare the high two bits with a bunch of special case ors. I'm not sure a single comparison will do, as the subset if what you want is if A > B then inc(B) elseif A < B then dec(B) but you are also asking for a 'shortest path' test, which adds another test, to decide which way is closer : the maths way, or the wrap-way. and I think that is 4 branches, no matter how you code it ?Article: 152119
Jim Granville wrote: > On Jul 10, 3:20 pm, Jon Elson <el...@pico-systems.com> wrote: >> It seems like there must be a proper way to treat this so it can be done >> with a simple less-than or greater-than comparison, without having to >> compare the high two bits with a bunch of special case ors. > > I'm not sure a single comparison will do, as the subset if what you > want is > if A > B then inc(B) elseif A < B then dec(B) > but you are also asking for a 'shortest path' test, which adds another > test, to decide which way is closer : the maths way, or the wrap-way. > and I think that is 4 branches, no matter how you code it ? Yes, of course, you need the count up test and the count down test, so as to accommodate the case where the input did not change. Right now I have 6 tests (a pair of 3-way ors depending on the state of the upper two bits of input and counter) and I'm not sure this is covering all cases. I think my main problem was making the input and counter signed. This takes care of the rollover between -1 and zero both ways work fine, but totally messes up the overflow between largest negative number and largest positive. Changing to unsigned should help, but I still have to come up with a test for when the < or > comparison give the wrong result. Thanks, Tim and Jim! JonArticle: 152120
>If you are using a memory port on the microprocessor, then there will be >a timing diagram in the microprocessor data sheet that details its >operation. Take that timing diagram and copy it out, then finish it >with the pertinent internal signals of the FPGA. Calculate where all >the edges may land (remember that if you're clocking the port from a >50MHz clock that's asynchronous to the micro that you have to treat the >FPGA clock edges as being uncertain to +/- 10us). > >If you are bit-banging the exchange, and you have the pins available, >then the timing diagram is your responsibility -- but you should still >draw it out; in particular you should make sure that the read and write >pulses out of the micro are long enough that the FPGA reliably catches >the edges. > >-- > >Tim Wescott >Wescott Design Services >http://www.wescottdesign.com > >Do you need to implement control loops in software? >"Applied Control Theory for Embedded Systems" was written for you. >See details at http://www.wescottdesign.com/actfes/actfes.html > If i would be restricted to a memory interface the problem would have a direct solution.. but as the uC is not fixed i cannot ensure the existence of a memory interface. I did try to create a bit-banged the communtication (i did run a test on a PIC32 that i had here on my hand, but i am expecting to use some Texas DSC on the final version to run the tests) but i could not get a real good communication speed, nothing close to the 40Mbps of the SPI, so created a simple SPI interface on the FPGA and it is working quite well. Thank you for the help. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152121
Jon Elson wrote: Well, I changed it over to unsigned, but I still ended up with more or clauses than I think should be needed. Anyway, it seems to be working correctly now. Thanks, JonArticle: 152122
Hi everyone i'm pleased to announce that after two years (and about 2000 man- hours), the HercuLeS high-level synthesis tool is ready for non- trivial work. HercuLeS allows you to synthesize ANSI C code (certain rules apply) to RTL VHDL. HercuLeS is named after the homonymous constellation and not after the demigod. You can find information on HercuLeS here: http://www.nkavvadias.com/hercules/index.html Some of its features: 1. Integer and fixed-point (VHDL-2008) arithmetic of arbitrary lengths 2. It is able to synthesize VHDL from code spanning across several C functions 3. Support for both the Synopsys "de-facto standard" libraries and the official IEEE standard libraries 4. Support of synchronous read ROM and RAM memories (directly mapped to FPGA block RAMs) 5. Functions can pass single-dimensional array arguments 6. Support of streaming outputs (producing a sample at a time) You can either code your input in ANSI C or in a bit-accurate typed- assembly language called NAC (N-Address Code). Then, your input is converted to a series of CDFGs (Control/Data Flow Graphs), expressed as Graphviz graphs with user-defined attributes, which again are translated to VHDL code adhering to the FSMD (Finite-State Machine with Datapath) paradigm. I would appreciate if you had a look at the sample files available at the website. They illustrate complete examples of automatically synthesized algorithms such as Bresenham's line drawing algorithm, and the Sieve of Eratosthenes. Overall, eight complete examples can be found at the HercuLeS website. There will be regular updates on the HercuLeS webpage (every 1-1.5 months). The October update, scheduled for 2011/10/11, will allow access to HercuLeS via a web interface! But first I would appreciate feedback on whatever related to the HercuLeS webpage. Best regards, Nikolaos Kavvadias Lecturer, Research Scientist, Hardware developer, Ph.D., M.Sc., B.Sc.Article: 152123
On 07/10/2011 03:22 PM, Jon Elson wrote: > Jon Elson wrote: > > Well, I changed it over to unsigned, but I still ended up with > more or clauses than I think should be needed. Anyway, it seems > to be working correctly now. 2's compliment or unsigned binary is going to behave the same way as far as finding the shortest path. Doing the c = a-b subtraction on the top two (or three) bits will certainly use less logic -- I'm sort of a permanent FPGA Rip Van Winkle, so I don't know if you could to the 3-bit version in a pair of LUTs -- but you certainly could with the 2-bit version, particularly since you only care about the sign bit and equality. If your synthesizer is at all good with optimization, you should be able to just do the c = a-b with two (or three) bit data, and have the right answer pop out. If not, take the truth table below, and have fun with it. a b up equal --- --- --- --- 00 00 x 1 00 01 1 0 00 11 0 0 00 10 x x (indeterminate case) 01 10 1 0 01 11 x x " " 01 01 x 1 01 00 0 0 11 00 1 0 11 01 x x " " 11 11 x 1 11 10 0 0 10 10 x 1 10 11 1 0 10 01 0 0 10 00 x x " " -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Do you need to implement control loops in software? "Applied Control Theory for Embedded Systems" was written for you. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 152124
Is the limitation to *non-programmable* hardware merely a technical limitation, or is it a license restriction? For example, could one use it to design a microprocessor by simply excluding the RAM from the C program, and then adding a bit of hand- written RTL VHDL to the output to add in the programmability? John Savard
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