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On Jun 21, 4:04=A0pm, jc <jcappe...@optimal-design.com> wrote: > On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote: > > > > > > > > > > > Hello all, > > > I struggle with an issue I can't understand the root cause. > > > When simulating my back annoted design with modelsim, I get unexpected > > behavior when using a simulation step of 1ns, but no errors when using > > a step of 1ps. > > > My design is running at 1MHz (so I expect a simulation step of 1ns to > > be highly sufficient). > > The part that is causing trouble is a wrapper around an SRAM instance > > (it is an actel RAM512x18 component on an actel proasic3 FPGA). > > > I've got the exact same component instanciated in the exact same > > wrapper simulating fine on an actel igloo FPGA. I am aware that place > > and route may have produce significantly different results between the > > two FPGAs and that having the design running smoothly on one FPGA > > don't prove anything. > > > Still I can't figure out why modelsim would not simulate identically > > using a 1ns or 1ps step. > > > Last but not least, I've got no warning from modelsim (no glitch > > found). > > > If any of you have an idea of what could be happening there I would be > > glad to ear it. > > > Regards > > I don't see evidence that this is your problem, but a classic "back- > annotated sim time resolution problem" that often arises is the mixing > of your testbench environment made up only of idealistic delays (i.e. > delays are only based on the temporal ordering assignments made by > your simulator) with your back-annotated "real world" worst case > delays. For instance, if you attempt to clock a signal from a simple > clocked assignment statement into a back-annotated reg with a real > setup time assigned to it, it will always be one cycle behind. A > typical fix for this is to add an artificial delay to your testbench > assignment statements that interact directly with the back-annotated > code to satisfy the setup times. > - John should probably use correct timescale directives. Thanks ShyamArticle: 152001
I have designed a 32 bit counter but I am having a difficulty in assigning 32 pins to the 32 bits since I don't know the "LOC" (location) of the pins which is required in the User Constraints file. I need help. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152002
I had been working with Xilinx ISE 12.4 for a while trying to improve the performance of a SPARC based processor. Till now, I was always and stopping at the "Synthesize - XST" step. I found that going into the "Process Properties" -> "Xilinx Specific Options" for the synthesis process and reducing Max Fanout from 500, down to between 40-16 got me timing closure with not too much additional area. Which is nice. Now, I need to generate a bitfile and therefore need a proper Xilinx license. Unfortunately, I have access only to a license for ISE 11 (from my university). So, I installed 11.1, set the max fanout the same way as earlier, and re ran XST. I now find that this max fanout is ignored (lots of FFs with fanouts > 100 and correspondingly large delays) and this causes timing requirements to not be met. I googled around, and found a couple of suggestions: 1. Switch off "Resource Sharing" under "HDL Options" 2. Switch off "Equivalent Register Removal" under "Xilinx Specific Options" 3. Make sure "Register Duplication" is on (which it always was) At least #2 seemed to make sense because I felt that equivalent register removal conflicts with the goal of max fanout. So I did all this. => Still, max fanout seems to be ignored. I have also looked at the Xilinx Constraints Guide and it does not clearly tell when global max fanout is ignored. In fact it goes into detail explaining an example where a module specific max fanout (defined in the xcf file) is ignored, but it says nothing about global max fanout. It does say that really low values are not always followed. But a fanout of 100 where the max defined as 16 seems a bit too much. So why does this happen? There is no difference between the sources I used for 12.4 and am now using for 11.1. More importantly, how can I fix this? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152003
I want to add a custom verilog core to an already established pipeline of microblaze. The core should be able to read data from memory locations from DDR RAM (external) which is already present on PLB, process it i.e add to value of data and replace the data it has read with the new processed data. In short i want to add certain constant number to data on RAM in a parallel fashion,(video frame) and write back to those very locations. Please guide me how should i go about. Should i create a custom peripheral? Should i use FSL? As i am new in this field kindly guide me! Thank You I am using Xilinx Spartan3E 1600. With ISE and XPS 10.1 sp1 --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152004
Hi, I want to using ChipScope Pro Analyzer to check my design. I have already generated the icon and ila cores and connected them with my design. But I am stumbled with how to open the interface GUI of ChipScope on linux. Dose it have interface GUI on linux? If it has, what`s the commands to open it? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152005
On Jun 18, 11:31=A0am, Simon <goo...@gornall.net> wrote:
> On Jun 17, 7:33=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > On Jun 16, 2:38=A0pm, Gabor <ga...@szakacs.invalid> wrote:
>
> > > Simon wrote:
> > > > Hopefully not sparking any religious wars here, but hoping for some
> > > > advice from those-who-know :)
>
> > > > I switched to using Altera's software a couple of years ago, becaus=
e
> > > > it felt more intuitive to me - probably a personal thing, but it ju=
st
> > > > grocked better; however, I was browsing the xilinx site just recent=
ly,
> > > > idly wondering if the -7 series that I'd heard so much about had
> > > > actually arrived yet (big surprise, it's still vapour-ware to the
> > > > likes of me), and I saw the SP605 evaluation kit had dropped to $69=
5.
>
> > > > This seems to be a really great deal. You get a nice high-bandwidth=
-
> > > > memory card, with a PCI-e interface, and high-speed external
> > > > connections (ok, only 68/34 pins, but still), as well as a full (ev=
en
> > > > if device-locked) ISE license for both the EDK and ISE. My innate
> > > > cynicism asks "what's the catch ?"
>
> > > > So, I thought I'd access the wisdom of crowds ([grin] on the first
> > > > pass, that read: wisdom of crows :) and ask:
>
> > > > =A0- Do you actually get a real, useful, not time-limited or anythi=
ng
> > > > like that PCIe core ?
> > > > =A0- Ditto for the DDR memory core ?
> > > > =A0- Ditto for the Microblaze core ?
> > > > =A0- Does "lite" mean the ethernet-lite core "only' does 10/100 rat=
her
> > > > than 10/100/1000 ?
>
> > > > It seems to suggest in the docs that the answers to the above are
> > > > {yes, yes, yes, yes}, but that seems too good to be true. Over in
> > > > Altera-land I'd be paying $500 for the nios2 license, and $1000 for
> > > > the memory/ethernet cores, both on top of a board-cost... I'm halfw=
ay
> > > > through a project that uses a nios2 qsys-based system, and for the =
~
> > > > $1000 difference, I'm happy to port it back to Xilinx (this is a
> > > > hobby, the cost/benefit analysis is different to most people's on h=
ere
> > > > - y'all don't have the 'WAF' (wife-approval factor) to consider, an=
d
> > > > WAF trumps pretty much all :)
>
> > > > I understand that if I ever wanted to target something other than a=
n
> > > > LX45T I'd have to re-purchase the software. Does that apply to the =
EDK
> > > > as well as ISE ? Or could I use the EDK that comes with the kit in
> > > > tandem with WebPack to target a smaller device ?
>
> > > > Cheers
>
> > > > Simon
>
> > > Xilinx has a new approach to supplying software with demo boards. =A0=
Read
> > > the fine print with your board, but generally what you get is a licen=
se
> > > to use the full EDK (Microblaze development software), which is
> > > otherwise quite expensive. =A0This license is good for one computer
> > > (node-locked) *and* also locked to the particular Xilinx device on yo=
ur
> > > demo board.
>
> > > There's nothing to stop you from using it on your own hardware, provi=
ded
> > > you choose the same chip. =A0Any other cores provided are also licens=
ed
> > > for use on that particular chip. =A0I'm not familiar enough with Spar=
tan
> > > 6 to know if you would normally pay for the PCIe license, but on the
> > > Virtex 5 parts that have a built-in PCIe endpoint block the "wrapper"
> > > core is free. =A0Ditto for the ethernet MAC block wrappers. =A0The Et=
hernet
> > > TriMode soft MAC is not free.
>
> > > For very simple MicroBlaze-based designs there is a "simple MicroBlaz=
e"
> > > pre-built core available at no charge, with very limited connectivity=
.
> > > You can use this wih the SDK without the need for the EDK. =A0However
> > > as soon as you want to build a processor with external memory and/or
> > > network connectivity you need to pony up for the EDK.
>
> > > As far as I know, all of the Xilinx licenses are not time limited for
> > > use, but do have a time limit for maintenance (includes upgrades to
> > > the latest version - not always a blessing). =A0The renewal fee for
> > > maintenance is almost the same as a new license. =A0You also get
> > > webcase support while under maintenance. =A0After that you're back to
> > > trolling forums with the students.
>
> > > -- Gabor- Hide quoted text -
>
> > > - Show quoted text -
> > > I'm not familiar enough with Spartan 6 to know if you would normally
> > > pay for the PCIe license, but on the Virtex 5 parts that have a built=
-in
> > > PCIe endpoint block the "wrapper" core is free
>
> > Spartan-6 devices also include an integrated PCIe block so there is no
> > extra license cost.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> Thanks Ed, (and everyone else). Looks like I'll be getting one of the
> embedded kits then. Everyone wins, because as soon as I actually pay
> for it, the Zynq or -7 series will immediately be available... That's
> just the way it goes :)
>
> Cheers
> =A0 =A0Simon- Hide quoted text -
>
> - Show quoted text -
Simon and all, not available at the moment but hopefully soon is a
family of boards my company is working on that may help avoid the
old... "That's just the way it goes". The concept provides virtual
pin-compatibility between FPGAs so one can switch between Xilinx,
Altera, or others, as well as upgrade to their newer technologies when
available. Bascially, a main board will have all the bells and
whistles you'd find on most full featured dev boards (ie., HDMI, USB,
UART, etc), but a high density/performance 'socket' for an FPGA
specific daughter card.
On the down-side there will be some degradation to the FPGA's
performance, IO count, and a few features due to the connectorization
but surprisingly not much. On the up-side, one can get much more
milleage out of a full-featured main board that's not tied to a
particular FPGA technology. The cost will be more if compared to an
existing eval board (at least till volumes grow) but the extra value
comes from the flexibility that makes our family of boards a better
investment. There are other benefits such as 'bake-off' benchmarking
and even choosing to use the FPGA daughter cards in production
(thereby designing in the same flexibility to a customer's end
product). This gets a little disruptive and may be another step
toward commoditizing FPGAs but, ... "that's just the way it goes :)"
There're usually many detailed questions but in general, does this
sound like something of interest. Any feedback would be appreciated.
Thanks,
Tom
Article: 152006On Jun 21, 4:56=A0am, "moudud" <hi.maddy08@n_o_s_p_a_m.gmail.com> wrote: > I have designed a 32 bit counter but I am having a difficulty in assignin= g > 32 pins to the 32 bits since I don't know the "LOC" (location) of the pin= s > which is required in the User Constraints file. > I need help. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Take a look at your board schematic for the pin locations. Ed McGettigan -- Xilinx Inc.Article: 152007
On Jun 20, 12:50=A0pm, "scrts" <mailsoc@[remove@here]gmail.com> wrote: > Maybe You're interested in other manufacturers? E.g. Lattice offers ECP3 > FPGA devkit with transceivers and PCI-e connection, plus 1Gb DDR3 memory = and > two gigabit network transceivers for 99$.http://www.latticesemi.com/produ= cts/developmenthardware/developmentki... I did see that too, and yes, it's really tempting (for me, it'd be ~ $300 for the board + IP modules I'd want - PCIe + network), but there's a couple of problems: - It's not clear that the mico32 processor (which appears to be free, itself) will support DDR3 - it only claims support for DDR/DDR2 on the web-page - The license only runs for a year, and I don't know how aggressively Lattice enforces that. It looks as though you really can't make any new projects after that first year. - Once this years license expires, the IP will probably cost $995/ year thereafter, unless the promotion is still running a year later, which seems unlikely. I'm not really too worried about the first of these - I'd expect Lattice to support their boards. The second and third are a concern though. For most people on here, a year's license is fine. You'll all be upgrading hardware/software sufficiently often for business reasons that it's really not an issue. For hobbyists like me though, splashing the cash happens only once every 2 or 3 years - it's just too expensive otherwise. Xilinx seems to have a more-friendly-to-the- hobbyist approach - from reading their licensing faq: "License expiration for Xilinx software and IP licenses is as follows: - WebPACK, purchased SW and purchased IP licenses never expire, but only enable the set of software and IP versions released before or during your warranty period. - Evaluation and trial licenses for software expire 30 days from the day they were generated. - Hardware evaluation IP license key expiration is four months starting in 11.1 - LogiCORE IP licenses which require no fee do not expire and full LogiCORE IP licenses which you purchase do not expire. However, full license keys only enable versions of the IP core released during or prior to your 1-year warranty period. To access new IP versions and associated enhancements and bug fixes after your initial 1-year warranty period expires, you must renew your support contract annually. " So, according to that, and assuming the board/sw falls into the first category, I get to keep *using* what I've bought until I buy something new. I just run out of maintenance after the year. Over the 2 or 3 years this board will have to last for, that makes the '605 the better purchase, even if it's more up-front. Simon.Article: 152008
are u using a custom board or some starter kit ? If u are using a starter kit, which i am assuming u will be using, look at the starter kit manual. It contains the UCF for different IOs. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152009
On May 20, 4:17=A0am, "tandt_53" <dothetan.040490@n_o_s_p_a_m.gmail.com> wrote: > hi all! > I'm working on the Spartan 3E started with mapping MJPEG decoder. I had t= he > source code of the JPEG deccoding, now I use AVI container to display MJP= EG > via VGA port. I wanna find the first image inside of AVI container but I > don't understand the AVI's structure. it has some index such as super > index, old index, ect. And I don't know how to display video into monitor > via VGA port. any body has idea for my problems? Please, help me! > thanks alot! > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com I was acutally doign somethign similar not too long ago. I was receiving video into an FPGA and trying to write out to and SDXC card in AVI format. I didn't finish this, got pulled into something else. But after hours I figured out AVI is formatted and wrote a C program to pull out the data. If you get your code please email it me to sk3ptic@gmail.com. Below are the links I used to figure it out. http://www.jmcgowan.com/avitech.html http://www.tomkv.com/what-is-avi-format.html Basically a typical byte stream looks like this: [52 49 46] [46 B0 2C ][07 00 41] 56 49 20 4C 49 53 54 D2 00 00 00 68 64 72 6C 61 76 69 68 38 00 00 00 1A 41 00 00 28 FC 00 00 00 00 00 00 10 08 00 00 8C 00 00 00 00 00 00 00 01 00 00 00 0C 1E 00 00 00 01 00 00 00 01 00 00 00 00 If you look at those links it tells you how AVI is formatted. You will see it is 'RIFF' + 4 byte file length + 'AVI' + 'LIST' + 4 byte list length + 'hdrl' + 'avih' + 4 byte chunk size + (data) It is liek a hierarchy where RIFF contains AVI and AVI contains LIST and LIST contains hdrl etc.. until you get down to the image. Each time you get a container you get a label and size, so from the size you know how many bytes to count to the header. Hope that helps.Article: 152010
Hi, >From the ChipScope user guide: On 32-bit Linux systems, you can invoke the analyzer from the command line by running: <XILINX_ISE_INSTALL>/bin/lin/analyzer On 64-bit Linux systems, you can invoke the analyzer from the command line by running: <XILINX_ISE_INSTALL>/bin/lin64/analyzer where <XILINX_ISE_INSTALL> represents the location where the Xilinx ISE Design Suite tools are installed. For example, default ISE installation on 64-bit machine: /opt/Xilinx/12.4/ISE_DS/ISE/bin/lin64/analyzer Thanks, Evgeni ======================================= http://outputlogic.com =======================================Article: 152011
One more thing. Xilinx only supports certain Linux distributions, such as RHEL. I've seen quite a few problems using ISE GUI tools, such as FPGA Editor, ChipScope analyzer, on Ubuntu, which is not supported. Thanks, EvgeniArticle: 152012
On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote: > On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote: > > > > > Thanks I will use 1ps resolution then. > > I still find weird that modelsim (or VITAL libraries) does not warn in > > such cases. > > Recheck the transcript right at the start before running for the > following type of message: > > The minimum time resolution limit (1ps) in the Verilog source is > smaller than the one chosen for SystemC or VHDL units in the design. > Use the vsim -t option to specify the desired resolution. > > KJ Well, I re-checked and there is no such warning in the transcript.... Maybe modesim does not warn if a timing is extracted from an SDF back annotation and not "hard coded" into the libraries, which I guess is the case here.Article: 152013
On 21 juin, 13:04, jc <jcappe...@optimal-design.com> wrote: > On Jun 20, 6:12=A0am, JB <jb.dubois....@gmail.com> wrote: > > > > > > > > > > > Hello all, > > > I struggle with an issue I can't understand the root cause. > > > When simulating my back annoted design with modelsim, I get unexpected > > behavior when using a simulation step of 1ns, but no errors when using > > a step of 1ps. > > > My design is running at 1MHz (so I expect a simulation step of 1ns to > > be highly sufficient). > > The part that is causing trouble is a wrapper around an SRAM instance > > (it is an actel RAM512x18 component on an actel proasic3 FPGA). > > > I've got the exact same component instanciated in the exact same > > wrapper simulating fine on an actel igloo FPGA. I am aware that place > > and route may have produce significantly different results between the > > two FPGAs and that having the design running smoothly on one FPGA > > don't prove anything. > > > Still I can't figure out why modelsim would not simulate identically > > using a 1ns or 1ps step. > > > Last but not least, I've got no warning from modelsim (no glitch > > found). > > > If any of you have an idea of what could be happening there I would be > > glad to ear it. > > > Regards > > I don't see evidence that this is your problem, but a classic "back- > annotated sim time resolution problem" that often arises is the mixing > of your testbench environment made up only of idealistic delays (i.e. > delays are only based on the temporal ordering assignments made by > your simulator) with your back-annotated "real world" worst case > delays. For instance, if you attempt to clock a signal from a simple > clocked assignment statement into a back-annotated reg with a real > setup time assigned to it, it will always be one cycle behind. A > typical fix for this is to add an artificial delay to your testbench > assignment statements that interact directly with the back-annotated > code to satisfy the setup times. > - John I simulate my design as a black box with delays that can be quite random and never synched with the clock. It may happen that modelsim detects timing violation on the antimetastability FF inputs but the design shall be robust to that. Anyway simulating at 1ps got solved my problem. I called Actel to ask them what was the optimal time resolution to gain simulation perfomance without trading accuracy and the only answer I got is "generate a simulation through Libero and look in the generated .do file for the requested time resolution", which I did and it was 1ps. I find weird that this advised resolution can't not found in any Actel documentation I've searched, except one application note which request 1ps only if using a PLL (which was not my case). Thanks anyway for your advices.Article: 152014
On Jun 21, 6:59=A0pm, JB <jb.dubois....@gmail.com> wrote:
> On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote:
>
>
>
>
>
> > On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:
>
> > > Thanks I will use 1ps resolution then.
> > > I still find weird that modelsim (or VITAL libraries) does not warn i=
n
> > > such cases.
>
> > Recheck the transcript right at the start before running for the
> > following type of message:
>
> > The minimum time resolution limit (1ps) in the Verilog source is
> > smaller than the one chosen for SystemC or VHDL units in the design.
> > Use the vsim -t option to specify the desired resolution.
>
> > KJ
>
> Well, I re-checked and there is no such warning in the transcript....
> Maybe modesim does not warn if a timing is extracted from an SDF back
> annotation and not "hard coded" into the libraries, which I guess is
> the case here.- Hide quoted text -
>
Do you have all messages enabled? Under simulation run-time options
there are choices to disable certain levels of messages ('note',
'warning', 'error').
KJ
Article: 152015
On Jun 21, 6:04=A0am, Tom Johnson <digdesignc...@gmail.com> wrote:
> On Jun 18, 11:31=A0am, Simon <goo...@gornall.net> wrote:
>
>
>
>
>
>
>
>
>
> > On Jun 17, 7:33=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > On Jun 16, 2:38=A0pm, Gabor <ga...@szakacs.invalid> wrote:
>
> > > > Simon wrote:
> > > > > Hopefully not sparking any religious wars here, but hoping for so=
me
> > > > > advice from those-who-know :)
>
> > > > > I switched to using Altera's software a couple of years ago, beca=
use
> > > > > it felt more intuitive to me - probably a personal thing, but it =
just
> > > > > grocked better; however, I was browsing the xilinx site just rece=
ntly,
> > > > > idly wondering if the -7 series that I'd heard so much about had
> > > > > actually arrived yet (big surprise, it's still vapour-ware to the
> > > > > likes of me), and I saw the SP605 evaluation kit had dropped to $=
695.
>
> > > > > This seems to be a really great deal. You get a nice high-bandwid=
th-
> > > > > memory card, with a PCI-e interface, and high-speed external
> > > > > connections (ok, only 68/34 pins, but still), as well as a full (=
even
> > > > > if device-locked) ISE license for both the EDK and ISE. My innate
> > > > > cynicism asks "what's the catch ?"
>
> > > > > So, I thought I'd access the wisdom of crowds ([grin] on the firs=
t
> > > > > pass, that read: wisdom of crows :) and ask:
>
> > > > > =A0- Do you actually get a real, useful, not time-limited or anyt=
hing
> > > > > like that PCIe core ?
> > > > > =A0- Ditto for the DDR memory core ?
> > > > > =A0- Ditto for the Microblaze core ?
> > > > > =A0- Does "lite" mean the ethernet-lite core "only' does 10/100 r=
ather
> > > > > than 10/100/1000 ?
>
> > > > > It seems to suggest in the docs that the answers to the above are
> > > > > {yes, yes, yes, yes}, but that seems too good to be true. Over in
> > > > > Altera-land I'd be paying $500 for the nios2 license, and $1000 f=
or
> > > > > the memory/ethernet cores, both on top of a board-cost... I'm hal=
fway
> > > > > through a project that uses a nios2 qsys-based system, and for th=
e ~
> > > > > $1000 difference, I'm happy to port it back to Xilinx (this is a
> > > > > hobby, the cost/benefit analysis is different to most people's on=
here
> > > > > - y'all don't have the 'WAF' (wife-approval factor) to consider, =
and
> > > > > WAF trumps pretty much all :)
>
> > > > > I understand that if I ever wanted to target something other than=
an
> > > > > LX45T I'd have to re-purchase the software. Does that apply to th=
e EDK
> > > > > as well as ISE ? Or could I use the EDK that comes with the kit i=
n
> > > > > tandem with WebPack to target a smaller device ?
>
> > > > > Cheers
>
> > > > > Simon
>
> > > > Xilinx has a new approach to supplying software with demo boards. =
=A0Read
> > > > the fine print with your board, but generally what you get is a lic=
ense
> > > > to use the full EDK (Microblaze development software), which is
> > > > otherwise quite expensive. =A0This license is good for one computer
> > > > (node-locked) *and* also locked to the particular Xilinx device on =
your
> > > > demo board.
>
> > > > There's nothing to stop you from using it on your own hardware, pro=
vided
> > > > you choose the same chip. =A0Any other cores provided are also lice=
nsed
> > > > for use on that particular chip. =A0I'm not familiar enough with Sp=
artan
> > > > 6 to know if you would normally pay for the PCIe license, but on th=
e
> > > > Virtex 5 parts that have a built-in PCIe endpoint block the "wrappe=
r"
> > > > core is free. =A0Ditto for the ethernet MAC block wrappers. =A0The =
Ethernet
> > > > TriMode soft MAC is not free.
>
> > > > For very simple MicroBlaze-based designs there is a "simple MicroBl=
aze"
> > > > pre-built core available at no charge, with very limited connectivi=
ty.
> > > > You can use this wih the SDK without the need for the EDK. =A0Howev=
er
> > > > as soon as you want to build a processor with external memory and/o=
r
> > > > network connectivity you need to pony up for the EDK.
>
> > > > As far as I know, all of the Xilinx licenses are not time limited f=
or
> > > > use, but do have a time limit for maintenance (includes upgrades to
> > > > the latest version - not always a blessing). =A0The renewal fee for
> > > > maintenance is almost the same as a new license. =A0You also get
> > > > webcase support while under maintenance. =A0After that you're back =
to
> > > > trolling forums with the students.
>
> > > > -- Gabor- Hide quoted text -
>
> > > > - Show quoted text -
> > > > I'm not familiar enough with Spartan 6 to know if you would normall=
y
> > > > pay for the PCIe license, but on the Virtex 5 parts that have a bui=
lt-in
> > > > PCIe endpoint block the "wrapper" core is free
>
> > > Spartan-6 devices also include an integrated PCIe block so there is n=
o
> > > extra license cost.
>
> > > Ed McGettigan
> > > --
> > > Xilinx Inc.
>
> > Thanks Ed, (and everyone else). Looks like I'll be getting one of the
> > embedded kits then. Everyone wins, because as soon as I actually pay
> > for it, the Zynq or -7 series will immediately be available... That's
> > just the way it goes :)
>
> > Cheers
> > =A0 =A0Simon- Hide quoted text -
>
> > - Show quoted text -
>
> Simon and all, not available at the moment but hopefully soon is a
> family of boards my company is working on that may help avoid the
> old... =A0"That's just the way it goes". =A0The concept provides virtual
> pin-compatibility between FPGAs so one can switch between Xilinx,
> Altera, or others, as well as upgrade to their newer technologies when
> available. =A0Bascially, a main board will have all the bells and
> whistles you'd find on most full featured dev boards (ie., HDMI, USB,
> UART, etc), but a high density/performance 'socket' for an FPGA
> specific daughter card.
>
> On the down-side there will be some degradation to the FPGA's
> performance, IO count, and a few features due to the connectorization
> but surprisingly not much. =A0On the up-side, one can get much more
> milleage out of a full-featured main board that's not tied to a
> particular FPGA technology. =A0The cost will be more if compared to an
> existing eval board (at least till volumes grow) but the extra value
> comes from the flexibility that makes our family of boards a better
> investment. =A0There are other benefits such as 'bake-off' benchmarking
> and even choosing to use the FPGA daughter cards in production
> (thereby designing in the same flexibility to a customer's end
> product). =A0This gets a little disruptive and may be another step
> toward commoditizing FPGAs but, ... =A0"that's just the way it goes :)"
>
> There're usually many detailed questions but in general, does this
> sound like something of interest. =A0Any feedback would be appreciated.
>
> Thanks,
> Tom
I'd definitely be in favor of this kind of effort. IMHO, FPGA
development/integration boards are generally too 'integrated' (and
hence too expensive), considering that many users have no need for
bells and whistles apart from their desire to stay out of the BGA/
multilayer PCB business. A line of low-cost daughterboards with
nothing on them but medium-speed I/O connectivity, power management,
and the FPGA itself would be welcome. Maybe some pads for an optional
DRAM chip.
Article: 152016
To some extent we already do some this in our boards and there will be
some products announced shortly that will some of the way we are
going. The question of cost is always a difficult one and the dev
board market isn't usually large numbers and makes it difficult to do
consumer level pricing.
On the Xilinx/Altera comparision we have our Raggedstone2
http://www.enterpoint.co.uk/raggedstone/raggedstone2.html and
Raggedtone3 http://www.enterpoint.co.uk/raggedstone/raggedstone3.html
which offer which offer nearly the same thing in the competing
technologies. In reality it's a ding dong battle. On these 2 boards
Altera wins on the PCIe by offering X4 PCIe hard core whilst Xilinx
offers DDR3 and a hard core controller for it. The Xilinx Quad SPI
generally is much simpler (coming soon in RS2 with XC6SLX150T
versions) but slightly slower than using a loader circuit that we
deploy on Raggedstone3 to meet configuration time targets is another
difference. After that it is down to the development software.
For a low cost hardware target comparision have a look at our
Polmmaddie family http://www.enterpoint.co.uk/polmaddie/polmaddie_family.ht=
ml.
John Adair
Enterpoint Ltd.
On Jun 22, 3:27=A0am, John Miles <jmi...@gmail.com> wrote:
> On Jun 21, 6:04=A0am, Tom Johnson <digdesignc...@gmail.com> wrote:
>
>
>
> > On Jun 18, 11:31=A0am, Simon <goo...@gornall.net> wrote:
>
> > > On Jun 17, 7:33=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > > > On Jun 16, 2:38=A0pm, Gabor <ga...@szakacs.invalid> wrote:
>
> > > > > Simon wrote:
> > > > > > Hopefully not sparking any religious wars here, but hoping for =
some
> > > > > > advice from those-who-know :)
>
> > > > > > I switched to using Altera's software a couple of years ago, be=
cause
> > > > > > it felt more intuitive to me - probably a personal thing, but i=
t just
> > > > > > grocked better; however, I was browsing the xilinx site just re=
cently,
> > > > > > idly wondering if the -7 series that I'd heard so much about ha=
d
> > > > > > actually arrived yet (big surprise, it's still vapour-ware to t=
he
> > > > > > likes of me), and I saw the SP605 evaluation kit had dropped to=
$695.
>
> > > > > > This seems to be a really great deal. You get a nice high-bandw=
idth-
> > > > > > memory card, with a PCI-e interface, and high-speed external
> > > > > > connections (ok, only 68/34 pins, but still), as well as a full=
(even
> > > > > > if device-locked) ISE license for both the EDK and ISE. My inna=
te
> > > > > > cynicism asks "what's the catch ?"
>
> > > > > > So, I thought I'd access the wisdom of crowds ([grin] on the fi=
rst
> > > > > > pass, that read: wisdom of crows :) and ask:
>
> > > > > > =A0- Do you actually get a real, useful, not time-limited or an=
ything
> > > > > > like that PCIe core ?
> > > > > > =A0- Ditto for the DDR memory core ?
> > > > > > =A0- Ditto for the Microblaze core ?
> > > > > > =A0- Does "lite" mean the ethernet-lite core "only' does 10/100=
rather
> > > > > > than 10/100/1000 ?
>
> > > > > > It seems to suggest in the docs that the answers to the above a=
re
> > > > > > {yes, yes, yes, yes}, but that seems too good to be true. Over =
in
> > > > > > Altera-land I'd be paying $500 for the nios2 license, and $1000=
for
> > > > > > the memory/ethernet cores, both on top of a board-cost... I'm h=
alfway
> > > > > > through a project that uses a nios2 qsys-based system, and for =
the ~
> > > > > > $1000 difference, I'm happy to port it back to Xilinx (this is =
a
> > > > > > hobby, the cost/benefit analysis is different to most people's =
on here
> > > > > > - y'all don't have the 'WAF' (wife-approval factor) to consider=
, and
> > > > > > WAF trumps pretty much all :)
>
> > > > > > I understand that if I ever wanted to target something other th=
an an
> > > > > > LX45T I'd have to re-purchase the software. Does that apply to =
the EDK
> > > > > > as well as ISE ? Or could I use the EDK that comes with the kit=
in
> > > > > > tandem with WebPack to target a smaller device ?
>
> > > > > > Cheers
>
> > > > > > Simon
>
> > > > > Xilinx has a new approach to supplying software with demo boards.=
=A0Read
> > > > > the fine print with your board, but generally what you get is a l=
icense
> > > > > to use the full EDK (Microblaze development software), which is
> > > > > otherwise quite expensive. =A0This license is good for one comput=
er
> > > > > (node-locked) *and* also locked to the particular Xilinx device o=
n your
> > > > > demo board.
>
> > > > > There's nothing to stop you from using it on your own hardware, p=
rovided
> > > > > you choose the same chip. =A0Any other cores provided are also li=
censed
> > > > > for use on that particular chip. =A0I'm not familiar enough with =
Spartan
> > > > > 6 to know if you would normally pay for the PCIe license, but on =
the
> > > > > Virtex 5 parts that have a built-in PCIe endpoint block the "wrap=
per"
> > > > > core is free. =A0Ditto for the ethernet MAC block wrappers. =A0Th=
e Ethernet
> > > > > TriMode soft MAC is not free.
>
> > > > > For very simple MicroBlaze-based designs there is a "simple Micro=
Blaze"
> > > > > pre-built core available at no charge, with very limited connecti=
vity.
> > > > > You can use this wih the SDK without the need for the EDK. =A0How=
ever
> > > > > as soon as you want to build a processor with external memory and=
/or
> > > > > network connectivity you need to pony up for the EDK.
>
> > > > > As far as I know, all of the Xilinx licenses are not time limited=
for
> > > > > use, but do have a time limit for maintenance (includes upgrades =
to
> > > > > the latest version - not always a blessing). =A0The renewal fee f=
or
> > > > > maintenance is almost the same as a new license. =A0You also get
> > > > > webcase support while under maintenance. =A0After that you're bac=
k to
> > > > > trolling forums with the students.
>
> > > > > -- Gabor- Hide quoted text -
>
> > > > > - Show quoted text -
> > > > > I'm not familiar enough with Spartan 6 to know if you would norma=
lly
> > > > > pay for the PCIe license, but on the Virtex 5 parts that have a b=
uilt-in
> > > > > PCIe endpoint block the "wrapper" core is free
>
> > > > Spartan-6 devices also include an integrated PCIe block so there is=
no
> > > > extra license cost.
>
> > > > Ed McGettigan
> > > > --
> > > > Xilinx Inc.
>
> > > Thanks Ed, (and everyone else). Looks like I'll be getting one of the
> > > embedded kits then. Everyone wins, because as soon as I actually pay
> > > for it, the Zynq or -7 series will immediately be available... That's
> > > just the way it goes :)
>
> > > Cheers
> > > =A0 =A0Simon- Hide quoted text -
>
> > > - Show quoted text -
>
> > Simon and all, not available at the moment but hopefully soon is a
> > family of boards my company is working on that may help avoid the
> > old... =A0"That's just the way it goes". =A0The concept provides virtua=
l
> > pin-compatibility between FPGAs so one can switch between Xilinx,
> > Altera, or others, as well as upgrade to their newer technologies when
> > available. =A0Bascially, a main board will have all the bells and
> > whistles you'd find on most full featured dev boards (ie., HDMI, USB,
> > UART, etc), but a high density/performance 'socket' for an FPGA
> > specific daughter card.
>
> > On the down-side there will be some degradation to the FPGA's
> > performance, IO count, and a few features due to the connectorization
> > but surprisingly not much. =A0On the up-side, one can get much more
> > milleage out of a full-featured main board that's not tied to a
> > particular FPGA technology. =A0The cost will be more if compared to an
> > existing eval board (at least till volumes grow) but the extra value
> > comes from the flexibility that makes our family of boards a better
> > investment. =A0There are other benefits such as 'bake-off' benchmarking
> > and even choosing to use the FPGA daughter cards in production
> > (thereby designing in the same flexibility to a customer's end
> > product). =A0This gets a little disruptive and may be another step
> > toward commoditizing FPGAs but, ... =A0"that's just the way it goes :)"
>
> > There're usually many detailed questions but in general, does this
> > sound like something of interest. =A0Any feedback would be appreciated.
>
> > Thanks,
> > Tom
>
> I'd definitely be in favor of this kind of effort. =A0IMHO, FPGA
> development/integration boards are generally too 'integrated' (and
> hence too expensive), considering that many users have no need for
> bells and whistles apart from their desire to stay out of the BGA/
> multilayer PCB business. =A0A line of low-cost daughterboards with
> nothing on them but medium-speed I/O connectivity, power management,
> and the FPGA itself would be welcome. =A0Maybe some pads for an optional
> DRAM chip.
Article: 152017
On 22 juin, 01:38, KJ <kkjenni...@sbcglobal.net> wrote:
> On Jun 21, 6:59=A0pm, JB <jb.dubois....@gmail.com> wrote:
>
>
>
>
>
>
>
>
>
> > On 20 juin, 18:23, KJ <kkjenni...@sbcglobal.net> wrote:
>
> > > On Jun 20, 8:52=A0am, JB <jb.dubois....@gmail.com> wrote:
>
> > > > Thanks I will use 1ps resolution then.
> > > > I still find weird that modelsim (or VITAL libraries) does not warn=
in
> > > > such cases.
>
> > > Recheck the transcript right at the start before running for the
> > > following type of message:
>
> > > The minimum time resolution limit (1ps) in the Verilog source is
> > > smaller than the one chosen for SystemC or VHDL units in the design.
> > > Use the vsim -t option to specify the desired resolution.
>
> > > KJ
>
> > Well, I re-checked and there is no such warning in the transcript....
> > Maybe modesim does not warn if a timing is extracted from an SDF back
> > annotation and not "hard coded" into the libraries, which I guess is
> > the case here.- Hide quoted text -
>
> Do you have all messages enabled? =A0Under simulation run-time options
> there are choices to disable certain levels of messages ('note',
> 'warning', 'error').
>
> KJ
I launch the simulation using a command line, the only disabled
message are VITAL glitch messages (+no_glitch_msg). From what I've
read (mostly) all messages are enabled by default.
Article: 152018On 22 Jun., 01:08, JB <jb.dubois....@gmail.com> wrote: > I simulate my design as a black box with delays that can be quite > random and never synched with the clock. It may happen that modelsim > detects timing violation on the antimetastability FF inputs but the > design shall be robust to that. > > Anyway simulating at 1ps got solved my problem. > > I called Actel to ask them what was the optimal time resolution to > gain simulation perfomance without trading accuracy and the only > answer I got is "generate a simulation through Libero and look in the The timescale in your sdf is most likely 100ps. If you consider, that values with two digit after the decimal point are used within sdf, you could guess that you need 1 ps resolution to model these timings provided. I would not expect any vendor to give a minimum timescal explicit, but you need to use a decent resolution when simulating in order to get correct results. This is some basic of engineering, that you are needed to justify all simplifications you do to a model. And setting the resolution of netlist simulation to 1 ns is a major simplification with todays technologies. You should ask yourself on what assumption you came to the conclusion that 1 ns resolution is good for netlist simulation. best regards ThomasArticle: 152019
On Jun 21, 11:57=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > To some extent we already do some this in our boards and there will be > some products announced shortly that will some of the way we are > going. The question of cost is always a difficult one and the dev > board market isn't usually large numbers and makes it difficult to do > consumer level pricing. > > On the Xilinx/Altera comparision we have our Raggedstone2http://www.enter= point.co.uk/raggedstone/raggedstone2.htmland > Raggedtone3http://www.enterpoint.co.uk/raggedstone/raggedstone3.html > which offer which offer nearly the same thing in the competing > technologies. In reality it's a ding dong battle. On these 2 boards > Altera wins on the PCIe by offering X4 PCIe hard core whilst Xilinx > offers DDR3 and a hard core controller for it. The Xilinx Quad SPI > generally is much simpler (coming soon in RS2 with XC6SLX150T > versions) but slightly slower than using a loader circuit that we > deploy on Raggedstone3 to meet configuration time targets is another > difference. After that it is down to the development software. > > For a low cost hardware target comparision have a look at our > Polmmaddie familyhttp://www.enterpoint.co.uk/polmaddie/polmaddie_family.h= tml. I looked at your boards, John, because I'd *really* like a x4 PCIe for the co-processor card, but when I went to see if the raggedstone3 board was available, the shop page failed to load (it's just a blank white page). I tried it on Safari and on Firefox before giving up. The thing is that even if I get one of the third-party boards, I won't get an embedded-cpu license for free, and I'm sort of considering the board to be pretty-much free and I'm paying for the IP when I buy a vendor board... If I were to buy a 3rd-party board, I have to buy the IP (in this case the EDK | NIOS2/DDR) as well... Simon.Article: 152020
On Jun 22, 5:21=A0am, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > I would not expect any vendor to give a minimum timescal explicit, but > you need to use a decent resolution when simulating in order to get > correct results. This is some basic of engineering, You're probably being overly harsh on JB as well as being guilty of the same thing that you say he is lax on. After all, what is your definition of 'decent resolution' if you yourself don't expect a vendor to give you minimum timescale...which they did by the way in this case by telling JB the method to determine that timescale. KJArticle: 152021
Simon The board isn't properly live on our shop as yet. We are still completing the qualification tests on this board and that testing is now nearly complete. The board design looks very good so far and at the moment it looks like Issue1 will ship without mods or alteration of the design. Realistically I think they should be available in small numbers in about 4-8 weeks time assuming no major issues are found with a significant ramp in numbers the month or two behind that. John Adair Enterpoint Ltd. On Jun 22, 3:47=A0pm, Simon <goo...@gornall.net> wrote: > On Jun 21, 11:57=A0pm, John Adair <g...@enterpoint.co.uk> wrote: > > > > > To some extent we already do some this in our boards and there will be > > some products announced shortly that will some of the way we are > > going. The question of cost is always a difficult one and the dev > > board market isn't usually large numbers and makes it difficult to do > > consumer level pricing. > > > On the Xilinx/Altera comparision we have our Raggedstone2http://www.ent= erpoint.co.uk/raggedstone/raggedstone2.htmland > > Raggedtone3http://www.enterpoint.co.uk/raggedstone/raggedstone3.html > > which offer which offer nearly the same thing in the competing > > technologies. In reality it's a ding dong battle. On these 2 boards > > Altera wins on the PCIe by offering X4 PCIe hard core whilst Xilinx > > offers DDR3 and a hard core controller for it. The Xilinx Quad SPI > > generally is much simpler (coming soon in RS2 with XC6SLX150T > > versions) but slightly slower than using a loader circuit that we > > deploy on Raggedstone3 to meet configuration time targets is another > > difference. After that it is down to the development software. > > > For a low cost hardware target comparision have a look at our > > Polmmaddie familyhttp://www.enterpoint.co.uk/polmaddie/polmaddie_family= .html. > > I looked at your boards, John, because I'd *really* like a x4 PCIe for > the co-processor card, but when I went to see if the raggedstone3 > board was available, the shop page failed to load (it's just a blank > white page). I tried it on Safari and on Firefox before giving up. > > The thing is that even if I get one of the third-party boards, I won't > get an embedded-cpu license for free, and I'm sort of considering the > board to be pretty-much free and I'm paying for the IP when I buy a > vendor board... If I were to buy a 3rd-party board, I have to buy the > IP (in this case the EDK | NIOS2/DDR) as well... > > Simon.Article: 152022
Hi, I need to modify the netlist generated from "Generate Post-map simulation model"(i.e. netgen). After the netlist modifcation, can I continue the work of place&route based on the modified simulation model netlist? Thanks! Eric --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152023
> When simulating my back annoted design with modelsim, I get unexpected > behavior when using a simulation step of 1ns, but no errors when using > a step of 1ps. Do you need to do back annotated simulation? If a functional simulation works, the design is properly constrained and is passing static timing analysis then I'd expect it to work solidly. ? Nial.Article: 152024
>Hi, > I need to modify the netlist generated from "Generate Post-map simulation >model"(i.e. netgen). > > After the netlist modifcation, can I continue the work of place&route >based on the modified simulation model netlist? > > Thanks! > > Eric > > >--------------------------------------- >Posted through http://www.FPGARelated.com > Short answer: no. Why do you need to modify the post-map SIMULATION netlist? --------------------------------------- Posted through http://www.FPGARelated.com
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