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In fact you are right, this is what I was searching for, but I didn't know what was the better way to implement it. Now with your help I found it. Thanks GioArticle: 85801
Neo wrote:
> I am into hardware design and eventhough I have designed for many
> components and modules one question always bugs me. How do we go about
> determining the partition of a design, say some device controller.
A single design module is simplest if there is
no reason to split it. Connections
between modules are tedious.
Possible reasons to partition include
multiple module instances, testbench complexity,
multiple designers and the availability of specifications.
-- Mike Treseler
Article: 85802Hi Neo, There is no unique way to do this. However, there are some general guidelines for methodological approach, which I am always using in my team. The list is very long, but the basic considerations that the blocks are partitoined according to are: (*) complexity (mostly in terms of logic density) (*) independency in terms of logic functionality (say, TX & RX flows are always in the different blocks) (*) ability to debug, that is, if you bring a block to waveform, there would not be too many signals (no need ot scroll and group too many signals) (*) always keep not more than 1 clock per module (*) in one module, there should be no mix of logic and instances (*) clock and reset generation should be handled within a separate block. These are not mandatory, i.e. the design still could be working if the above are not considered, but this represents a good design practice in terms of organized team work & design integrability & interoperability, especially if you are designing something for several applications and the changes are only in several places, than a correct and profound thinking about the partitioning could ease the future work. Hope this helps. Vladislav "Neo" <zingafriend@yahoo.com> wrote in message news:1118902318.707501.21630@g14g2000cwa.googlegroups.com... > Hi comrades, > I am into hardware design and eventhough I have designed for many > components and modules one question always bugs me. How do we go about > determining the partition of a design, say some device controller. In > case of interfaces like control blocks to memories or fifos the > interface and fucntionality is quite clear. But what about the > interfaces when we partition a design in to sub-blocks. Is there an > optimum way to partition the design and also minimize the interface > details between them. >Article: 85803
Narayan, Let me first ask why? If you synthesize the design, either ISE or Synplify do generate edif netlist. In ISE, i believe, there is ndg2edif or ngc2edif command or something like this. Vladislav "Narayan" <narayan.subramanian@gmail.com> wrote in message news:1118893150.128237.7370@g44g2000cwa.googlegroups.com... > hi all, > > I am trying to find some means of converting a design described as a > vhdl code to edif file. I am using xilinx tool set (from entry to > device programming). Are there any other tools that can do the same > job. > > Thanks! > Narayan >Article: 85804
Hi Davy,
No tool that I know of, but you can write code in such a way that the
pipelining is configurable. I've written a few blocks where I could
adjust the pipelining of the block by changing a "pipelining schedule",
which was just an array variable containing pipeline-able points in the
design. By changing this variable, I could change the amount of
pipelines, and therefore the amount of registers used and the fmax of
the design. This has worked pretty well for me for designs like binary
trees of arbitrary depth. At the top of the code I would have a
variable like:
pipeline_schedule(TREE_DEPTH-1 downto 0) := ( 0, 1, 1, 0, 1, 1 );
and further in the code where I would have, say a tree I would do
something like (this is not the actual code, just the idea here):
for i in 1 to TREE_DEPTH-1 generate
for j in 0 to LEAVES-1 generate
if (pipeline_schedule(i)==0) generate
-- just a level of logic
a(i)(j*2) <= max( a(i-1)(j), a(i-1)(j+1) );
end generate;
if (pipeline_schedule(i)==1) generate
-- create a pipeline stage
if clk='1' and clk'event
a(i) <= max( a(i-1)(j), a(i-1)(j+1) );
endif
endif
endgenerate;
endgenerate;
So whereever the variable pipeline_schedule has a 1, that level in the
tree would be pipelined. This works for a regular structure like a
tree. It would be more difficult to code something non-regular like a
complex control circuit with configurable pipelining. Anyways, this
method allowed me to balance an IP block between resource usage and
speed. You could extend the idea by automatically creating a schedule
if you knew how many levels of logic a certain fmax in a certain device
could be tolerated (I didnt' go this far; I created the schedule
empirically).
-- Pete
Article: 85805On 15 Jun 2005 20:06:31 -0700, Peter Alfke wrote: > sean wrote: >>> Is this from UMC or Toshiba? Or Both? >> >> Will the current specifications be maintained? Or is there a new >> specification to deal with the change in process/FAB? > > Whether the parts are made by UMC or Toshiba (Spartan3 is not), and > whether they were born on a 200 mm or a 300 mm wafer is of no concern ( > or should be of no concern) to the average user. All these parts have > to meet (and do meet) the data sheet specification. This would certainly speak to the lack of parts, the obvious reason to migrate to 300mm wafers(I was informed that this happened a long time ago) is increased yeild. Making this change now would indicate that the current method is not meeting demand/yield needs. It also suggests that transition to 300mm wafers is not seemless, as the process has to meet the existing specification and not the other way around. > But since there are (albeit minute) process differences and different > mask sets involved, we have to do new qualification tests ( like static > discharge) on all pins and on all internal functions. And that takes > time. > Having multiple fabs is common these days, not only for ICs, also for > raw materials, food stuff, machinery, automobiles, household goods, > books and magazines, etc. Whether a particular car is assembled in > Michigan, Canada, or Ohio should not be a major concern for the buyer. > But when you buy a whole fleet of them, you may be interested, perhaps > for reasons of consistency and tracability. This assumes that all FABs use the same materials and methods, or the specification has to stretch to cover both FABs, correct? > > IC mask sets and wafer sizes went through many rapid changes over the > previous decades, and few buyers were concerned, as long as the specs > were met. And the IC supplier had a lot of latitude. Now we have far > less freedom, since a smaller-geometry process automatically means a > lower supply voltage, and thus a completely new part number. In the 5-V > era, we all used to make lots of changes without telling you, unless > you were a big corporate customer. Guess how many fabs and mask > revisions Intel has on their Pentiums? (Pentia?) > > In other words, no user should be concerned about the wafer diameter. > We just try to abide by self-imposed rules. (And they, unfortunately, > led to the artificial scarcity). > Peter Alfke, from home.Article: 85806
Another reason is to partition into things you think would make sense to re-use, so I like to partition at boundaries where I could take a partition and move it into another project with minimum interface change. -- Pete > Possible reasons to partition include > multiple module instances, testbench complexity, > multiple designers and the availability of specifications. > > -- Mike TreselerArticle: 85807
Hi ppl, I previously asked something similar. The thing is that I am integrating a design of somebody who's been using schematic design capture and his design is delivered in a generated VHDL code (or NGC as well). Now, the delivered design has already IBUFs / OBUFs inside, whereas my high-level code (the top module) does not. Consequently, I cannot do AND between two dsesigns, one with and one without IBUFs / OBUFs. If I turn on "Add I/O Buffers" option, I get an error, as the buffers are trying to be driven by another buffers inferred by the tool. If I turn off "Add I/O Buffers" option, all the logic is removed form design, as LOC constraints on the pins cannot be applied, because no buffers are inferred. As far as I understand the situation I have two choices: (*) I design this core by myself. (*) I manually add IBUFs / OBUFs in the top module and try synthesizing with "Add I/O Buffers" option turned off. Is there a way to enable / disable the option "Add I/O Buffers" in Xilinx per module / block? Is there a way to overcome this problem? Thank you all for your time and attention Sincerely, VladislavArticle: 85808
Hi,
There's a few ways to do this. For Xilinx you would probably want to go
through Coregen and implement a ROM with an init file.
You can also built the LUT entirely out of slices (as opposed to the
specialize block memory structures) by using generic code. Below is an
example that should work for probably any FPGA (Xilinx, Altera, etc).
The LUT contents are define in-line, so it's not as nice as using a
data file. (I'm lazy, so it's only an 8-entry 8-bit LUT).
Finally, for simulation only, you can use the Verilog block "initial"
to and $readmemb to read from a file. This won't work if you want to
synthesize to real hardware like the code below.
-- Pete
module lut
#(
parameter INPUT_WIDTH = 3,
parameter DATA_WIDTH = 8
)
(
input clk, reset,
input [INPUT_WIDTH-1:0] in,
output reg [DATA_WIDTH-1:0] out
);
wire [DATA_WIDTH-1:0] my_lut_values[2**INPUT_WIDTH-1:0];
wire [0:DATA_WIDTH*(2**INPUT_WIDTH)-1] my_lut_string;
// my string of values that will initialize the LUT: A0, B7, 15, C3,
11, 22, 33, 44
assign my_lut_string = { 64'ha0b715c318223344 };
// put the initialization string into the LUT array
genvar i;
generate
for (i=0; i < 2**INPUT_WIDTH; i=i+1)
begin: part_select
assign my_lut_values[i] = my_lut_string[(i+1)*DATA_WIDTH-1 -:
DATA_WIDTH];
end
endgenerate
// do the lookup
always @(posedge clk)
begin
if (reset)
out <= 8'b0;
else
out <= my_lut_values[in];
end
endmodule
Article: 85809xilinx_user wrote: > Does anyone know if there is a specific problem leading to long lead > times for the Spartan3. Someone from one of the major distribitors said > there was. Also, Xilinx no longer sells the Spartan3 on the website, > whereas they used to do so. > > An answer would be appreciated as I want to use this part and already > have it designed in. This appears to be a significant issue. Xilinx (both here and in their press releases) has touted Spartan-3 as alive and well for about two years now. However, there have been multiple reports of this nature during that period as a quick scan of comp.arch.fpga history illustrates: http://groups-beta.google.com/groups?q=spartan+3+availability&hl=en&lr=& A certain amount of this is tolerable, but not for an extended period of time.Article: 85810
Hi Everyone, I would be really for any help or advice you can offer me on the following. I have created a simple tri-state bus as a macro using xdl. The design consists of two TBUFs driving a single long line. (Diagram at http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif) <img src="http://www.comms.scitech.susx.ac.uk/~ian/files/tbuf.gif"> I attach external macro pins to Out, Enable and In of each TBUF. However, when I try to include the macro in a design, the DRC in the map phase complains that the Out pin is being driven by two sources. MAP Error Message: ERROR:MapLib:22 - Bus M0_DATA_LEFT_O_OBUF driven by bm_instance and bm_instance has multiple active drivers. This is not correct, as the O pins are external macro outputs! Is there anyway to prevent this? Xilinx don't list any help for this Error. /Ian.Article: 85811
Hi, I have a FDB board but I have lost schematics. Here is the board : http://www.cmosexod.com/fnd.htm Did someone of you got it and can send it to me by mail? ThanksArticle: 85812
Thanks I have made as you have said... unfortunately nothing... not work.... :( :( I have installed the last version of impact.....is the same... :cry: :oops:Article: 85813
Hi,
I 'm trying to use UART with NIOS2 (Stratix).
I would like to send a message to Hyperterminal.
(not with JTAG_UART, and not with NIOS IDE console)
Could you help me ?.
(free example could be perfect !).
Regards,
BH.
Article: 85814(This was originally posted on sci.electronics.design and was intended to be cross-posted to these groups but that got missed before sending. So here it is posted to these groups but not sci.electronics.design--if you like please cross-post your reply to that newsgroup. Sorry for the inconvenience). ------------- Hello, Does anyone else find themselves in the position I often find myself in: It is a royal pain to get prototype quantities populated with BGA components. If an assembly house has BGA machinery they are typically too big to care about the little guy like me who doesn't need all that many boards assembled but is willing to pay for the service for a few boards. For the first few boards I often like to populate in blocks and do tests at each stage so if there is a problem it is much easier to isolate the problem. If you populate the whole board and then find a problem (if you can) fixing it often means removing components that you've already populated. It would also be very expensive to populate a small run using an SMT-line and then find out that the power supply is going to blow up parts (especially a worry if you have a boost power supply). Does anyone know of anywhere that will take a few boards and populate a few BGA's by hand? In Canada? In southern Onatrio? If there is nothing out there, is anyone interested in this type of service. I need this service so I was considering purchasing a rework station and then making the service available for a fee to pay for the station and to provide a service to the design world. Would anyone use this? Thanks for your input, James.Article: 85815
>"James Morrison" <spam1@stratforddigital.ca> schrieb im Newsbeitrag news:p5ise.10538$5u4.34021@nnrp1.uunet.ca... > > Hello, > > Does anyone else find themselves in the position I often find myself in: > It is a royal pain to get prototype quantities populated with BGA > components. If an assembly house has BGA machinery they are typically > too big to care about the little guy like me who doesn't need all that > many boards assembled but is willing to pay for the service for a few > boards. > > For the first few boards I often like to populate in blocks and do tests > at each stage so if there is a problem it is much easier to isolate the > problem. If you populate the whole board and then find a problem (if > you can) fixing it often means removing components that you've already > populated. > > It would also be very expensive to populate a small run using an > SMT-line and then find out that the power supply is going to blow up > parts (especially a worry if you have a boost power supply). > > Does anyone know of anywhere that will take a few boards and populate a > few BGA's by hand? In Canada? In southern Onatrio? > > If there is nothing out there, is anyone interested in this type of > service. I need this service so I was considering purchasing a rework > station and then making the service available for a fee to pay for the > station and to provide a service to the design world. Would anyone use > this? > > Thanks for your input, > > James. > where I work we have inhouse facilities for exactly that type of work, the BGAs are not a pain at all if you have the vapor phase thing :) and yes we do populate the new to be tested boards step by step.. to make sure the power supply doesnt blow it all appart we are not in Canada, but postal services are fast todays :) a plain rework station is not much good (if you main hot air station), you really need a vapor phase also if you are doing BGAs with 0.5mm pitch then its getting more complicated to get them placed correctly, for 0.8mm it is ok to just manually place, it works also without solder being applied 0.5mm to my knowledge will not solder without extra solder being applied or needs some higher temperatures than the normal stuff, at least we have not succeeded in soldering them without paste, they just did not stick at all, well the BGA was PBfree and we had too low temperatur medium I think there are plans here to offer the SMT services more widely (not only for inhouse needs) so we might be able to help AnttiArticle: 85816
Thanks for the reply. I downloaded the Jam Player code, not the greatest code. but there is no document detailing the STAPL format. What I liked about 1532 was the dedicated ISP commands that would provide almost direct access to the flash. But I'm afraid that with STAPL I may have to go through the whole boundary scan chain and I can see how that needs lots of memory. Thanks, mArticle: 85817
On Thu, 16 Jun 2005 08:58:16 -0500, Chuck Dillon <spam@nimblegen.com> wrote: >I believe he's talking about a single frame exposure not video. He's >talking about motion during the exposure and I assume a problem of >varying affects of the motion on the different sensors (e.g. R,G and B) >that combine to give the final image. If the end product is a single frame, what prevents from taking multiple exposures and combine the shifted exposures into a single frame ? In ground based optical astronomy, the telescope is stable, but the atmospheric turbulence deflect the light rays quite frequently to slightly different directions. Taking a long exposure would cause quite blurred pictures. Take multiple short exposures, shift each exposure according to the atmospheric deflection and combine the exposures. Look for "stacking" and "speckle-interferometer". To do the image stabilisation in a camera, the MPEG motion vectors could be used to determine the global movement between exposures, but unfortunately getting reliable motion vectors from low SNR exposures is quite challenging. Of course if 3 axis velocity sensors are available, these can be used to get rid of any ambiguous motion vectors and also simplify searching for motion vectors. With reliable motion vectors for these multiple low SNR exposures, the exposures can be shifted accordingly, before summing the exposures to a single high SNR frame. PaulArticle: 85818
This is the "catch-all" error for impact when the JTAG loop doesn't work. I've seen this problem when there was a break in the TDI to TDO chain, especially when the break was in TDI at the programming connector of the board to be programmed. If your chain first shows up (parts correctly identified) and then won't respond to any programming commands I would look at the TDI line to the first device in the chain. Also check that all devices in the chain have core and I/O power and that PROGB and INITB lines are high (for FPGA's). No version of impact will work if the chain is improperly connected. Good Luck, Gabor damidar wrote: > Thanks I have made as you have said... unfortunately nothing... not > work.... :( :( > > I have installed the last version of impact.....is the same... :cry: > :oops:Article: 85819
Hi, I'm starting to learn FPGA programming (using a Xilinx Spartan II 200K). I will use VHDL and already have bought VHDL books, but I think I also need a general introduction to FPGA so I plan to buy a book on FPGA. I found this one: FPGA-Based System Design by Wayne Wolf I would like to know if this book is any good, especialy for a beginer like me. I also if it will be useful in the futur for some more advanced stuff, or is it just a entry level book that you throw away once you know the stuff. It's expensive, that's why I don't want any chance. If you have any other suggestion it could be useful. what I'm really looking for is an introduction on FPGA structure (CLB,IOB,BLOCK RAM,etc..), not a VHDL or VERILOG programming book ThanksArticle: 85820
Vladislav Muravin wrote: > Hi ppl, > > I previously asked something similar. The thing is that I am integrating a > design of somebody > who's been using schematic design capture and his design is delivered in a > generated VHDL code (or NGC as well). > > Now, the delivered design has already IBUFs / OBUFs inside, whereas my > high-level code (the top module) does not. > Consequently, I cannot do AND between two dsesigns, one with and one without > IBUFs / OBUFs. > If I turn on "Add I/O Buffers" option, I get an error, as the buffers are > trying to be driven by another buffers inferred by the tool. > If I turn off "Add I/O Buffers" option, all the logic is removed form > design, as LOC constraints on the pins cannot be applied, > because no buffers are inferred. > > As far as I understand the situation I have two choices: > (*) I design this core by myself. > (*) I manually add IBUFs / OBUFs in the top module and try synthesizing with > "Add I/O Buffers" option turned off. > > Is there a way to enable / disable the option "Add I/O Buffers" in Xilinx > per module / block? No. The Add I/O buffers only really affects the top level module anyway. If you need more control, turn it off and instantiate all your I/O buffers (IBUF, IBUFG, OBUF, ughh...). > Is there a way to overcome this problem? > Yes. When you want to use another design as a black box, it should be built without IO buffers. Only the top level design should have IO buffers. Therefore you need two projects, one to build the black box (in your case a schematic project) with add I/O buffers turned off. You don't need to translate / map / place / route this project, just "synthesize" (yes there's HDL under the hood of ECS schematics) to create the ngc file. The second is your top level project (HDL in your case) with Add I/O Buffers turned on. In this project you create an empty HDL module with the i/o list from the schematic. If the schematic module connects to pins, you'll need to add the connections from this module to the pins in your HDL top-level code. Then just move the ngc file from the schematic project to the synthesis directory (project directory) of the HDL project. Make sure the base filename is the same as the module name in your HDL. XST will not try to synthesize your empty HDL module, but will insert the compiled ngc into the top level design. > Thank you all for your time and attention > > Sincerely, > VladislavArticle: 85821
Giox wrote:
>Hello everybody, I'm a newbye in FPGA so I need some help in a simple
>problem.
>I would like to implement a 256 byte LUT on a Virtex 300 E FPGA.
>Can you suggest me some on line resource that explains how to implement
>this LUT, how to select the memory resources that I want use for this
>task etc?
>Thanks a lot for any help, Giovanni
>
>
>
Unless you don't have the BRAM to spare, I'd use a BRAM for this. The
easiest method is to use the core generator and an initialization file.
Alternatively, you can instantiate a RAMB16 and set up the INIT
attributes with your data.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 85822I heard back from the major distributor today, who said that there are indeed no parts available for prototype / pre-production and certainly not larger quantities. They thought there might be a possibility of obtaining something in an industrial temperature grade, but otherwise nothing, magic 300mm suffix or no magic suffix. Otherwise there appears to be nothing anywhere. The Xilinx web store commented that the reason the S3 was removed from the site was because there was 'no stock'. They made no mention of a policy decision to cut off small quantities. However, they did not offer any explanation why the entire product line in all sizes and packages would simultaneously disappear from the store instead of just showing 'no stock' on the items that were not in stock. There was no time frame given for restoring the items to the web store, or for having anything back in stock. It does not appear that Xilinx is quite ready to come clean just yet. It is encouraging that Xilinx is listening, which is more than many companies do, though ultimately it needs to be followed up by concrete action. This would seem likely to include restoring the products to the web store (even if out of stock), and then reserving quantities for the web store such that design and preproduction don't get torpedoed because of supply issues on a larger production scale. Large-scale production supply problems are not good, but Xilinx is certainly not the first to suffer from a popular product or process problem (whatever the case is here). What would be inexcusable would be allowing availability issues to hold up new product designs and marketing prototypes. I agree that Xilinx would do well to look at TI and similar companies. I am sure that the sample and small-quantity order system must look like a money-losing business. The trouble is that without it, there probably is no business. Perhaps the bean counters pushed the marketers and engineers away from the Xilinx controls?Article: 85823
"User" <tech3@cavelle.com> wrote in message news:1118958956.419423.83120@g14g2000cwa.googlegroups.com... > I heard back from the major distributor today, who said that there are > indeed no parts available for prototype / pre-production and certainly > not larger quantities. They thought there might be a possibility of > obtaining something in an industrial temperature grade, but otherwise > nothing, magic 300mm suffix or no magic suffix. Otherwise there > appears to be nothing anywhere. <snip> Could you mention for those in-the-know (since it's not in this thread): 1) what part, package, and speed grade 2) which distributor is giving you the info (city may help) I love to see things get solved but I don't like to see people get upset without providing the information needed to help them through the "side channels" here on the newsgroup. If there's bad info getting around, that info should be squashed.Article: 85824
> I'm starting to learn FPGA programming (using a Xilinx Spartan II >200K). I will use VHDL and already have bought VHDL books, but I think >I also need a general introduction to FPGA so I plan to buy a book on >FPGA. I found this one: Have you checkedthe data sheet? It's got all the info you need. You will probably have to read it at least 6 times - more will make sense each pass. You can learn a lot of details and what's behind them if you follow this newsgroup. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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