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We need a quick guide about how to instantiate a LVDS input and a LVDS output on the ECP3. Using the VHDL language (and Symplicity), we would like to use a set of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). I would expect, that I could instantiate a LVDS-input-cell by naming two input ports and providing their proper "LOC" attribute (say again for AN and AP), and then use AQ for the single-ended buffer output connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should IO_TYPE attribute be applied to LVDS cells ? Similar arrangement for output. Is this correct ? Or is there another way ? What is the name of the LVDS25_IN and LVDS25_OUT cells ? Thanks !Article: 139351
I'm sure I'm not the first person to control an oscillator by the amount of data in a FIFO, but I haven't found a reference to this design which is similar to a PLL. In place of a typical phase detector, I am using the count of samples in the FIFO to control the DCO which drives the output clock. Data is clocked into the FIFO using the reference (input) clock. I have an integrator between the data count and the DCO phase step input. The data count is also offset so that it is zero when at the set point. I am having trouble understanding how to model this design. Is there a unique name for this sort of circuit? At first I was thinking it was a frequency locked loop (FLL), but then I realized that the data count works the same as a phase detector by integrating the difference in frequency of the two signals, it just has a granularity of 1 cycle and does not wrap around like typical phase detectors do. So should I be using the same model for this as I would use for a conventional PLL using a standard phase detector? I am having trouble getting the circuit to lock in quickly without overshoot and hold lock as the frequency shifts. I believe I need to add a proportional element to the feedback loop. I am also considering using different coefficients when the loop is locked and when not locked. Am I making this hard and it just needs to be treated like any other PLL? RickArticle: 139352
Antti, Spartan 3 does not support dynamic reconfiguration. The design of the memory cells is such that a frame is reset to all zeroes prior to being written with the configuration. This is the "glitching" that was referenced. Now, Spartan 3A is different, and does not have this reset before being written behavior. I am aware of Recobus, and of their excellent work. I suggest that the best experience with dynamic reconfiguration will be with something other than Spartan 3, however. If you don't care that the entire frame is set to zeroes before being written (you can stop what you are doing, and resume), then you can do what you wish. I suppose this would be just "plain" reconfiguration (to configure again). More to the point, if you call or email with a problem while dynamically reconfiguring Spartan 3, you will be told that dynamic reconfiguration is not supported in Spartan 3. AustinArticle: 139353
On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote: > We need a quick guide about how to instantiate a LVDS input and a LVDS > output on the ECP3. > > Using the VHDL language (and Symplicity), we would like to use a set > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > I would expect, that I could instantiate a LVDS-input-cell by naming > two input ports and providing their proper "LOC" attribute (say again > for AN and AP), and then use AQ for the single-ended buffer output > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > IO_TYPE attribute be applied to LVDS cells ? > Similar arrangement for output. > Is this correct ? Or is there another way ? > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > Thanks ! RTFM :) if i recall correctly if you constrain the positive pad and select some LVDS io standard the rest is done by the lattice tools but you just need to read the docs and try out AnttiArticle: 139354
On Mar 27, 11:04=A0am, rickman <gnu...@gmail.com> wrote: > I'm sure I'm not the first person to control an oscillator by the > amount of data in a FIFO, but I haven't found a reference to this > design which is similar to a PLL. > > In place of a typical phase detector, I am using the count of samples > in the FIFO to control the DCO which drives the output clock. =A0Data is > clocked into the FIFO using the reference (input) clock. =A0I have an > integrator between the data count and the DCO phase step input. =A0The > data count is also offset so that it is zero when at the set point. > > I am having trouble understanding how to model this design. =A0Is there > a unique name for this sort of circuit? =A0At first I was thinking it > was a frequency locked loop (FLL), but then I realized that the data > count works the same as a phase detector by integrating the difference > in frequency of the two signals, it just has a granularity of 1 cycle > and does not wrap around like typical phase detectors do. =A0So should I > be using the same model for this as I would use for a conventional PLL > using a standard phase detector? > > I am having trouble getting the circuit to lock in quickly without > overshoot and hold lock as the frequency shifts. =A0I believe I need to > add a proportional element to the feedback loop. =A0I am also > considering using different coefficients when the loop is locked and > when not locked. > > Am I making this hard and it just needs to be treated like any other > PLL? > > Rick I call it a "rate-locked loop", but I'm not sure there is an official name. Other keywords include "elastic store" or "elastic buffer". You can write loop equations and get response curves. If the buffer length is B, the error is (x - B/2)/(B/2) where x is how much is in the buffer. The feedback is through a standard lead-lag filter, the output of which controls the buffer's empty rate. JohnArticle: 139355
rickman wrote: > I'm sure I'm not the first person to control an oscillator by the > amount of data in a FIFO, but I haven't found a reference to this > design which is similar to a PLL. > > In place of a typical phase detector, I am using the count of samples > in the FIFO to control the DCO which drives the output clock. Data is > clocked into the FIFO using the reference (input) clock. I have an > integrator between the data count and the DCO phase step input. The > data count is also offset so that it is zero when at the set point. > > I am having trouble understanding how to model this design. Is there > a unique name for this sort of circuit? The name of this circuit is the toilet flush tank regulator. It was invented by Heron of Alexandria. Just go to the toilet and see how it works. > At first I was thinking it > was a frequency locked loop (FLL), but then I realized that the data > count works the same as a phase detector by integrating the difference > in frequency of the two signals, it just has a granularity of 1 cycle > and does not wrap around like typical phase detectors do. So should I > be using the same model for this as I would use for a conventional PLL > using a standard phase detector? > > I am having trouble getting the circuit to lock in quickly without > overshoot and hold lock as the frequency shifts. I believe I need to > add a proportional element to the feedback loop. I am also > considering using different coefficients when the loop is locked and > when not locked. > > Am I making this hard and it just needs to be treated like any other > PLL? Keep it simple. If you don't want to pee, you don't have to force youself. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.comArticle: 139356
On Mar 27, 5:16=A0pm, austin <aus...@xilinx.com> wrote: > Antti, > > Spartan 3 does not support dynamic reconfiguration. =A0The design of the > memory cells is such that a frame is reset to all zeroes prior to > being written with the configuration. =A0This is the "glitching" that > was referenced. > > Now, Spartan 3A is different, and does not have this reset before > being written behavior. > > I am aware of Recobus, and of their excellent work. =A0I suggest that > the best experience with dynamic reconfiguration will be with > something other than Spartan 3, however. > > If you don't care that the entire frame is set to zeroes before being > written (you can stop what you are doing, and resume), then you can do > what you wish. =A0I suppose this would be just "plain" reconfiguration > (to configure again). > > More to the point, if you call or email with a problem while > dynamically reconfiguring Spartan 3, you will be told that dynamic > reconfiguration is not supported in Spartan 3. > > Austin Hi Austin :) no need to teach me on those topics, i know the difference what is officially supported and what is DOABLE by some read die hards.. so while i may be qualified diehard in some regards, i have not even attempted S3 reconfig (or config after erase frame, what it is called) asfaik S3A reconfiguration via ICAP is possible, but it also not much endorsed by xilinx i am still considering from time to time, some sort of COLD configuration, where some part of the bitstream is configured BEFORE download, that is not only change the content of BRAMs but also LUTS or SRL16, IO Cells, and DCM this is more likely to be doable and useable without sideffects and yes there is reason why i am interested in that, namly preconfiguration (bitfile patch) for the pregenerated MicroFPGA bitstreams. If not using the bit patch, then all parts would be need to be runtime configurable. Bit patching would reduce some logic AnttiArticle: 139357
On Mar 27, 11:18=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote: > > > We need a quick guide about how to instantiate a LVDS input and a LVDS > > output on the ECP3. > > > Using the VHDL language (and Symplicity), we would like to use a set > > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > > I would expect, that I could instantiate a LVDS-input-cell by naming > > two input ports and providing their proper "LOC" attribute (say again > > for AN and AP), and then use AQ for the single-ended buffer output > > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > > IO_TYPE attribute be applied to LVDS cells ? > > Similar arrangement for output. > > Is this correct ? Or is there another way ? > > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > > Thanks ! > > RTFM :) > > if i recall correctly if you constrain the positive pad and select > some LVDS io standard the rest is done by the lattice tools > but you just need to read the docs and try out > > Antti That was true for the tools I use, so no reason they would change for ECP3. Basically pretend the world is single-ended and the negative side of your differential pairs is inferred by the I/O standard. Locating both pins is redundant because there is only one possible I/O pairing. Just make sure you reserve the negative pins...Article: 139358
On Mar 27, 3:03=A0pm, jfh <jfhas...@club-internet.fr> wrote: > Hi, > > We are working on a project involving the Igloo part from Actel. We > have a 20 MHz clock which may present a stable logic state (either '1' > or '0') for up to 150 ns. We don't expect this event to occur very > often (not more than once per second). We were thinking of using the > PLL of the Igloo part to filter out this unnwanted state of the clock. > The characteristics of the PLL are up to 45kHz loop bandwidth (seen in > the datasheet). We did a test on an Igloo dev kit (icicle) and the > Igloo PLL looses lock. The unwanted event is repeated every 3 ms and > lasts 150 ns.The loss of lock is very fast and just before the lock > comes back the output clock from the PLL disappears for a few hundred > ns. How come regarding the characteristics of the PLL ? Any ideas ? > > Best regards, > > JF just use a free running clock at say 200 mhz and implement your own lock and adjust that will lock to the 20 mhz you would get +/- i clock jitter of the high clock but there would be no missing times of the recovered clock AnttiArticle: 139359
On Mar 27, 11:27=A0am, gabor <ga...@alacron.com> wrote: > On Mar 27, 11:18=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Mar 27, 4:46=A0pm, PGS <p...@algonordic.dk> wrote: > > > > We need a quick guide about how to instantiate a LVDS input and a LVD= S > > > output on the ECP3. > > > > Using the VHDL language (and Symplicity), we would like to use a set > > > of LVDS-inputs (say AN and AP on the pins, and AQ leading into FPGA). > > > I would expect, that I could instantiate a LVDS-input-cell by naming > > > two input ports and providing their proper "LOC" attribute (say again > > > for AN and AP), and then use AQ for the single-ended buffer output > > > connecting to FPGA-CLBs ? Does such LVDS cell exist ? And should > > > IO_TYPE attribute be applied to LVDS cells ? > > > Similar arrangement for output. > > > Is this correct ? Or is there another way ? > > > What is the name of the LVDS25_IN and LVDS25_OUT cells ? > > > Thanks ! > > > RTFM :) > > > if i recall correctly if you constrain the positive pad and select > > some LVDS io standard the rest is done by the lattice tools > > but you just need to read the docs and try out > > > Antti > > That was true for the tools I use, so no reason they would change > for ECP3. =A0Basically pretend the world is single-ended and the > negative side of your differential pairs is inferred by the > I/O standard. =A0Locating both pins is redundant because there > is only one possible I/O pairing. =A0Just make sure you reserve > the negative pins... Oops, didn't see the other questions... The LVDS I/O standard is called LVDS25 (at least for ECP and ECP2). The easiest way to set your IO standards is using the spreadsheet view in the Design Planner (Pre-Map). In the IO Standard column you can right click an item and get a drop-down list of choices. Regards, GaborArticle: 139360
Hi, Thank you for these replies. However, I think I am missing something in the understanding I had of a PLL. I thought that having a -3dB bandwith for the loop filter of 45 kHz would have implied that a glitch of 100 ns could be filtered out. Unfortunatly I cannot add easily a high frequency clock as mentionned as we are trying to limit the number of possible sources of spurious signals in the system. Best regards, JFArticle: 139361
> In place of a typical phase detector, I am using the count of samples > in the FIFO to control the DCO which drives the output clock. =A0Data is > clocked into the FIFO using the reference (input) clock. =A0I have an > integrator between the data count and the DCO phase step input. =A0The > data count is also offset so that it is zero when at the set point. > > I am having trouble understanding how to model this design. =A0Is there > a unique name for this sort of circuit? =A0At first I was thinking it > was a frequency locked loop (FLL), but then I realized that the data > count works the same as a phase detector by integrating the difference > in frequency of the two signals, it just has a granularity of 1 cycle > and does not wrap around like typical phase detectors do. =A0So should I > be using the same model for this as I would use for a conventional PLL > using a standard phase detector? > > I am having trouble getting the circuit to lock in quickly without > overshoot and hold lock as the frequency shifts. =A0I believe I need to > add a proportional element to the feedback loop. =A0I am also > considering using different coefficients when the loop is locked and > when not locked. > > Am I making this hard and it just needs to be treated like any other > PLL? It's like a usual PLL but without the wraparound of the PD at 2pi. There is no granularity of 1 Cycle, as long as the fill indicator is not synchronized to any clock. Add a proportional value in your loop, have a look at how you synchronize the fill indicator.Article: 139362
On Mar 27, 9:32 am, gabor <ga...@alacron.com> wrote: > On Mar 27, 9:03 am, jfh <jfhas...@club-internet.fr> wrote: > > > Hi, > > > We are working on a project involving the Igloo part from Actel. We > > have a 20 MHz clock which may present a stable logic state (either '1' > > or '0') for up to 150 ns. We don't expect this event to occur very > > often (not more than once per second). We were thinking of using the > > PLL of the Igloo part to filter out this unnwanted state of the clock. > > The characteristics of the PLL are up to 45kHz loop bandwidth (seen in > > the datasheet). We did a test on an Igloo dev kit (icicle) and the > > Igloo PLL looses lock. The unwanted event is repeated every 3 ms and > > lasts 150 ns.The loss of lock is very fast and just before the lock > > comes back the output clock from the PLL disappears for a few hundred > > ns. How come regarding the characteristics of the PLL ? Any ideas ? > > > Best regards, > > > JF > > A standard PLL attempts to lock continuously to the input signal. > So even if the clock comes back at the same phase after the event, > the PLL will have slewed its VCO significantly during the event, > causing the loss of lock. You can try to compensate for this by > reducing the filter bandwidth. However if you know when the clock > losses will occur the ideal approach is to use a PLL with hold > capability, like those used in the AD988x Analog Flat Panel > interface chips from Analog Devices. Those PLL's can "coast" > during vertical sync, essentially shutting off the feedback loop > while the horizontal sync is interrupted. > > I'm not familiar with the Actel parts, but Lattice FPGA's have > external capacitor pins for their PLL's to allow you to reduce > the filter bandwidth. I'm not sure what PLLs you have used in the past, but every PLL I have worked with has a low pass filter in the feedback loop. This low pass filter is often used to filter out jitter in an incoming clock. So in general, the situation that the OP describes is not unworkable. The question is: what does the rest of the clock signal look like when the stable state is observed? If it is a single pulse (either the high part or the low part) that is missing with the rest of the clock pulses intact, I would expect a PLL to retain lock. Most types of phase detectors will just output a blip which is filtered by the low pass filter resulting in very little change in the PPL ouput frequency. However, if the clock changes phase at the discontinuity wrt the PLL output, the phase detector output is offset and the PLL output will shift frequency until the phase is realigned. Even then, I would expect the PLL to be able to handle this if it does not see this as a loss of lock which obviously is happening. When these "stable logic states" occur, does the clock shift phase as well as miss a pulse? If you have a clock that is a higher frequency than the 20 MHz clock, you could design your own digital PLL to generate the output clock. Typically a DPLL will have jitter in the output clock of one period of the controlling clock. I don't know if this would be acceptable to your application or not. You can use the Actel PLL to boost the frequency of the controlling clock to reduce the jitter in the output clock. RickArticle: 139363
On Fri, 27 Mar 2009 08:04:43 -0700 (PDT) rickman <gnuarm@gmail.com> wrote: > I'm sure I'm not the first person to control an oscillator by the > amount of data in a FIFO, but I haven't found a reference to this > design which is similar to a PLL. > > In place of a typical phase detector, I am using the count of samples > in the FIFO to control the DCO which drives the output clock. Data is > clocked into the FIFO using the reference (input) clock. I have an > integrator between the data count and the DCO phase step input. The > data count is also offset so that it is zero when at the set point. > > I am having trouble understanding how to model this design. Is there > a unique name for this sort of circuit? At first I was thinking it > was a frequency locked loop (FLL), but then I realized that the data > count works the same as a phase detector by integrating the difference > in frequency of the two signals, it just has a granularity of 1 cycle > and does not wrap around like typical phase detectors do. So should I > be using the same model for this as I would use for a conventional PLL > using a standard phase detector? > > I am having trouble getting the circuit to lock in quickly without > overshoot and hold lock as the frequency shifts. I believe I need to > add a proportional element to the feedback loop. I am also > considering using different coefficients when the loop is locked and > when not locked. > > Am I making this hard and it just needs to be treated like any other > PLL? > > Rick Sure sounds like it's just a phase detector. That said, unless every clock of the input clock is putting a sample into the FIFO you start giving away gain pretty rapidly. In a digital feedback loop, gain=bits=ability to treat things as mathematically perfect rather than mucking around in non-linear quantization effects. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 139364
Hi, Thank you for your replies. I used the method proposed by gabor. and it didn't work for me. everything went well and green in ISE and when i "update Bitstream with Processor Data" it generates a messed bitfile and it doesn't work. May be i'm doing something wrong ... In addition to that, passing from XPS to SDK or ISE is a one way operation, i can't go back to xps ... Any tips ? I think i will use command line flow too. Are you using Xflow ? Any example , advices .. Best Regards, Hassen.Article: 139365
Hi, Indeed I was expecting the low pass filter to handle the issue. However, we don't know what the phase of the clock will be when it "disappears" for a short period in the final application. In the test we made on the Actel dev kit we used a locally generated 20 MHz clock. We input it in the PLL of the Igloo part and every 3 ms, we remove 2 (100 ns) input clock periods with some FPGA logic therefore the phase of the clock when it reappears is the same as when it disappeared so the phase detector should not generate a large signal to the low pass filter. Best regards, JFArticle: 139366
On Fri, 27 Mar 2009 08:19:43 -0700 (PDT), John <sampson164@gmail.com> wrote: >On Mar 27, 11:04 am, rickman <gnu...@gmail.com> wrote: >> I'm sure I'm not the first person to control an oscillator by the >> amount of data in a FIFO, but I haven't found a reference to this >> design which is similar to a PLL. >> >> In place of a typical phase detector, I am using the count of samples >> in the FIFO to control the DCO which drives the output clock. Data is >> clocked into the FIFO using the reference (input) clock. I have an >> integrator between the data count and the DCO phase step input. The >> data count is also offset so that it is zero when at the set point. >> >> I am having trouble understanding how to model this design. Is there >> a unique name for this sort of circuit? At first I was thinking it >> was a frequency locked loop (FLL), but then I realized that the data >> count works the same as a phase detector by integrating the difference >> in frequency of the two signals, it just has a granularity of 1 cycle >> and does not wrap around like typical phase detectors do. So should I >> be using the same model for this as I would use for a conventional PLL >> using a standard phase detector? >> >> I am having trouble getting the circuit to lock in quickly without >> overshoot and hold lock as the frequency shifts. I believe I need to >> add a proportional element to the feedback loop. I am also >> considering using different coefficients when the loop is locked and >> when not locked. >> >> Am I making this hard and it just needs to be treated like any other >> PLL? >> >> Rick > >I call it a "rate-locked loop", but I'm not sure there is an official >name. Other keywords include "elastic store" or "elastic buffer". > >You can write loop equations and get response curves. If the buffer >length is B, the error is (x - B/2)/(B/2) where x is how much is in >the buffer. The feedback is through a standard lead-lag filter, the >output of which controls the buffer's empty rate. > >John Also sometimes called a "delay-locked loop". Eric Jacobsen Minister of Algorithms Abineau Communications http://www.ericjacobsen.org Blog: http://www.dsprelated.com/blogs-1/hf/Eric_Jacobsen.phpArticle: 139367
On Mar 27, 7:04=A0pm, hassen.kar...@gmail.com wrote: > Hi, > > Thank you for your replies. > I used the method proposed by gabor. and it didn't work for me. > everything went well and green in ISE and when i "update Bitstream > with Processor Data" it generates a messed bitfile and it doesn't > work. May be i'm doing something wrong ... In addition to that, > passing from XPS to SDK or ISE is a one way operation, i can't go back > to xps ... Any tips ? > > I think i will use command line flow too. Are you using Xflow ? Any > example , advices .. > > Best Regards, > Hassen. ISE -> new project ->New File select XPS system start XPS create syste close XPS update bitstream in ISE works. AnttiArticle: 139368
On 27 Mrz., 15:13, Antti <Antti.Luk...@googlemail.com> wrote: > I wonder if there are better candidates for each bit-width category > microblaze clone could be considered for 32, but i would rather leave > such clones out from the table If you include an 8080 clone, you can also include a microblaze clone. AFAIK the open cores microblaze is a cleanroom reimplementation of the microblaze ISA. KoljaArticle: 139369
"jfh" <jfhasson@club-internet.fr> wrote in message news:6bdd6241-a24d-4e7b-aa45-59356f88d8b4@42g2000yqk.googlegroups.com... > Hi, > > We are working on a project involving the Igloo part from Actel. We > have a 20 MHz clock which may present a stable logic state (either '1' > or '0') for up to 150 ns. We don't expect this event to occur very > often (not more than once per second). We were thinking of using the > PLL of the Igloo part to filter out this unnwanted state of the clock. > The characteristics of the PLL are up to 45kHz loop bandwidth (seen in > the datasheet). We did a test on an Igloo dev kit (icicle) and the > Igloo PLL looses lock. The unwanted event is repeated every 3 ms and > lasts 150 ns.The loss of lock is very fast and just before the lock > comes back the output clock from the PLL disappears for a few hundred > ns. How come regarding the characteristics of the PLL ? Any ideas ? > Perhaps what you are seeing are the characteristics of the lock detector.Article: 139370
On Mar 27, 7:13=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > i know has been discussed before ;) > > if we leave out the vendor supplied ones (including open source like > mico32) and the large ones, then my current list: The requirements for being on the list appear underspecified. For instance, it does not take performance into account. My own MIPS clone YARI is not tiny at ~ 5,000 LE (LUT4 + FF), but is certainly one of the faster open source cores out there and it (being MIPS compatible) has fantastic tool support. Does ZPU have a debugger? A Linux port? A JAVA jit? TommyArticle: 139371
On Mar 28, 2:13=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > i know has been discussed before ;) > > if we leave out the vendor supplied ones (including open source like > mico32) and the large ones, then my current list: Why leave the Open-Source ones off the list ? - surely they should be there, as important reference points ? -jgArticle: 139372
filter001@desinformation.de wrote: > It's like a usual PLL but without the wraparound of the PD at 2pi. > There is no granularity of 1 Cycle, as long as the fill indicator is > not synchronized to any clock. Hmmm, this comment makes me think this has all been hashed out under the topic of "Frequency locked loops". Similar to a PLL, but there is no wraparound of the freq. detector. JonArticle: 139373
On Mar 27, 10:38=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Mar 28, 2:13=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > Hi > > > i know has been discussed before ;) > > > if we leave out the vendor supplied ones (including open source like > > mico32) and the large ones, then my current list: > > Why leave the Open-Source ones off the list ? > - surely they should be there, as important reference points ? > > -jg sorry, i did mean vendor provided open-source one (the onlysuch one bein mico32) and as of clean room microblaze vs i8080 clone, i think i did think i8080 clone is more safe and clean then microblaze clones and i was considering MIPS if allowing more resource hungry implementations AnttiArticle: 139374
Does anyone know where I could find a xc6200 fpga? I would like to experiment things on reconfigurable computing and it seems to be the only fpga with a complete documentation to be fully dynamically reconfigurable. Thanks. Thomas
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