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On Mon, 29 Dec 2008 16:06:40 -0800, "Teece" <tom_cip_11551_nospam@hotmail.com> wrote: >if (signal1(0) xor signal2(0)) then >........ > >however, this gives a compiler error because xor wishes to return a Boolean >and signal1 and signal2 are not of type Boolean. I did try changin the type >of Signal1 and Signal2 but that did not get rid of the compiler error. Others have given you the solution. But just to be clear on why this does not work: xor does NOT "wish to return a boolean"; it operates correctly on std_logic and returns a std_logic. (If it was applied to two booleans it would return a boolean). But "if ... then" MUST have an expression which returns a boolean. (signal1(0) xor signal2(0)) = '1' is such an expression. Find the source for the std_logic_1164 package (for example, in your Xilinx ISE install dir, under vhdl/IEEE/std_logic_1164 ) which contains the definition of all the functions you can use with std_logic. - BrianArticle: 137176
Mike Treseler wrote: > US Labor statistics > > http://www.bls.gov/oco/ocos095.htm > > says there were > 196,000 professional musicians and singers in the US in 2006 > > Let's guess that 30,000 are guitarists > 10,000 use an effects box > > May not need that asic. For every "pro" musician there are gazillions of weekend warriors that buy effect boxes. There is sizeable market for this sort of thing. But I agree an asic NRE does not make economic sense when you can buy something like an analog devices SHARC DSP that can give you 300 million MACs/sec for under $10. -JeffArticle: 137177
FPGA/CPLD Design Group on LinkedIn Group for People Involved In the Design and Verification of FPGA's, other Programmable Logic , and CPLD's to Exchange Idea's and Techniques. You should have FPGA / CPLD Design / Verification on your Profile. (The focus is more on FPGA/CPLD in the product as opposed to FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC and other HDL's as well. Vendors included: Xilinx, Altera, Actel, Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn can be a way to get technical questions answered. It can also be a way to meet contacts with expertise in other domains of knowledge other than your own. Additionally, many career enhancing contacts, and mentors can potentially found especially if one is at a smaller company that lacks the resources for extensive internal networking. http://www.cpldfpga.com https://sites.google.com/site/fpgacpldgroup/ (Tip - when first signing up on linkedin cut-paste from a resume)Article: 137178
On Dec 30, 4:24=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > FPGA/CPLD Design Group on LinkedIn > > Group for People Involved In the Design and Verification of FPGA's, > other Programmable Logic , and CPLD's to Exchange Idea's and > Techniques. You should have FPGA / CPLD Design / Verification on your > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn > can be a way to get technical questions answered. It can also be a way > to meet contacts with expertise in other domains of knowledge other > than your own. Additionally, many career enhancing contacts, and > mentors can potentially found especially if one is at a smaller > company that lacks the resources for extensive internal networking. > > http://www.cpldfpga.com > > https://sites.google.com/site/fpgacpldgroup/ > > (Tip - when first signing up on linkedin cut-paste from a resume) you posted this info already on aug 27, i believe AnttiArticle: 137179
Hello, I wanted to order boards from Digilent, but their prices brutally raised between Sunday and today. They have introduced 'Academic prices' which are the former regular prices, and new regular prices are 20 to 40 USD higher (which is a huge increase in percentage) :-( Any reason for that ? Goodbye, Stéphane.Article: 137180
On Dec 30, 4:50=A0pm, St=E9phane Goujet <stephane.n...@wana.invalid> wrote: > Hello, > > =A0 I wanted to order boards from Digilent, but their prices brutally > raised between Sunday and today. They have introduced 'Academic prices' > which are the former regular prices, and new regular prices are 20 to 40 > USD higher (which is a huge increase in percentage) :-( > =A0 Any reason for that ? > > Goodbye, > =A0 St=E9phane. reason? I know the result :) never ever considering buying their products hm.. i did happen to write about one of their products in the december issue http://groups.google.com/group/antti-brain/files?hl=3Den the reason for that was they they labeled the + - on the Power plug wrong on Xilinx S3A starter board what caused 2 days delay for an project AnttiArticle: 137181
Antti wrote: > On Dec 30, 2:11 pm, Lorenz Kolb <lorenz.k...@uni-ulm.de> wrote: >> Antti wrote: >>> Xilinx QUIZ 2008 >>> system setup >>> * Xilinx Virtex FPGA >>> - DDR2 memory >>> - SFP sockets on MGTs >>> - Gigabit TEMAC with SG DMA >> Ok, what I can remember from running in Virtex-4FX issues (information >> from about one year ago, so maybe that has changed meanwhile) with ethernet: >> >> SG-DMA used to be buggy. >> >> HardTemac-Version used to be Silicon-Revision dependend (and was not >> selected properly automatically) >> >> Maybe that helps a little. >> >> Regards, >> >> Lorenz > > Thank you, well it not very encouraging :( > the system uses > > LL_TEMAC_SGMII_V1_00a (user modified!) > and MPMC2 > #define GUI_VERSION 1.9 > #define PCORE_VERSION _v2_10_a > #define pcorename mpmc2_ddr2_pnncc_200mhz_x16_mt47h16m16_3 Ah, sorry, I'm out. Until now I only used the old fashioned way (PLB_Temac + HardTemac) as I didn't need the extra performance of a MPMC, sorry. But please also check Your version of the hard_temac IP-Core: e.g. for the silicon-revision of our ML403s we needed BEGIN hard_temac PARAMETER INSTANCE = hard_temac_0 PARAMETER HW_VER = 3.00.a though EDK encouraged us to use 3.00.b instead... Good luck, anyway, LorenzArticle: 137182
St=E9phane There have been big changes in the board making economics in the last few months and it may be they are simply passing on some of these costs to what they see as the least cost sensitive part of their customer base. A big driver has been the rise in energy and commodity costs which has also knocked on to everything from pcbs to chips. It's also possible they are seeing a volume reduction in their home market. I know we have seen a lot less sales in the US even through we are getting cheaper by the day with currency shifts. A reduction in volume could be a lot of reason to increase sale price to recoup extra unit costs on lower volumes. If they manufacture in China it could also be the rise in manufacturing labour costs in that country. Which of these reasons is the answer I don't know. It's maybe simply they wish to make more money but that will need someone from Digilent to answer. John Adair Enterpoint Ltd. On 30 Dec, 14:50, St=E9phane Goujet <stephane.n...@wana.invalid> wrote: > Hello, > > =A0 I wanted to order boards from Digilent, but their prices brutally > raised between Sunday and today. They have introduced 'Academic prices' > which are the former regular prices, and new regular prices are 20 to 40 > USD higher (which is a huge increase in percentage) :-( > =A0 Any reason for that ? > > Goodbye, > =A0 St=E9phane.Article: 137183
Antti wrote: > the reason for that was they they labeled the + - > on the Power plug wrong on Xilinx S3A starter board > what caused 2 days delay for an project This proves the harmfulness of reading labels and such things :-) Goodbye, Stéphane.Article: 137184
RealInfo wrote: > Hi all > > I have a litle dream to turn a FPGA based design into a real ASIC so I can > sell this ASIC in the market . > This is an audio processing design aimed at the guitar effects market. > We have a couple nice little analog signal processors (with a fair amount of digital control logic, too) that we have made in the 0.5 um AMI CMOS process through MOSIS. A minimum run of 40 of these chips costs us about $11,000. A larger run of a couple hundred parts runs to about $45,000. Remember that not all of these components are good, although the yield has been remarkable, over 90%! Perhaps your DSP, all-digital design could fit in a smaller die, and therefore cost a bit less. One thing to watch out for is that with the smaller feature size processes, the mask costs go up exponentially. If you make 100K parts, that is not a concern, if you make 1000, it will KILL you! I doubt you can find anyone that can put a single waffle tray of parts on your desk cheaper than MOSIS. But, they won't layout the chip for you. There are various packages that can do the layout, such as Mentor, Cadence, etc. Note that there are restrictions on what can be done with the educational versions of their software, specifically, you can't use the educ. version to make commercial chips! Also, note that there are REAL risks in ASIC design. Digital stuff is "fairly" straightforward, but you still need rigorous and conservative design rules, and take all representations from the foundry with a large grain of salt, or you could end up with a pile of sparkling trinkets instead of functional chips. Why do you think you can't sell an FPGA design? I've been selling boards with FPGAs in them for years to a niche market, and certainly have NO plans to go ASIC on them! JonArticle: 137185
On Dec 30, 9:48=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > On Dec 30, 4:24=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > > > > > FPGA/CPLD Design Group on LinkedIn > > > Group for People Involved In the Design and Verification of FPGA's, > > other Programmable Logic , and CPLD's to Exchange Idea's and > > Techniques. You should have FPGA / CPLD Design / Verification on your > > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > > Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn > > can be a way to get technical questions answered. It can also be a way > > to meet contacts with expertise in other domains of knowledge other > > than your own. Additionally, many career enhancing contacts, and > > mentors can potentially found especially if one is at a smaller > > company that lacks the resources for extensive internal networking. > > >http://www.cpldfpga.com > > >https://sites.google.com/site/fpgacpldgroup/ > > > (Tip - when first signing up on linkedin cut-paste from a resume) > > you posted this info already on aug 27, i believe > > Antti I think that was in another group, not here... RickArticle: 137186
On Dec 31, 8:38=A0am, rickman <gnu...@gmail.com> wrote: > On Dec 30, 9:48=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On Dec 30, 4:24=A0pm, cpld-fpga-asic <cpld.fpga.a...@gmail.com> wrote: > > > > FPGA/CPLD Design Group on LinkedIn > > > > Group for People Involved In the Design and Verification of FPGA's, > > > other Programmable Logic , and CPLD's to Exchange Idea's and > > > Techniques. You should have FPGA / CPLD Design / Verification on your > > > Profile. (The focus is more on FPGA/CPLD in the product as opposed to > > > FPGA's solely as a path to an ASIC) VHDL / Verilog / ABLE / SystemC > > > and other HDL's as well. Vendors included: Xilinx, Altera, Actel, > > > Lattice, Atmel, QuickLogic, Tabula, Silicon Blue, Mentor, Cadence, > > > Synopsys, Aldec, NI, Altium, and Many Others. Networking on LinkedIn > > > can be a way to get technical questions answered. It can also be a wa= y > > > to meet contacts with expertise in other domains of knowledge other > > > than your own. Additionally, many career enhancing contacts, and > > > mentors can potentially found especially if one is at a smaller > > > company that lacks the resources for extensive internal networking. > > > >http://www.cpldfpga.com > > > >https://sites.google.com/site/fpgacpldgroup/ > > > > (Tip - when first signing up on linkedin cut-paste from a resume) > > > you posted this info already on aug 27, i believe > > > Antti > > I think that was in another group, not here... > > Rick i think here too he is posting the same post on many newsgroups... AnttiArticle: 137187
I'made a VHDL file for a one-channel serial DAC. When the host CPU writes to a specific address, the FGPA sends that data serially via 4 lines (CS, SCK, SI, LDAC). In addition to that 4 output ports, it uses several input ports from the host, several internal signals and at least one common-use internal signal. Now I need a second DAC channel. All is much the same, except: 1. new triggering write address. 2. new copy of internal signals. 3. new output pins. How do I do that? As you can probably see from the subject, I have no clue what I am searching for.. something to do with the COMPONENT, i guess.. A link to a example would be nice. I've tried using "Design Utilites, View HDL Instantiation Template". Is that the way to go? That only makes the list of ports used, how can I then change the write address, and the names of internal signals? I could, of course, just copy&paste and search&replace, but maybe I should learn something ;) P.S. Will there be any simulation problems? Happy New Year!Article: 137188
aleksa wrote: > I've tried using "Design Utilites, View HDL Instantiation Template". > Is that the way to go? That only makes the list of ports used, how can > I then change the write address, and the names of internal signals? In the top entity you define signals for all ports, e.g. data1, data2, trigger1, trigger2 etc. Then you connect it to both instances. The output pins are ports in your top entity for the FPGA pins. Finally you write a multiplexer in your top entity, something like this: on rising clock edge in some process: trigger1 <= false; trigger2 <= false; if address = DAC1 then data1 <= dataBus; trigger1 <= true; elsif address = DAC2 then data2 <= dataBus; trigger2 <= true; end if; -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 137189
Hi Antti,
Try disabling cache if it is enabled.
Try increasing the stack.
Also, take a look at the old GSRD reference design using MPMC and LL_TEMAC.
It used to work quite reliably but it was long time ago since I tried it
last time.
/Mikhail
From rgaddi@technologyhighland.com Wed Dec 31 10:05:12 2008
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Date: Wed, 31 Dec 2008 10:05:12 -0800
From: Rob Gaddi <rgaddi@technologyhighland.com>
Newsgroups: comp.arch.fpga
Subject: Xilinx Timing Constraint Woes
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Got a problem that's been kicking me around for a couple of days
now, and CGD.PDF is it's usual helpful self.
I've got a Spartan 3 design with a signal coming in on an LVDS pair
named VL_P<1> and VL_N<1>, the output net from which is called
vern_trip_n<1>.
vern_trip_n<1> goes on to drive, along with several timing uncritical
things, two LUTs that drive nets flop_clr<0> and flop_pre<0>. These
two nets are asynchronous clear and preset, respectively for the
I/O cell output flop that drives pin OUTPUT<0>.
I'm trying to constrain the raw prop delay between a change on the
VL_P/VL_N pin pair and a change on the OUTPUT pin. However, no matter
what I try, the place-and-route tool winds up ignoring my constraint.
At the moment I've thrown out most of the other things I've tried
along the way, and I'm back down to just having the following in this
section of the UCF file:
-----------------------------------------
enable=reg_sr_o;
enable=reg_sr_r;
TIMEGRP "VERN_FALL" = PADS("VL_*") ;
NET "OUTPUT<*>" TNM_NET = "CHANNEL_OUT";
TIMESPEC TS_OUTPUT = FROM "VERN_FALL" TO "CHANNEL_OUT" 8 ns;
-----------------------------------------
And still I get the result that: WARNING:Timing:3223 - Timing constraint
TS_OUTPUT = MAXDELAY FROM TIMEGRP "VERN_FALL" TO TIMEGRP "CHANNEL_OUT" 8
ns; ignored during timing analysis.
Anyone know how to convince PAR that I wouldn't have asked if I hadn't
meant it?
Thanks, all, and happy new year.
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 137190Hi, I have a chip top which has an 8-bit output "out[7:0]". I am implementing it on a BASYS board which uses Xilinx Spartan 3E. I would like to see the 8-bit output on the seven segment LED display. How can I do this? Do I need to add any additional Verilog code to do this? Please help. Thanks,Article: 137191
Antti <Antti.Lukats@googlemail.com> wrote: > PC sends very little amount of small UDP > packets that are responded by FPGA I'm wondering if greatly increasing the volume of packets going from the PC to the FPGA would make the problem reproduce faster, etc. Do you have the flexibility to change the PC side to increase or even flood it with status checks or some noop command? G.Article: 137192
john_griessen wrote:
>> RealInfo <therighti...@yahoo.com> wrote:
>>> I have a litle dream to turn a FPGA based design into a real ASIC
>=20
> viasic.com is another low cost metal mask programmable ASIC vendor.
I did not know this company so I went there and downloaded a PDF,
that writes :
"
Available processes include:
=B7 TSMC 90nm
=B7 ST 0.13
=B7 TSMC 0.13
=B7 DongBuAnam 0.13
=B7 IBM 0.13 Rad Hard
=B7 AMS 0.35 4ML
=B7 Sandia 0.35 Rad Hard
"
I also read on another page :
"
Two mask high density configurable logic fabric built on
silicon proven standard cells that can be used as an
embedded block on an SOC or as a full chip fabric for
building structured ASICs.
"
So this seems (to me) to be just a provider of large standard
multi-purpose logic cells...
By coincidence, I discovered another company yesterday
that provides "via-layer electron-beam programmed FPGA-like chips"
(my own interpretation, not theirs) see http://www.easic.com/
They seem to provide the chips, not layouts/designs.
It seems interesting for low-volume ASIC-alike stuff.
I asked for pricing but all the reps are away...
I don't even know if anyone will answer
but their stuff looks interesting.
Happy new year everyone,
> John
yg
--=20
http://ygdes.com / http://yasep.org
Article: 137193
I am trying to use xilinx's fifo core with independent read and write
clocks in one of my modules. A stream of 8-bit data will come to this
module as input from an input port of 8-bit width. In the module data
is shifted from registers a33 -> a32 -> a31 -> fifo1_in ; after fifo1
gets sufficient writes, its rd_en is asserted so that data shifts from
fifo1_out -> a23 -> a22 -> a21 -> fifo2_in (at this time data still
gets shifted from a33 -> a32 ....); after fifo2 gets sufficient data,
rd_en of fifo2 is asserted and data shifts from fifo2_out -> a13 ->
a12 -> a11 too.
Shifting rate is same as the input data rate which is a few times
slower than the clock used for the module and for fifos.
At present I'm using same clock for both rd and wr for both fifos
although I may require diff. clocks later on.
I need the values of all a's (9 of them) for some other module so in
this module I have 9 w's (like w11 , w12, ... w33) as output ports.
Then there are concurrent statements in the architecture as:
w11 <= a11; .... w33 <= a33;
I had a successful behavioral simulation of the design with modelsim
invoked from xilinx's ise9.2i. However when trying to do a postmap
simulation, ise gave some errors and could not synthesize. Errors were
for signals w13 and w23 and it complains about the multiple-source for
these signals. One of the errors :
Error:Xst:528 - Multi-source in Unit <moving_window> on signal
<w23<4>>
Sources are:
Output port RAMB16BWER:DOB16 of instance <windowing1/fifo1/BU2/U0/
gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/blk_mem_generator/
valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram>
Signal <windowing1/w23<4>> in Unit <moving_window> is assigned to GND
I don't understand how w23 is being assigned to GND and therefore why
multi-source here.
Some of the relevant parts of the code:
architecture behav of moving_window is
-- component declarations
--fifocore generated form coregen
....
...
--signal declarations
....
signal fifo1_out: std_logic_vector(fifo_width
- 1 downto 0);
signal fifo2_out: std_logic_vector(fifo_width
- 1 downto 0);
signal a11, a12,a13: std_logic_vector(FIFO_WIDTH - 1
downto 0);
signal a21, a22,a23: std_logic_vector(FIFO_WIDTH - 1
downto 0);
signal a31, a32,a33: std_logic_vector(FIFO_WIDTH - 1
downto 0);
begin
-- component instantiations:
fifo1 : fifocore
port map (
din => a31,
..
..
dout => fifo1_out,
...
fifo2 : fifocore
port map (
din => a21,
rd_clk => clk,
...
...
dout => fifo2_out,
....
--concurrent signal assignments
w11 <= a11;
w12 <= a12;
..
w33 <= a33;
main: process(clk) is
begin
if rising_edge(clk) then
if reset = '1' then
a11 <= (others => '0'); a12 <= (others => '0'); a13 <=
(others => '0');
a21 <= (others => '0'); a22 <= (others
=> '0'); a23 <= (others => '0');
a31 <= (others => '0'); a32 <= (others => '0'); a33 <=
(others => '0'); ....
else
if data_valid = '1' then --data_valid is input to the module that
indicates new data available at input
a33 <= d_in; a32 <= a33; a31 <= a32;
a23 <= fifo1_out; a22 <= a23; a21 <= a22;
a13 <= fifo2_out; a12 <= a13; a11 <= a12;
... -- other logic for asserting and deasserting rd_en and wr_en
signals for fifo cores .....
.... -- there are no assignments
for a's and w's here.
end process;
end behav;
Article: 137194Happy new year, A seven segment display can show the status of 4 bits by displaying a digit, or it can display 8 bits by connecting each bit to one segment plus the decimal point if the display has one. That would be very hard to interpret, but if you are a 7 segment savant, you might be able to pull it off. Otherwise, you might think about displaying two 4 bit digits in succession. It would need to show one digit, a brief delay and the second digit, followed by a longer delay before repeating. Think you can work with that? Rick On Dec 31, 4:07=A0pm, Digi Suji <digis...@gmail.com> wrote: > Hi, > > I have a chip top which has an 8-bit output "out[7:0]". I am > implementing it on a BASYS board which uses Xilinx Spartan 3E. I would > like to see the 8-bit output on the seven segment LED display. How can > I do this? > > Do I need to add any additional Verilog code to do this? Please help. > > Thanks,Article: 137195
Hello there, I've just migrated from Xilinx to Altera. Using the NIOS IDE I've created a system with working SW. I would like to program the on-board EPCS flash so on power up the FPGA is programed with the right HW and SW. I read that I need to convert the sof file to jic. OK, but what about the software - as I noticed the sof only contains the HW. what to do? how do I create a sof file that contains both the HW and SW? thanks alot. GuyArticle: 137196
I have tried to classify a few different ways to optimize a design
for an FPGA. I have tried to keep the categories fairly general
without going into too much details. Comments (both positive and
negative) would be appreciated.
1 Pipelining
* A must in almost any FPGA design. Relatively cheap to do since
flip-flops are usually abundant. This is not very FPGA specific
though, but usually an ASIC design doesn't have to be pipelined
as much as an FPGA design is.
2 Utilizing FPGA resources efficiently
2.1 Change the design to use as much of the FPGA LUTs as possible.
* For example, a 32-bit adder/subtracter takes up the same amount
of space as a plain 32-bit adder. Sometimes you might have to
instantiate LUTs, flip-flops, carry-chains, etc manually to
do this.
2.2 Utilizing memories efficiently.
* For example, if your design will be more efficient by utilizing
both ports of a block RAM you should probably do so. Using
distributed memories, shift registers, etc efficiently.
2.3 Utilizing DSP blocks efficiently
* Change the architecture of your design to be able to take
maximum advantage of the DSP blocks. For example, if you have a
DSP processor with 4 accumulation registers this will not map
very well to a Virtex-4 DSP48 block which only have one accumulation
register. (Although this can be fixed by using result forwarding and
utilizing a register file outside the DSP48 block.)
2.4 Utilizing other embedded FPGA resources
* Embedded processors, serializers/deserializers, DLLs/PLLs, etc
3. Manual floorplanning
* Either through RLOCs or graphical tools
4. Manual routing
* Not very common but can be a powerful tool to meet timing in extreme
situations.
5. Partial reconfiguration
* Not very common yet but has a potential to save a lot of area if
certain parts of a design are not needed all the time.
6. <Insert your comment here> :)
Have I forgotten something very important here?
And by the way, is there any definitive book one should read to learn
more about how to optimize a design for an FPGA? I have looked at many
FPGA books but most books only seem to cover fairly introductory
material.
I have looked at for example "Digital Signal Processing with Field
Programmable Gate Arrays (Signals and Communication Technology)" but
this book doesn't really have that much FPGA material. (Although it has
a lot of nice DSP material.)
Another book, "Advanced FPGA Design" by Steve Kilts was a decent text for
intermediate designers but I'm not sure I would have called it "Advanced".
At the moment I have probably had more use of some of the postings on this
newsgroup than most of the FPGA related books I have looked at however :)
/Andreas
Article: 137197On Wed, 31 Dec 2008 18:48:36 -0800 (PST), bish <bisheshkh@gmail.com> wrote: On Wed, 31 Dec 2008 18:48:36 -0800 (PST), in comp.arch.fpga you wrote: >I had a successful behavioral simulation of the design with modelsim >invoked from xilinx's ise9.2i. >Error:Xst:528 - Multi-source in Unit <moving_window> on signal ><w23<4>> >Sources are: >Output port RAMB16BWER:DOB16 of instance <windowing1/fifo1/BU2/U0/ >gen_as.fgas/normgen.memblk/bmem.bmg.bmg_inst/blk_mem_generator/ >valid.cstr/ramloop[0].ram.r/v2.ram/dp36x36.ram> >Signal <windowing1/w23<4>> in Unit <moving_window> is assigned to GND > >I don't understand how w23 is being assigned to GND and therefore why >multi-source here. Perhaps applying the Modelsim "Drivers" command to Signal <windowing1/w23<4>> would help trace the problem. - BrianArticle: 137198
On 2009-01-01, valwn@silvtrc.org <valwn@silvtrc.org> wrote: > Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote: >>I have tried to classify a few different ways to optimize a design >>for an FPGA. I have tried to keep the categories fairly general >>without going into too much details. Comments (both positive and >>negative) would be appreciated. > >>1 Pipelining > >>6. <Insert your comment here> :) > > Parallellisation. True, although my intent (which I realize that I did not describe in as much detail as I should have) was to list optimizations that were mostly FPGA specific in contrast to ASIC specific. Parallellism can be used to great effect in both FPGAs and in ASICs. Basically, I am trying to come up with a list of what to do to optimize an FPGA design in contrast to an ASIC design. (Although I realize that both floorplanning and manual routing can be done in an ASIC as well. In fact, I would guess that more ASIC designs than FPGA designs have some sort of floorplanning although I don't have any numbers to support this claim.) /AndreasArticle: 137199
Andreas Ehliar <ehliar-nospam@isy.liu.se> wrote: >I have tried to classify a few different ways to optimize a design >for an FPGA. I have tried to keep the categories fairly general >without going into too much details. Comments (both positive and >negative) would be appreciated. >1 Pipelining >6. <Insert your comment here> :) Parallellisation.
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