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Jon Elson <jmelson@wustl.edu> wrote: (snip) > I know what I was forced to do broke all the digital rules, but it was > necessary to make the analog part work. Maybe not all of them. While most of the modern rules are based on synchronous logic, asynchronous (sometimes called self-timed) logic is still around, with its own, different, rules. -- glenArticle: 152801
In comp.arch.embedded Mark Wills <forthfreak@forthfiles.net> wrote: > In what have congress changed the law? The main ones are: - A move to first to file rather than first to invent (which brings the US into line with most of the rest of the world). - Allowing the USPTOs to set its own fees in a way that in aggregate covers its own costs. - A mechanism to allow thirdparty submission of prior art subsequent to publication of the patent. Unfortunately the bill does almost nothing to combat trolls nor does it get rid of the treble damages on wilful infringement setup. -p -- Paul Gotch --------------------------------------------------------------------Article: 152802
In comp.dsp Paul Gotch <paulg@at-cantab-dot.net> wrote: (snip on patent rule changes) > Unfortunately the bill does almost nothing to combat trolls nor does it > get rid of the treble damages on wilful infringement setup. As I understand it (not very well), though, it does remove the submarine patent. Isn't it now some number of years from filing, instead of from approval? -- glenArticle: 152803
In comp.arch.embedded glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > As I understand it (not very well), though, it does remove the > submarine patent. Isn't it now some number of years from filing, > instead of from approval? That one was fixed through a combination of a 1995 WTO treaty which change the term to start from the day of filing not the day of grant combined with a change in 2000(?) to publish most patents after 18 months rather than keeping them secret until they were granted. Together they mean that there is no benefit in terms of term in pushing the date of issuance into the future and that the patent will almost certainly be published before it is granted. -p -- Paul Gotch --------------------------------------------------------------------Article: 152804
On Oct 24, 3:59=A0pm, rickman <gnu...@gmail.com> wrote: > > ... > > We are still looking for a panelist who is a consultant able to speak > regarding the impact of this new law. =A0Anyone available in the area? I believe he is retired now but John D. Trudell was a knowledgeable and active campaigner against the changes made in 1999, which also favored the corporations at the expense of the individual inventor. His website isn't being maintained, but hopefully he might be willing to participate. http://www.trudelgroup.com/pwars.htmArticle: 152805
An email from some relatives was posted on a similar thread I made on LinkedIn, that confirms he passed away in July as a result of his illness. Sad=85Article: 152806
Hello,i have knowledge of basic vhdl and i have implement a few fundemental programs on digital circuits. Iam very new to FPGA.I want to experiment a complete details of microprocessor design with FPGA using VHDL language.starting with writing the coding.Article: 152807
Hello,i have some idea about vhdl.I want coding of ADC by using counter method on FPGA by using VHDL.. I know the some idea about this program the following process. a) first reset the counter b)the references and analog voltages are equal then gate can be closed.then the the value can be stored in the couters i.e., the value in counter is equavalent to digital value to analog input. I want coding the above two stepsArticle: 152808
Hello, i follow the book Microprocessor design with VHDL by Enoch O.Hwang. I want some reference books and some web address on this topic.Article: 152809
Hallo, I am new in the world of FPGA. I am asked to design he functional flow for a image processing hardware. The hardware i.e FPGA will be used for video decompression . Hence it has to receive the video from the microcontroller and then execute a decompression algorithm . Now I am confused as to how the data (image/ video) will be managed by the FPGA before the decompression algorithm is executed. What are the blocks required in the functional flow . I am assuming there should be some functions required for buffering of data (for data in and out). Can anyone please guide me on how I should go about designing the functional flow? Regards.Article: 152810
>Hello, i follow the book Microprocessor design with VHDL by Enoch >O.Hwang. I want some reference books and some web address on this >topic. > >From a well-known Internet search engine: http://faculty.lasierra.edu/~ehwang/digitaldesign/ --------------------------------------- Posted through http://www.FPGARelated.comArticle: 152811
On Oct 24, 6:20=A0pm, Paul Gotch <pa...@at-cantab-dot.net> wrote: > In comp.arch.embedded Mark Wills <forthfr...@forthfiles.net> wrote: > > > In what have congress changed the law? > > The main ones are: > > - A move to first to file rather than first to invent (which brings the > US into line with most of the rest of the world). > > - Allowing the USPTOs to set its own fees in a way that in aggregate > covers its own costs. > > - A mechanism to allow thirdparty submission of prior art subsequent to > publication of the patent. > > Unfortunately the bill does almost nothing to combat trolls nor does it > get rid of the treble damages on wilful infringement setup. > > -p > -- > Paul Gotch > -------------------------------------------------------------------- ** - A move to first to file rather than first to invent (which brings the ** US into line with most of the rest of the world). Believe it or not, but we need "first to file": it just makes life simpler for everybody, including small guys ** - A mechanism to allow thirdparty submission of prior art subsequent to ** publication of the patent. I can predict exactly what happens: PTO will be flooded with junk "third-party" submissions of "prior art" completely irrelevant to patent claims (There was a bounty prize on invalidating Amazon's "one- click patent" some years ago which produced tons of junk "prior art" and not a single invalidating reference) Poor, poor patent examiners... ** Unfortunately the bill does almost nothing to combat trolls nor does it ** get rid of the treble damages on wilful infringement setup. And who are those evil "trolls" ? Have you seen one ? Are they some PhDs on a loose not employed by corporate monstrosities, just sitting in their basements and filing evil patents on their own ? How can you allow this in America ? Or maybe they are some shrewd investors who buy patents from those PhD and then use those patents to beat the shit out of fat corporate infringers ? And why treble damages for willful infringement should be removed ? To encourage willful infrigement ??? I say: make willfull infringement a criminal offense (Hint: it's awfully hard to prove willful infringement nowadays)Article: 152812
vibha <vibha.rao19@gmail.com> wrote: > I am new in the world of FPGA. I am asked to design he functional flow > for a image processing hardware. The hardware i.e FPGA will be used > for video decompression . Hence it has to receive the video from the > microcontroller and then execute a decompression algorithm . Now I am > confused as to how the data (image/ video) will be managed by the FPGA > before the decompression algorithm is executed. What are the blocks > required in the functional flow . I am assuming there should be some > functions required for buffering of data (for data in and out). I presume functional flow means block diagram. I recommend a systolic array for image processing in FPGA. The buffering should be done on the microcontroller. (Which could be separate, or a soft processor in the FPGA.) It will then send data into the systolic array, and extract results some clock cycles later. The functional flow/block diagram will be the successive stages of the decompression algorithm. -- glenArticle: 152813
On Oct 25, 9:38=A0am, fatalist <simfid...@gmail.com> wrote: > ** - A move to first to file rather than first to invent (which brings > the > ** US into line with most of the rest of the world). > > Believe it or not, but we need "first to file": it just makes life > simpler for everybody, including small guys > Simpler isn't always better. This change makes it possible to patent work done by someone else, with no recourse for the actual inventor. What used to be theft is now legal. This certainly will make things easier for the courts but one obvious consequence is that there will be increased secrecy surrounding any research that might lead to patentable developments. Given the bias toward corporations and globalization displayed by governments lately, I am deeply suspicious of the motives behind any change like those made to the patent law.Article: 152814
On Oct 24, 3:20=A0pm, Paul Gotch <pa...@at-cantab-dot.net> wrote: > In comp.arch.embedded Mark Wills <forthfr...@forthfiles.net> wrote: > > > In what have congress changed the law? > > The main ones are: > > - A move to first to file rather than first to invent (which brings the > US into line with most of the rest of the world). > > - Allowing the USPTOs to set its own fees in a way that in aggregate > covers its own costs. > > - A mechanism to allow thirdparty submission of prior art subsequent to > publication of the patent. > > Unfortunately the bill does almost nothing to combat trolls nor does it > get rid of the treble damages on wilful infringement setup. > > -p > -- > Paul Gotch > -------------------------------------------------------------------- Unfortunately the underlying system is still bankrupt. Most of the creative people I know were burned out long ago over the way corporations treat inventions and patents as just another perk to hand out to suits. If anything I see the legislation as strengthening the potential for abuse. RickArticle: 152815
On Mon, 24 Oct 2011 22:58:59 -0700, VIJAY KUMAR wrote: > Hello,i have some idea about vhdl.I want coding of ADC by using counter > method on FPGA by using VHDL.. I know the some idea about this program > the following process. > a) first reset the counter > b)the references and analog voltages are equal then gate can be > closed.then the the value can be stored in the couters i.e., the value > in counter is equavalent to digital value to analog input. > I want coding the above two steps A single-slope ADC is probably so easy to code that if you know how to write the code to use it, the actual ADC logic is trivial. A dual-slope ADC is nearly so. So, perhaps you should be inquiring as to how to make a single- or dual- slope ADC _work_, then just write the code. -- www.wescottdesign.comArticle: 152816
All, I (and others) only recently were made aware of Peter's passing. Xilinx will respond (soon). We were extremely fortunate to have Peter as an employee, and I am personally quite sad, as he and I edited each others papers, posts, and articles. Not to mention the fun we had here on comp.arch.fpga together. Austin LeseaArticle: 152817
On Oct 20, 12:33=A0am, Suhaib Fahmy <suh...@fahmy.net> wrote: > Those who've been on this newsgroup for any period of time will > remember Peter Alfke, the Xilinx legend, and his infectious > enthusiasm. He was a great help as I got into FPGA design 8 years ago, > as I embarked on the academic track. I met him at a number of > conferences, and he was just as wonderful in person. He gave some real > life to the newsgroup and has been sorely missed since he stopped > posting. > > A tweet that carried the news:https://twitter.com/xilinxtraining/status/1= 26857481812066304 > > Our condolences to his family and friends; he will be sorely missed. > > Suhaib. I think he's the only one who wrote poetry in comp.arch.fpga R.I.PArticle: 152818
On 10/24/2011 03:57 PM, glen herrmannsfeldt wrote: > Jon Elson<jmelson@wustl.edu> wrote: > > (snip) >> I know what I was forced to do broke all the digital rules, but it was >> necessary to make the analog part work. > > Maybe not all of them. While most of the modern rules are based > on synchronous logic, asynchronous (sometimes called self-timed) > logic is still around, with its own, different, rules. Well, when the digital part fires up, I do have a clock, the serial clock for the shift register. As long as that is clean (enough), then there is no problem. This design has been working fine since 2004 or so. JonArticle: 152819
Very sad, a great loss. Peter had so many virtues, but I'll remember his generosity. It never failed, even when he had to explain metastability for the millionth time.Article: 152820
On Oct 25, 10:55=A0am, Rick <richardcort...@gmail.com> wrote: > On Oct 24, 3:20=A0pm, Paul Gotch <pa...@at-cantab-dot.net> wrote: > > > > > > > > > > > In comp.arch.embedded Mark Wills <forthfr...@forthfiles.net> wrote: > > > > In what have congress changed the law? > > > The main ones are: > > > - A move to first to file rather than first to invent (which brings the > > US into line with most of the rest of the world). > > > - Allowing the USPTOs to set its own fees in a way that in aggregate > > covers its own costs. > > > - A mechanism to allow thirdparty submission of prior art subsequent to > > publication of the patent. > > > Unfortunately the bill does almost nothing to combat trolls nor does it > > get rid of the treble damages on wilful infringement setup. > > > -p > > -- > > Paul Gotch > > -------------------------------------------------------------------- > > Unfortunately the underlying system is still bankrupt. Most of the > creative people I know were burned out long ago over the way > corporations treat inventions and patents as just another perk to hand > out to suits. If anything I see the legislation as strengthening the > potential for abuse. > > Rick So is anyone in the Baltimore/Washington area and willing to participate in the panel discussion? This event is being heavily advertised and we are expecting a good turn out. Not only will you get a free lunch, I'll take you kayaking sometime! RickArticle: 152821
On 25 Okt., 07:58, VIJAY KUMAR <jvkphys...@gmail.com> wrote: > Hello,i have some idea about vhdl.I want coding =A0of ADC by using > counter method on FPGA by using VHDL.. I know the some idea about this > program the following process. > a) first reset the counter > b)the references and analog voltages are equal then gate can be > closed.then the the value can be stored in the couters i.e., the value > in counter is equavalent to digital value to analog input. > =A0I want coding the above two steps Hi Vijay, please read a little about delta sigma ADCs. Almost every functional element of these can be done in digital logic and the theory is well described. Only a analog comparator and a RC-Lowpass (as DAC for the reference signal) are needed as external devices. Have a nice synthesis EilertArticle: 152822
On 25 Okt., 10:20, vibha <vibha.ra...@gmail.com> wrote: > Hallo, > > I am new in the world of FPGA. I am asked to design he functional flow > for a image processing hardware. The hardware i.e FPGA will be used > for video decompression . Hence it has to receive the video from the > microcontroller and then execute a decompression algorithm . Now I am > confused as to how the data (image/ video) will be managed by the FPGA > before the decompression algorithm is executed. What are the blocks > required in the functional flow . I am assuming there should be some > functions required for buffering of data (for data in and out). > > Can anyone please guide me on how I should go about designing the > functional flow? > > Regards. Hi, you should have a look at some application notes first. (e.g those available from Xilinx) They even have reference designs that might be useful as a starting point. But what is your real intent? Image processing or video decompression? Or both? Depending on the answer the best approach for your design will be different. To learn about the functional flow, you might read the standards or specifications of the required algorithms. Then you need to develop a hardware oriented approach to implement these functions. It will be different from the straightforward mathematic formulas or programming examples because hardware design is based on a different paradigm. Have a nice synthesis EilertArticle: 152823
hi all. im currently learning FPGAs and having big interesting in it. but the only place i can practice is the uni lab. i wanna practice at home with my own laptop as well. but i dont know which software should i download as im using ubuntu10.4 as my OS. any advices and tips? thx :DArticle: 152824
In comp.arch.embedded fatalist <simfidude@gmail.com> wrote: > Believe it or not, but we need "first to file": it just makes life > simpler for everybody, including small guys I'm arguing for first to file. > I can predict exactly what happens: PTO will be flooded with junk Um rather than the system being flooded with junk patents which are massively costly and time consuming to invalidate afterwards? I've much rather the patents were never awarded in the first place even it it does mean the PTO have to do a lot of sifting of paper. > And who are those evil "trolls" ? Have you seen one ? Yes. However clearly I can't go into details of specific cases. The system at the moment is setup on the basis of mutally assured destruction. A sues B over infringement B counter sues A over infringment A and B both produce widgets and their businesses will be adversely affected if they have to stop shipping widgets. Therfore A and B settle out of court and sign a cross licensing agreement. Now C, a 'Patent Troll' doesn't have anything widgets to counter sue over all they do is litigate until either their patent is invalidated or they win. The amount of time an money spent on this is such that for many companies it is cheaper to settle and pay royalties on an invalid patent than it is to get it overturned. This is then used as precident to attack other people using the same patent 'look they licensed it it must be valid' pay up or else. > And why treble damages for willful infringement should be removed ? Because the actual effect of this is that you build something and you *do not* do any kind of search to see if you need to license anything and need to pay royalties. If you do do a search and miss something then it's impossibly hard to prove that you didn't find the patent in question and aren't willfully infringing it. -p -- Paul Gotch --------------------------------------------------------------------
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