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On Mon, 31 Oct 2011 15:07:00 -0500, "krw@att.bizzzzzzzzzzzz" <krw@att.bizzzzzzzzzzzz> wrote: >On Mon, 31 Oct 2011 10:02:37 -0700 (PDT), "langwadt@fonz.dk" ><langwadt@fonz.dk> wrote: > >>On 31 Okt., 01:17, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >>wrote: >>> On Sun, 30 Oct 2011 15:09:58 -0700 (PDT), "langw...@fonz.dk" >>> >>> >>> >>> >>> >>> >>> >>> >>> >>> <langw...@fonz.dk> wrote: >>> >On 30 Okt., 21:30, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >>> >wrote: >>> >> On Sun, 30 Oct 2011 10:47:26 -0700 (PDT), "langw...@fonz.dk" >>> >>> >> <langw...@fonz.dk> wrote: >>> >> >On 30 Okt., 18:04, John Larkin >>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> >> >> On Sun, 30 Oct 2011 04:32:51 -0700 (PDT), Michael S >>> >>> >> >> <already5cho...@yahoo.com> wrote: >>> >> >> >On Oct 20, 3:26 am, John Larkin >>> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> >> >> >> On Wed, 19 Oct 2011 21:57:00 +0100, "TTman" <pcw1....@ntlworld.com> >>> >> >> >> wrote: >>> >>> >> >> >> >> The ARM processor will load the FPGA through its SPI port in real >>> >> >> >> >> life, but we're using JTAG to test the PCI Express interface parts >>> >> >> >> >> first, because it's quick and easy. When it works. >>> >>> >> >> >> >> The production system has the ARM boot its code off a serial flash >>> >> >> >> >> chip. Then it reads more of that flash chip and configures the FPGA. >>> >> >> >> >> We'll probably compress the config data, because it's something insane >>> >> >> >> >> like 30 megabits, mostly zeroes. >>> >>> >> >> >> >> John >>> >>> >> >> >> >I thought Quartus will compress for you ??? Do you need all 30 Mbits ??? >>> >>> >> >> >> You don't really get a choice. Every config bit and every RAM bit is >>> >> >> >> in the config file. The vendor's compression usually doesn't help a >>> >> >> >> lot. Since most of the config data is 0's, simple bytewise RLL >>> >> >> >> compression on zeroes helps a lot, 2:1 to as much as 5:1. >>> >>> >> >> >> John >>> >>> >> >> >Methinks, you should try Altera's compression first. You wouldn't get >>> >> >> >5:1, but for low-utilization design with mostly uninitialized internal >>> >> >> >memories you will certainly get 2.5:1 and sometimes even 3:1. >>> >> >> >Besides, unlike vendor's compression, your own compression will not >>> >> >> >make boot process any faster. >>> >>> >> >> In a current Altera design with a GX45, low logic density, the Altera >>> >> >> compression is about 2:1, which isn't bad, 30M bits down to about 15. >>> >>> >> >> The Xilinx compression, at least for Spartans, is much less effective. >>> >>> >> >> I the case where a uP is bit-banging the config into the FPGA, >>> >> >> home-made compression can speed up configuration significantly, >>> >> >> because the bang-out-the-zeroes loop can be very fast. >>> >>> >> >> Not that any of that matters much. Huge serial flash chips are cheap, >>> >> >> and the difference between 3 seconds of config and 8 isn't going to >>> >> >> affect the world much. >>> >>> >> >> John >>> >>> >> >at least for xilinx you wouldn't even have to get the data through the >>> >> >uP, you >>> >> >could just wire the DO and clock on the flash to both the fpga and the >>> >> >uP spi interface >>> >> >and do enough reads from the flash to get through the whole >>> >> >configuration. >>> >> >Theres a sync word in the stream so the fpga knows when the config >>> >> >stream starts >>> >>> >> You assume the sync word only occurs once in the stream. >>> >>> >not really, you should start reading data at the start of the config >>> >it is just that the extra bits and clocks that the fpga will >>> >see when you send a read command etc. to the flash will be ignored >>> >because they come before the sync word >>> >>> ...and if there is more than one sync word? I've seen more than one gigged by >>> this amateur's mistake. >> >>what? you clock a few bytes into the flash start a read, >>then you read how ever many bytes needed for the whole configuration >>the sync word that counts is the first one > >...and if that magic word happens to appear before the "correct" one? It's >*bad* engineering practice to depend on magic words. As I said, I've seem >more than one rookie gigged by such dumbass mistakes. It only takes one wire from the uP to the FPGA to hold the FPGA reset until you're ready to stream the config data. JohnArticle: 152926
On Tue, 01 Nov 2011 08:48:03 -0700, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Mon, 31 Oct 2011 15:07:00 -0500, "krw@att.bizzzzzzzzzzzz" ><krw@att.bizzzzzzzzzzzz> wrote: > >>On Mon, 31 Oct 2011 10:02:37 -0700 (PDT), "langwadt@fonz.dk" >><langwadt@fonz.dk> wrote: >> >>>On 31 Okt., 01:17, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >>>wrote: >>>> On Sun, 30 Oct 2011 15:09:58 -0700 (PDT), "langw...@fonz.dk" >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> >>>> <langw...@fonz.dk> wrote: >>>> >On 30 Okt., 21:30, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >>>> >wrote: >>>> >> On Sun, 30 Oct 2011 10:47:26 -0700 (PDT), "langw...@fonz.dk" >>>> >>>> >> <langw...@fonz.dk> wrote: >>>> >> >On 30 Okt., 18:04, John Larkin >>>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> >> >> On Sun, 30 Oct 2011 04:32:51 -0700 (PDT), Michael S >>>> >>>> >> >> <already5cho...@yahoo.com> wrote: >>>> >> >> >On Oct 20, 3:26 am, John Larkin >>>> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> >> >> >> On Wed, 19 Oct 2011 21:57:00 +0100, "TTman" <pcw1....@ntlworld.com> >>>> >> >> >> wrote: >>>> >>>> >> >> >> >> The ARM processor will load the FPGA through its SPI port in real >>>> >> >> >> >> life, but we're using JTAG to test the PCI Express interface parts >>>> >> >> >> >> first, because it's quick and easy. When it works. >>>> >>>> >> >> >> >> The production system has the ARM boot its code off a serial flash >>>> >> >> >> >> chip. Then it reads more of that flash chip and configures the FPGA. >>>> >> >> >> >> We'll probably compress the config data, because it's something insane >>>> >> >> >> >> like 30 megabits, mostly zeroes. >>>> >>>> >> >> >> >> John >>>> >>>> >> >> >> >I thought Quartus will compress for you ??? Do you need all 30 Mbits ??? >>>> >>>> >> >> >> You don't really get a choice. Every config bit and every RAM bit is >>>> >> >> >> in the config file. The vendor's compression usually doesn't help a >>>> >> >> >> lot. Since most of the config data is 0's, simple bytewise RLL >>>> >> >> >> compression on zeroes helps a lot, 2:1 to as much as 5:1. >>>> >>>> >> >> >> John >>>> >>>> >> >> >Methinks, you should try Altera's compression first. You wouldn't get >>>> >> >> >5:1, but for low-utilization design with mostly uninitialized internal >>>> >> >> >memories you will certainly get 2.5:1 and sometimes even 3:1. >>>> >> >> >Besides, unlike vendor's compression, your own compression will not >>>> >> >> >make boot process any faster. >>>> >>>> >> >> In a current Altera design with a GX45, low logic density, the Altera >>>> >> >> compression is about 2:1, which isn't bad, 30M bits down to about 15. >>>> >>>> >> >> The Xilinx compression, at least for Spartans, is much less effective. >>>> >>>> >> >> I the case where a uP is bit-banging the config into the FPGA, >>>> >> >> home-made compression can speed up configuration significantly, >>>> >> >> because the bang-out-the-zeroes loop can be very fast. >>>> >>>> >> >> Not that any of that matters much. Huge serial flash chips are cheap, >>>> >> >> and the difference between 3 seconds of config and 8 isn't going to >>>> >> >> affect the world much. >>>> >>>> >> >> John >>>> >>>> >> >at least for xilinx you wouldn't even have to get the data through the >>>> >> >uP, you >>>> >> >could just wire the DO and clock on the flash to both the fpga and the >>>> >> >uP spi interface >>>> >> >and do enough reads from the flash to get through the whole >>>> >> >configuration. >>>> >> >Theres a sync word in the stream so the fpga knows when the config >>>> >> >stream starts >>>> >>>> >> You assume the sync word only occurs once in the stream. >>>> >>>> >not really, you should start reading data at the start of the config >>>> >it is just that the extra bits and clocks that the fpga will >>>> >see when you send a read command etc. to the flash will be ignored >>>> >because they come before the sync word >>>> >>>> ...and if there is more than one sync word? I've seen more than one gigged by >>>> this amateur's mistake. >>> >>>what? you clock a few bytes into the flash start a read, >>>then you read how ever many bytes needed for the whole configuration >>>the sync word that counts is the first one >> >>...and if that magic word happens to appear before the "correct" one? It's >>*bad* engineering practice to depend on magic words. As I said, I've seem >>more than one rookie gigged by such dumbass mistakes. > >It only takes one wire from the uP to the FPGA to hold the FPGA reset >until you're ready to stream the config data. Again, that wasn't fonz' intention. He proposes to use the FPGA's config sync word as the delimiter. It might even work, during debug.Article: 152927
On Oct 31, 11:54 pm, Al Clark <acl...@danvillesignal.com> wrote: ...snip... > Actually, I am not anti-patent. I just thing the game is completely rigged > to favor the large companies at the expense of small innovative companies > and individuals. ...snip... > Al Clark What in business in not slanted to the large company? They get the big money makers and the rest of us get the crumbs or what we can snatch off their plate. Even mid size companies have to think about what they are doing if they want to produce a BIG product regardless of the patent issues. What would be the point of ramping up to design and build millions a year of something that a much larger competitor can produce for $5 less? Is the reason why there are still just two big FPGA companies patents? No entirely, it is as much an issue of the enormous cost and time required to build such an infrastructure. Patents are the mainstay of large high tech companies, but what about high tech isn't slanted to the big companies? I just think "completely slanted" is an overstatement. There are plenty of individuals and small companies who have benefited greatly from patents. RickArticle: 152928
On 1 Nov., 17:42, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> wrote: > On Tue, 01 Nov 2011 08:48:03 -0700, John Larkin > > > > > > > > > > <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >On Mon, 31 Oct 2011 15:07:00 -0500, "k...@att.bizzzzzzzzzzzz" > ><k...@att.bizzzzzzzzzzzz> wrote: > > >>On Mon, 31 Oct 2011 10:02:37 -0700 (PDT), "langw...@fonz.dk" > >><langw...@fonz.dk> wrote: > > >>>On 31 Okt., 01:17, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> > >>>wrote: > >>>> On Sun, 30 Oct 2011 15:09:58 -0700 (PDT), "langw...@fonz.dk" > > >>>> <langw...@fonz.dk> wrote: > >>>> >On 30 Okt., 21:30, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzz= zz> > >>>> >wrote: > >>>> >> On Sun, 30 Oct 2011 10:47:26 -0700 (PDT), "langw...@fonz.dk" > > >>>> >> <langw...@fonz.dk> wrote: > >>>> >> >On 30 Okt., 18:04, John Larkin > >>>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >>>> >> >> On Sun, 30 Oct 2011 04:32:51 -0700 (PDT), Michael S > > >>>> >> >> <already5cho...@yahoo.com> wrote: > >>>> >> >> >On Oct 20, 3:26 am, John Larkin > >>>> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >>>> >> >> >> On Wed, 19 Oct 2011 21:57:00 +0100, "TTman" <pcw1....@ntlwo= rld.com> > >>>> >> >> >> wrote: > > >>>> >> >> >> >> The ARM processor will load the FPGA through its SPI por= t in real > >>>> >> >> >> >> life, but we're using JTAG to test the PCI Express inter= face parts > >>>> >> >> >> >> first, because it's quick and easy. When it works. > > >>>> >> >> >> >> The production system has the ARM boot its code off a se= rial flash > >>>> >> >> >> >> chip. Then it reads more of that flash chip and configur= es the FPGA. > >>>> >> >> >> >> We'll probably compress the config data, because it's so= mething insane > >>>> >> >> >> >> like 30 megabits, mostly zeroes. > > >>>> >> >> >> >> John > > >>>> >> >> >> >I thought Quartus will compress for you ??? Do you need al= l 30 Mbits ??? > > >>>> >> >> >> You don't really get a choice. Every config bit and every R= AM bit is > >>>> >> >> >> in the config file. The vendor's compression usually doesn'= t help a > >>>> >> >> >> lot. Since most of the config data is 0's, simple bytewise = RLL > >>>> >> >> >> compression on zeroes helps a lot, 2:1 to as much as 5:1. > > >>>> >> >> >> John > > >>>> >> >> >Methinks, you should try Altera's compression first. You woul= dn't get > >>>> >> >> >5:1, but for low-utilization design with mostly uninitialized= internal > >>>> >> >> >memories you will certainly get 2.5:1 and sometimes even 3:1. > >>>> >> >> >Besides, unlike vendor's compression, your own compression wi= ll not > >>>> >> >> >make boot process any faster. > > >>>> >> >> In a current Altera design with a GX45, low logic density, the= Altera > >>>> >> >> compression is about 2:1, which isn't bad, 30M bits down to ab= out 15. > > >>>> >> >> The Xilinx compression, at least for Spartans, is much less ef= fective. > > >>>> >> >> I the case where a uP is bit-banging the config into the FPGA, > >>>> >> >> home-made compression can speed up configuration significantly= , > >>>> >> >> because the bang-out-the-zeroes loop can be very fast. > > >>>> >> >> Not that any of that matters much. Huge serial flash chips are= cheap, > >>>> >> >> and the difference between 3 seconds of config and 8 isn't goi= ng to > >>>> >> >> affect the world much. > > >>>> >> >> John > > >>>> >> >at least for xilinx you wouldn't even have to get the data throu= gh the > >>>> >> >uP, you > >>>> >> >could just wire the DO and clock on the flash to both the fpga a= nd the > >>>> >> >uP spi interface > >>>> >> >and do enough reads from the flash to get through the whole > >>>> >> >configuration. > >>>> >> >Theres a sync word in the stream so the fpga knows when the conf= ig > >>>> >> >stream starts > > >>>> >> You assume the sync word only occurs once in the stream. > > >>>> >not really, you should start reading data at the start of the confi= g > >>>> >it is just that the extra bits and clocks that the fpga will > >>>> >see when you send a read command etc. to the flash will be ignored > >>>> >because they come before the sync word > > >>>> ...and if there is more than one sync word? =EF=BF=BDI've seen more = than one gigged by > >>>> this amateur's mistake. > > >>>what? you clock a few bytes into the flash start a read, > >>>then you read how ever many bytes needed for the whole configuration > >>>the sync word that counts is the first one > > >>...and if that magic word happens to appear before the "correct" one? = =A0It's > >>*bad* engineering practice to depend on magic words. =A0As I said, I've= seem > >>more than one rookie gigged by such dumbass mistakes. > > >It only takes one wire from the uP to the FPGA to hold the FPGA reset > >until you're ready to stream the config data. > > Again, that wasn't fonz' intention. =A0 He proposes to use the FPGA's con= fig > sync word as the delimiter. =A0It might even work, during debug. take the standard dataflash the read command is 0x03 and three bytes of address that is 32bits how could those 32 clocks in any possible way produce the 64bit sequence at the start of a config stream? -LasseArticle: 152929
On Tue, 1 Nov 2011 10:44:10 -0700 (PDT), "langwadt@fonz.dk" <langwadt@fonz.dk> wrote: >On 1 Nov., 17:42, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >wrote: >> On Tue, 01 Nov 2011 08:48:03 -0700, John Larkin >> >> >> >> >> >> >> >> >> >> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> >On Mon, 31 Oct 2011 15:07:00 -0500, "k...@att.bizzzzzzzzzzzz" >> ><k...@att.bizzzzzzzzzzzz> wrote: >> >> >>On Mon, 31 Oct 2011 10:02:37 -0700 (PDT), "langw...@fonz.dk" >> >><langw...@fonz.dk> wrote: >> >> >>>On 31 Okt., 01:17, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >> >>>wrote: >> >>>> On Sun, 30 Oct 2011 15:09:58 -0700 (PDT), "langw...@fonz.dk" >> >> >>>> <langw...@fonz.dk> wrote: >> >>>> >On 30 Okt., 21:30, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >> >>>> >wrote: >> >>>> >> On Sun, 30 Oct 2011 10:47:26 -0700 (PDT), "langw...@fonz.dk" >> >> >>>> >> <langw...@fonz.dk> wrote: >> >>>> >> >On 30 Okt., 18:04, John Larkin >> >>>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> >>>> >> >> On Sun, 30 Oct 2011 04:32:51 -0700 (PDT), Michael S >> >> >>>> >> >> <already5cho...@yahoo.com> wrote: >> >>>> >> >> >On Oct 20, 3:26 am, John Larkin >> >>>> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> >>>> >> >> >> On Wed, 19 Oct 2011 21:57:00 +0100, "TTman" <pcw1....@ntlworld.com> >> >>>> >> >> >> wrote: >> >> >>>> >> >> >> >> The ARM processor will load the FPGA through its SPI port in real >> >>>> >> >> >> >> life, but we're using JTAG to test the PCI Express interface parts >> >>>> >> >> >> >> first, because it's quick and easy. When it works. >> >> >>>> >> >> >> >> The production system has the ARM boot its code off a serial flash >> >>>> >> >> >> >> chip. Then it reads more of that flash chip and configures the FPGA. >> >>>> >> >> >> >> We'll probably compress the config data, because it's something insane >> >>>> >> >> >> >> like 30 megabits, mostly zeroes. >> >> >>>> >> >> >> >> John >> >> >>>> >> >> >> >I thought Quartus will compress for you ??? Do you need all 30 Mbits ??? >> >> >>>> >> >> >> You don't really get a choice. Every config bit and every RAM bit is >> >>>> >> >> >> in the config file. The vendor's compression usually doesn't help a >> >>>> >> >> >> lot. Since most of the config data is 0's, simple bytewise RLL >> >>>> >> >> >> compression on zeroes helps a lot, 2:1 to as much as 5:1. >> >> >>>> >> >> >> John >> >> >>>> >> >> >Methinks, you should try Altera's compression first. You wouldn't get >> >>>> >> >> >5:1, but for low-utilization design with mostly uninitialized internal >> >>>> >> >> >memories you will certainly get 2.5:1 and sometimes even 3:1. >> >>>> >> >> >Besides, unlike vendor's compression, your own compression will not >> >>>> >> >> >make boot process any faster. >> >> >>>> >> >> In a current Altera design with a GX45, low logic density, the Altera >> >>>> >> >> compression is about 2:1, which isn't bad, 30M bits down to about 15. >> >> >>>> >> >> The Xilinx compression, at least for Spartans, is much less effective. >> >> >>>> >> >> I the case where a uP is bit-banging the config into the FPGA, >> >>>> >> >> home-made compression can speed up configuration significantly, >> >>>> >> >> because the bang-out-the-zeroes loop can be very fast. >> >> >>>> >> >> Not that any of that matters much. Huge serial flash chips are cheap, >> >>>> >> >> and the difference between 3 seconds of config and 8 isn't going to >> >>>> >> >> affect the world much. >> >> >>>> >> >> John >> >> >>>> >> >at least for xilinx you wouldn't even have to get the data through the >> >>>> >> >uP, you >> >>>> >> >could just wire the DO and clock on the flash to both the fpga and the >> >>>> >> >uP spi interface >> >>>> >> >and do enough reads from the flash to get through the whole >> >>>> >> >configuration. >> >>>> >> >Theres a sync word in the stream so the fpga knows when the config >> >>>> >> >stream starts >> >> >>>> >> You assume the sync word only occurs once in the stream. >> >> >>>> >not really, you should start reading data at the start of the config >> >>>> >it is just that the extra bits and clocks that the fpga will >> >>>> >see when you send a read command etc. to the flash will be ignored >> >>>> >because they come before the sync word >> >> >>>> ...and if there is more than one sync word? �I've seen more than one gigged by >> >>>> this amateur's mistake. >> >> >>>what? you clock a few bytes into the flash start a read, >> >>>then you read how ever many bytes needed for the whole configuration >> >>>the sync word that counts is the first one >> >> >>...and if that magic word happens to appear before the "correct" one? It's >> >>*bad* engineering practice to depend on magic words. As I said, I've seem >> >>more than one rookie gigged by such dumbass mistakes. >> >> >It only takes one wire from the uP to the FPGA to hold the FPGA reset >> >until you're ready to stream the config data. >> >> Again, that wasn't fonz' intention. He proposes to use the FPGA's config >> sync word as the delimiter. It might even work, during debug. > >take the standard dataflash the read command is 0x03 and three bytes >of address >that is 32bits > >how could those 32 clocks in any possible way produce the 64bit >sequence at the >start of a config stream? I've seen an 80 byte SOF record do the same.Article: 152930
On 1 Nov., 21:47, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> wrote: > On Tue, 1 Nov 2011 10:44:10 -0700 (PDT), "langw...@fonz.dk" <langw...@fon= z.dk> > wrote: > > > > > > > > > > >On 1 Nov., 17:42, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> > >wrote: > >> On Tue, 01 Nov 2011 08:48:03 -0700, John Larkin > > >> <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> >On Mon, 31 Oct 2011 15:07:00 -0500, "k...@att.bizzzzzzzzzzzz" > >> ><k...@att.bizzzzzzzzzzzz> wrote: > > >> >>On Mon, 31 Oct 2011 10:02:37 -0700 (PDT), "langw...@fonz.dk" > >> >><langw...@fonz.dk> wrote: > > >> >>>On 31 Okt., 01:17, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzz= zz> > >> >>>wrote: > >> >>>> On Sun, 30 Oct 2011 15:09:58 -0700 (PDT), "langw...@fonz.dk" > > >> >>>> <langw...@fonz.dk> wrote: > >> >>>> >On 30 Okt., 21:30, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzz= zzzzz> > >> >>>> >wrote: > >> >>>> >> On Sun, 30 Oct 2011 10:47:26 -0700 (PDT), "langw...@fonz.dk" > > >> >>>> >> <langw...@fonz.dk> wrote: > >> >>>> >> >On 30 Okt., 18:04, John Larkin > >> >>>> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> >>>> >> >> On Sun, 30 Oct 2011 04:32:51 -0700 (PDT), Michael S > > >> >>>> >> >> <already5cho...@yahoo.com> wrote: > >> >>>> >> >> >On Oct 20, 3:26 am, John Larkin > >> >>>> >> >> ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >> >>>> >> >> >> On Wed, 19 Oct 2011 21:57:00 +0100, "TTman" <pcw1....@nt= lworld.com> > >> >>>> >> >> >> wrote: > > >> >>>> >> >> >> >> The ARM processor will load the FPGA through its SPI = port in real > >> >>>> >> >> >> >> life, but we're using JTAG to test the PCI Express in= terface parts > >> >>>> >> >> >> >> first, because it's quick and easy. When it works. > > >> >>>> >> >> >> >> The production system has the ARM boot its code off a= serial flash > >> >>>> >> >> >> >> chip. Then it reads more of that flash chip and confi= gures the FPGA. > >> >>>> >> >> >> >> We'll probably compress the config data, because it's= something insane > >> >>>> >> >> >> >> like 30 megabits, mostly zeroes. > > >> >>>> >> >> >> >> John > > >> >>>> >> >> >> >I thought Quartus will compress for you ??? Do you need= all 30 Mbits ??? > > >> >>>> >> >> >> You don't really get a choice. Every config bit and ever= y RAM bit is > >> >>>> >> >> >> in the config file. The vendor's compression usually doe= sn't help a > >> >>>> >> >> >> lot. Since most of the config data is 0's, simple bytewi= se RLL > >> >>>> >> >> >> compression on zeroes helps a lot, 2:1 to as much as 5:1= . > > >> >>>> >> >> >> John > > >> >>>> >> >> >Methinks, you should try Altera's compression first. You w= ouldn't get > >> >>>> >> >> >5:1, but for low-utilization design with mostly uninitiali= zed internal > >> >>>> >> >> >memories you will certainly get 2.5:1 and sometimes even 3= :1. > >> >>>> >> >> >Besides, unlike vendor's compression, your own compression= will not > >> >>>> >> >> >make boot process any faster. > > >> >>>> >> >> In a current Altera design with a GX45, low logic density, = the Altera > >> >>>> >> >> compression is about 2:1, which isn't bad, 30M bits down to= about 15. > > >> >>>> >> >> The Xilinx compression, at least for Spartans, is much less= effective. > > >> >>>> >> >> I the case where a uP is bit-banging the config into the FP= GA, > >> >>>> >> >> home-made compression can speed up configuration significan= tly, > >> >>>> >> >> because the bang-out-the-zeroes loop can be very fast. > > >> >>>> >> >> Not that any of that matters much. Huge serial flash chips = are cheap, > >> >>>> >> >> and the difference between 3 seconds of config and 8 isn't = going to > >> >>>> >> >> affect the world much. > > >> >>>> >> >> John > > >> >>>> >> >at least for xilinx you wouldn't even have to get the data th= rough the > >> >>>> >> >uP, you > >> >>>> >> >could just wire the DO and clock on the flash to both the fpg= a and the > >> >>>> >> >uP spi interface > >> >>>> >> >and do enough reads from the flash to get through the whole > >> >>>> >> >configuration. > >> >>>> >> >Theres a sync word in the stream so the fpga knows when the c= onfig > >> >>>> >> >stream starts > > >> >>>> >> You assume the sync word only occurs once in the stream. > > >> >>>> >not really, you should start reading data at the start of the co= nfig > >> >>>> >it is just that the extra bits and clocks that the fpga will > >> >>>> >see when you send a read command etc. to the flash will be ignor= ed > >> >>>> >because they come before the sync word > > >> >>>> ...and if there is more than one sync word? =EF=BF=BDI've seen mo= re than one gigged by > >> >>>> this amateur's mistake. > > >> >>>what? you clock a few bytes into the flash start a read, > >> >>>then you read how ever many bytes needed for the whole configuratio= n > >> >>>the sync word that counts is the first one > > >> >>...and if that magic word happens to appear before the "correct" one= ? =EF=BF=BDIt's > >> >>*bad* engineering practice to depend on magic words. =EF=BF=BDAs I s= aid, I've seem > >> >>more than one rookie gigged by such dumbass mistakes. > > >> >It only takes one wire from the uP to the FPGA to hold the FPGA reset > >> >until you're ready to stream the config data. > > >> Again, that wasn't fonz' intention. =EF=BF=BD He proposes to use the F= PGA's config > >> sync word as the delimiter. =EF=BF=BDIt might even work, during debug. > > >take the standard dataflash the read command is 0x03 and three bytes > >of address > >that is 32bits > > >how could those 32 clocks in any possible way produce the 64bit > >sequence at the > >start of a config stream? > > I've seen an 80 byte SOF record do the same. if 32 bit becomes 64 something is seriously broken and you can't even read the flash correctly so no matter what you do it won't work -LasseArticle: 152931
"langwadt@fonz.dk" <langwadt@fonz.dk> wrote: >On 1 Nov., 17:42, "k...@att.bizzzzzzzzzzzz" <k...@att.bizzzzzzzzzzzz> >wrote: >> On Tue, 01 Nov 2011 08:48:03 -0700, John Larkin >> >> >> >> >> >> >> >It only takes one wire from the uP to the FPGA to hold the FPGA reset >> >until you're ready to stream the config data. >> >> Again, that wasn't fonz' intention. =A0 He proposes to use the FPGA's con= >fig >> sync word as the delimiter. =A0It might even work, during debug. Ahh. That wasn't clear to me. > >take the standard dataflash the read command is 0x03 and three bytes >of address >that is 32bits > >how could those 32 clocks in any possible way produce the 64bit >sequence at the >start of a config stream? During development of JTAG programming routines for Xilinx FPGAs I smoked at least one FPGA. AFAIK the chances for something going are very small though because the frames also contain a CRC checksum. I also doubt missing the first frame is a problem since the start of the data consists of a few dummy frames to synchronize the FPGA to the datastream. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 152932
hi ! im from vietnam . my english is not good , i hope you can understand what i say . thanks ! i have project to graduate university . my project is draw circle , line , triagle in FPGA , display on VGA ( only use verilog , don't use C) . i have many problems , and time is running out . if you have data , code about it , please help me. .... thanks you so much !Article: 152933
lexuancong <lexuancong252@gmail.com> wrote: > im from vietnam . my english is not good , i hope you > can understand what i say . thanks ! > i have project to graduate university . > my project is draw circle , line , triagle in FPGA , display on VGA > ( only use verilog , don't use C) . i have many problems , and time is > running out . if you have data , code about it , please help me. > .... I don't have any code, but the usual VGA display logic takes a block of memory and writes that out repeatedly. If you don't need color, write the same to all three outputs. Then you have to figure out how to get the shapes drawn into memory. As it doesn't change, easiest is to load it in a a constant (ROM) that you have to somehow generate. You can write a ROM initialization table in any language, then translate that to verilog. But first you need the display logic. You need a high speed clock, a row counter, and column counter. You need to generate the syncronization pulses of the appropriate width and length. That is as close as I can give now. -- glenArticle: 152934
rickman wrote: > Noob wrote: > >> Steven Hirsch wrote: >> >>> My employer forbids engineers and software developers from reading patents >>> as a matter of policy (unless specifically requested to by legal). >> >> "[The Congress shall have Power] To promote the Progress of Science and >> useful Arts, by securing for limited Times to Authors and Inventors the >> exclusive Right to their respective Writings and Discoveries." >> >> What a travesty. >> >> Where's the progress when the wheel is reinvented every other month? >> >> One way out of this mess is for the EU to start ignoring US patents; >> that might make the US "snap out of it". > > This is exactly why patents are granted. Not only is the inventor > able to benefit financially from his invention but the invention is > made public. Once the patent expires the world is the recipient. Can I have some of what you've been smoking? In the real world, for all intents and purposes, patents are NOT public, because 1) they are written by lawyers who are deliberately trying to communicate as little information as possible, 2) many employers "forbid engineers and software developers from reading patents as a matter of policy" The system is borked.Article: 152935
lexuancong wrote: > i have project to graduate university . > my project is draw circle , line , triagle in FPGA , display on VGA > ( only use verilog , don't use C) . i have many problems , and time is The "video controller" section of Opencores has some VGA controllers source code. http://opencores.org/projects There is a line drawing implementation in VHDL. http://opencores.org/project,graphicsaccelerator (I've never tried these projects, so I don't know how useful they are.) Hope this helps, Jean-Marc -- http://www.cod5.orgArticle: 152936
I'm looking for pointers to an installation guide on how to install the Xilinx USB II Cable driver under Gentoo Linux? I just took a quick look at the installation script(1) and found checks for specific releases (grep -c -i "SUSE" /proc/version) rather than checks for functionality and features, which is a bad thing when it comes to portability across distributions. Also a quick ./configure and make resulted in lots of warnings and errors. Hence I wanted to know if anybody else have walked up this path already. I checked http://en.gentoo-wiki.com/ which seem to be down, at least I get only a blank page. 1)https://secure.xilinx.com/webreg/clickthrough.do?cid=103670&license=RefDesLicense&filename=install_drivers.tar.gz //Petter -- .sig removed by request.Article: 152937
fatalist wrote: Hello Dmitry Teres; > On Nov 1, 10:10 am, Regis <quela...@netscape.net> wrote: > >>EP1451804, the corresponding European Patent application, is >>considered withdrawn : prior art has been found... >>How much does it cost to invalidate a patent in the US ? >> > > A lawyer which you are should always check facts before posting and > never ever try to promote deliberate lies, even under pseudonym on the > internet "Tell us about your success" (c) Dmitry Teres.Article: 152938
On Wed, 02 Nov 2011 00:25:33 -0700, lexuancong wrote: > hi ! > im from vietnam . my english is not good , i hope you can understand > what i say . thanks ! > i have project to graduate university . my project is draw circle , line > , triagle in FPGA , display on VGA ( only use verilog , don't use C) . i > have many problems , and time is running out . if you have data , code > about it , please help me. .... > thanks you so much ! First get your FPGA so that it generates valid VGA sync signals (and a pixel clock, if VGA needs that). Once you've done that, then do some bog- simple thing with your pixel generator, like putting out eight white pixels followed by eight black ones -- that should give you vertical stripes on the screen, to show progress. Then figure out how to read pixels out of memory. Finally, stuff the memory with your circles, lines and squares. Do you have any friends in the class who are similarly bogged down? Helping one another isn't a bad idea. I don't know how your prof is planning on grading things, but if this were a US university, getting partial functionality is going to be better than nothing -- a C isn't as good as an A, but it's a lot better than a D or an F! -- www.wescottdesign.comArticle: 152939
On Wed, 02 Nov 2011 14:57:07 +0100, Petter Gustad wrote:
> I'm looking for pointers to an installation guide on how to install the
> Xilinx USB II Cable driver under Gentoo Linux?
>
> I just took a quick look at the installation script(1) and found checks
> for specific releases (grep -c -i "SUSE" /proc/version) rather than
> checks for functionality and features, which is a bad thing when it
> comes to portability across distributions. Also a quick ./configure and
> make resulted in lots of warnings and errors. Hence I wanted to know if
> anybody else have walked up this path already.
>
> I checked http://en.gentoo-wiki.com/ which seem to be down, at least I
> get only a blank page.
>
>
> 1)https://secure.xilinx.com/webreg/clickthrough.do?
cid=103670&license=RefDesLicense&filename=install_drivers.tar.gz
>
> //Petter
You don't want to use the WinDrvr that Xilinx provides, it doesn't work
for any modern kernel. Set the following variable in your shell before using chipscope or impact
setenv XIL_IMPACT_USE_LIBUSB 1
Then do the following setup (this for Redhat)
#!/bin/csh -f
yum -y install libusb libusb1 fxload
cp $XILINX/bin/lin64/*.hex /usr/share
cd /usr/lib64
ln -s libusb-1.0.so.0.0.0 libusb.so
cp setup_pcusb $XILINX/bin/lin64
setup_pcusb
xusbdfwu.rules /etc/udev/rules.d
-------------------------------
xusbdfwu.rules
# version 0003
ATTR{idVendor}=="03fd", ATTR{idProduct}=="0008", MODE="666"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0007", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusbdfwu.hex -D $tempnode"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0009", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusb_xup.hex -D $tempnode"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="000d", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusb_emb.hex -D $tempnode"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="000f", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusb_xlp.hex -D $tempnode"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0013", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusb_xp2.hex -D $tempnode"
SUBSYSTEM=="usb", ACTION=="add", ATTR{idVendor}=="03fd", ATTR{idProduct}=="0015", RUN+="/sbin/fxload -v -t fx2 -I /usr/share/xusb_xse.hex -D $tempnode"
-------------------------------
setup_pcusb
#!/bin/sh
# Copyright (c) 2005 Xilinx, Inc. All rights reserved.
#
# Xilinx, Inc.
# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
# COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
# ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
# STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
# IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
# FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
# XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
# THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
# ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
# FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
# AND FITNESS FOR A PARTICULAR PURPOSE.
#
TP_PCUSB_HEX_FILE="xusbdfwu.hex"
TP_KERNEL_VERSION=`uname -r`
# check if udev is running on version 2.6.13* and later
TP_MAJOR_VERSION=`echo $TP_KERNEL_VERSION | cut -f 1 -d "."`
TP_MINOR_VERSION=`echo $TP_KERNEL_VERSION | cut -f 2 -d "."`
TP_MINOR_SUBVERSION=`echo $TP_KERNEL_VERSION | cut -f 3 -d "." | cut -f 1 -d "-"`
#TP_USE_UDEV="0"
#TP_UDEV_ENABLED=`ps -e | grep -c udevd`
TP_UDEV_ENABLED="1"
if [ $TP_MAJOR_VERSION = "2" ]
then
if [ $TP_MINOR_VERSION = "6" ]
then
test $TP_MINOR_SUBVERSION -ge "13"
if [ $? = "0" ]
then
if [ $TP_UDEV_ENABLED = "1" ]
then
TP_USE_UDEV="1"
fi;
fi;
fi;
fi;
# $1 - destination directory
# $2 - driver name
update_hex_file ()
{
TP_INSTALL_DRIVER="1" # default to install
#TP_DRV_SRC_PATH="/etc/hotplug/usb/xusbdfwu.fw"
TP_DRIVER_FILE=$1/$2
get_hex_file_version $TP_DRIVER_FILE
if [ $? = "1" ]
then
TP_DEST_VERSION=$TP_DRIVER_VER
TP_DRIVER_FILE=$2
get_hex_file_version $TP_DRIVER_FILE
TP_SRC_VERSION=$TP_DRIVER_VER
if [ $TP_DEST_VERSION -lt $TP_SRC_VERSION ]
then
echo "--File $TP_DRIVER_FILE is newer than the destination file."
else
echo "--File $TP_DRIVER_FILE is already updated."
TP_INSTALL_DRIVER="0"
fi;
else
echo "--Error getting file version for $TP_DRIVER_FILE."
fi;
if [ $TP_INSTALL_DRIVER = "1" ]
then
echo "--Updating $2 file."
# Copy hex file to the fw directory.
mkdir -p $1
/bin/cp -p $2 $1
fi;
}
update_usermap ()
{
TP_ID_PRESENT=`cat /etc/hotplug/usb.usermap | grep xusbdfwu | grep -i -c $1`
if [ $TP_ID_PRESENT = "0" ]
then
echo "--Adding Product ID $1 to the usermap."
echo "xusbdfwu 0x0003 0x03fd 0x$1 0x0000 0x0000 0x00 0x00 0x00 0x00 0x00 0x00 0x00000000" >> /etc/hotplug/usb.usermap
else
echo "--Product ID $1 is already in the usermap."
fi;
}
file_exists ()
{
if [ -f $1 ]
then
echo "--File $1 exists."
return 1
else
echo "--File $1 does not exist."
return 0
fi;
}
get_hex_file_version ()
{
TP_DRIVER_VER="0000"
file_exists $1
if [ $? = "1" ]
then
TP_VERSION_STRING=`grep ":0219B900" $1`
#TP_HEX_VERSION=`expr substr $TP_VERSION_STRING 10 4`
TP_HEX_VERSION=${TP_VERSION_STRING:9:4}
TP_DRIVER_VER=`printf "%d" 0x$TP_HEX_VERSION`
echo "--File $1 version = "$TP_DRIVER_VER
return 1
else
return 0
fi;
}
# arg1 = file, arg2 = version string
get_rules_file_version ()
{
TP_DRIVER_VER="0000"
file_exists $1
if [ $? = "1" ]
then
TP_VER_STR_LINE=`cat $1 | grep "$2"`
TP_DRIVER_VER=${TP_VER_STR_LINE:10:4}
echo "--File $1 version = "$TP_DRIVER_VER
return 1
else
return 0
fi;
}
if [ $TP_USE_UDEV = "0" ]
then
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusbdfwu.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_xlp.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_emb.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_xpr.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_xup.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_xp2.hex
update_hex_file /etc/hotplug/usb/xusbdfwu.fw xusb_xse.hex
# Copy loader script file to the usb directory.
/bin/cp -p xusbdfwu /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusbdfwu
/bin/cp -p xusb_xlp /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_xlp
/bin/cp -p xusb_emb /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_emb
/bin/cp -p xusb_xpr /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_xpr
/bin/cp -p xusb_xup /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_xup
/bin/cp -p xusb_xp2 /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_xp2
/bin/cp -p xusb_xse /etc/hotplug/usb
chmod 775 /etc/hotplug/usb/xusb_xse
# Add entries to usermap
update_usermap "0007"
update_usermap "0009"
update_usermap "000d"
update_usermap "000f"
update_usermap "0013"
update_usermap "0015"
update_usermap "0008"
else
update_hex_file /usr/share xusbdfwu.hex
update_hex_file /usr/share xusb_xlp.hex
update_hex_file /usr/share xusb_emb.hex
update_hex_file /usr/share xusb_xpr.hex
update_hex_file /usr/share xusb_xup.hex
update_hex_file /usr/share xusb_xp2.hex
update_hex_file /usr/share xusb_xse.hex
TP_INSTALL_DRIVER="1"
TP_DRIVER_FILE="/etc/udev/rules.d/xusbdfwu.rules"
get_rules_file_version $TP_DRIVER_FILE "# version"
if [ $? = "1" ]
then
TP_DEST_VERSION=$TP_DRIVER_VER
TP_DRIVER_FILE="xusbdfwu.rules"
get_rules_file_version $TP_DRIVER_FILE "# version"
TP_SRC_VERSION=$TP_DRIVER_VER
if [ $TP_DEST_VERSION -lt $TP_SRC_VERSION ]
then
echo "--File $TP_DRIVER_FILE is newer than the destination file."
else
echo "--File $TP_DRIVER_FILE is already updated."
TP_INSTALL_DRIVER="0"
fi;
else
echo "--Error getting file version for $TP_DRIVER_FILE."
fi;
if [ $TP_INSTALL_DRIVER = "1" ]
then
echo "--Updating rules file."
/bin/cp -p xusbdfwu.rules /etc/udev/rules.d
fi;
fi;
# End of file.
Article: 152940IEEE sponsored Town Hall meeting/lunch/workshop Nov. 5 - Patent Reform and YOU Congress has recently enacted sweeping patent reform that is adverse to small inventors and entrepreneurs. The IEEE National Capital Area Consultants Network and Baltimore Consultants Network want you to know what has happened and how patent reform will affect the individual or small-business entrepreneur. We have put together a Town Hall meeting with a panel session and workshop. The event is open to the public, and IEEE student members are especially welcomed to participate. Lunch and a networking reception are included. IEEE Student members may bring a guest at no additional cost. Door prizes will be awarded! The NCACN welcomes IP experts Dr. Lee Hollaar and Dr. Amelia Morani who will present the current landscape of U.S. patent law and lead the workshop. Your admission ticket includes a complimentary lunch and admission to the networking reception. IEEE members can preregister to attend at a discounted price of $10, and IEEE student members will receive one guest admission as part of their $10 ticket price. IEEE discounted prices are available only by preregistration until 6pm on November 4. General admission is offered for $20 per person by preregistration and at the door. All registered attendees will be eligible for door prizes. WHERE: Loyola University Columbia, MD Graduate Campus 8890 MaGaw Road Room 260 Columbia, MD 21045 DIRECTIONS: http://www.loyola.edu/facilitiesmanagement/columbia/directions.html WHEN: Saturday November 5 10am - Panel session, lunch, and discussion 2pm - Networking reception COST: $20 - general admission $10 - IEEE member or guest (expires Nov. 4 6pm) $10 - IEEE student member with 1 complimentary guest admission (expires Nov. 4 6pm) RSVP: NCACN registration portal: http://www.ieee-consultants.org OR IEEE vtools registration link: http://meetings.vtools.ieee.org/meeting_view/list_meeting/8771 Thank you, and we hope to see you there! Monica Mallini, PE YOUR HOSTS: IEEE National Capital Area Consultants Network IEEE Baltimore Consultants Network IEEE Society on Social Implications of Technology (Wash/NoVA/Balt Chapter) IEEE Computer Society (Wash/Nova and Balt Chapters) IEEE Region 2 Professional Activities CommitteeArticle: 152941
General Schvantzkoph <schvantzkoph@yahoo.com> writes: > You don't want to use the WinDrvr that Xilinx provides, it doesn't work > for any modern kernel. Set the following variable in your shell before using chipscope or impact > > setenv XIL_IMPACT_USE_LIBUSB 1 > > Then do the following setup (this for Redhat) Thank you for the script. I don't seem to have a libusb1 on Gentoo, but I'll try to walk through the script and see if I can get it to work. I also noticed that there's a similar approach described at: http://www.george-smart.co.uk/wiki/Xilinx_JTAG_Linux But the driver fails to compile since it can't find a 32-bit ibftdi on my 64-bit system... //Petter -- .sig removed by request.Article: 152942
On 27 Okt., 04:31, self <padu...@gmail.com> wrote: > Do you know if it is possible to get a complete pinout report from the > Actel compilation flow? > > I want something complete like the CSV file that comes out of the > Xilinx ISE compilation process. In ACtel Design use pin report by number (Tools-> Reports-> Resources - > Pin, select Number). It gives you a full pin report including all pins even vcc, gnd and unused. bye ThomasArticle: 152943
> A lawyer which you are should always check facts before posting and > never ever try to promote deliberate lies, even under pseudonym on the > internet > > EPO can and does recycle same "prior art" references cited by > applicant himself to USPTO and already discussed in depth in office > actions and interviews with US examiners =A0... =A0just to prolong the > process and extort more money from poor applicant... until he is fed > up paying through his nose and walks away... > > Just tell me why EPO keeps collecting huge annuities on pending > applications (and keeps them pending for many years) and why you have > to go through EU-registered attorney like yourself just to communicate > with EPO ? > > =A0BTW, can you post your registration number ? About verifying facts... I'm not a lawyer but an EPO patent examiner. An applicant can always request an accelerated search and examination at the EPO, for free. I was just questioning the legal certainty of a patent in the US, which application has been abandoned at the EPO without even a reply to the first communication, citing novelty destroying documents. I did not check if these documents were also cited at the USPTO, before or after the EPO search report had been issued.Article: 152944
On 11/03/11 09:19, Petter Gustad wrote: > General Schvantzkoph <schvantzkoph@yahoo.com> writes: > >> You don't want to use the WinDrvr that Xilinx provides, it doesn't work >> for any modern kernel. Set the following variable in your shell before using chipscope or impact >> >> setenv XIL_IMPACT_USE_LIBUSB 1 >> >> Then do the following setup (this for Redhat) If you use ISE newer than 11 you don't even have to set the XIL_IMPACT_USE_LIBUSB variable. Just make sure you have a symlink /lib/libusb.so to your actual libusb-[version].so file. Then make sure you have the xusbdwfu.rules from $XILINX/ISE/bin/lin64/ at /etc/udev/rules.d/, fxload installed and the *.hex files from $XILINX/ISE/bin/lin64/ copied to /usr/share/. This works fine for me with Gentoo and dev-libs/libusb from portage for any recent ISE version. HTHArticle: 152945
rndhro <rnd@hro.org> writes: > On 11/03/11 09:19, Petter Gustad wrote: >> General Schvantzkoph <schvantzkoph@yahoo.com> writes: >> >>> You don't want to use the WinDrvr that Xilinx provides, it doesn't work >>> for any modern kernel. Set the following variable in your shell before using chipscope or impact >>> >>> setenv XIL_IMPACT_USE_LIBUSB 1 >>> >>> Then do the following setup (this for Redhat) > > If you use ISE newer than 11 you don't even have to set the Thanks. I'm using v13.3i. I got it working now. > XIL_IMPACT_USE_LIBUSB variable. Just make sure you have a symlink > /lib/libusb.so to your actual libusb-[version].so file. BTW, I don't like to replace system wide so files. I prefer to do something like: mkdir ~/libusb ln -s /usr/lib/libusb-1.0.so.0.0.0 ~/libusb/libusb.so LD_LIBRARY_PATH=~/libusb:$LD_LIBRARY_PATH impact //Petter -- .sig removed by request.Article: 152946
On Nov 3, 6:57=A0am, Regis <quela...@netscape.net> wrote: > > A lawyer which you are should always check facts before posting and > > never ever try to promote deliberate lies, even under pseudonym on the > > internet > > > EPO can and does recycle same "prior art" references cited by > > applicant himself to USPTO and already discussed in depth in office > > actions and interviews with US examiners =A0... =A0just to prolong the > > process and extort more money from poor applicant... until he is fed > > up paying through his nose and walks away... > > > Just tell me why EPO keeps collecting huge annuities on pending > > applications (and keeps them pending for many years) and why you have > > to go through EU-registered attorney like yourself just to communicate > > with EPO ? > > > =A0BTW, can you post your registration number ? > > About verifying facts... > I'm not a lawyer but an EPO patent examiner. > An applicant can always request an accelerated search and examination > at the EPO, for free. > I was just questioning the legal certainty of a patent in the US, > which application has been abandoned at the EPO without even a reply > to the first communication, citing novelty destroying documents. I did > not check if these documents were also cited at the USPTO, before or > after the EPO search report had been issued.- Hide quoted text - > > - Show quoted text - Every US patent attorney is obligated to submit all prior art references coming his way to USPTO during patent prosecution, including references from EPO search reports Once submitted prior art references are considered by examiner and made of record (and discussed in office actions and interviews), and US patent is officially granted then your chance of getting re-exam request approved based on the very same references is ZEROArticle: 152947
On Oct 31, 12:40=A0am, Dude Whocares <ipisg...@gmail.com> wrote: > US Patent 7,124,075 =93Methods and apparatus for pitch determination=94 > will be auctioned as Lot 147 at the upcoming ICAP Patent Brokerage > Live IP Action on November 17, 2011 at The Ritz Carlton, San > Francisco. > The patent addresses a core problem of signal processing in general, > and speech signal processing in particular: period (fundamental > frequency) determination of a (quasi)-periodic signal, or pitch > detection problem in speech/audio signal processing. > Patented nonlinear signal processing techniques originate from chaos > theory and address known limitations of traditional linear signal > processing methods like FFT or correlation. > Patented methods are amenable to efficient implementation in both > software and hardware (FPGAs, ASICs). > Forward citations include Microsoft, Mitsubishi Space Software, > Broadcom, Sharp and Teradata. > Visit ICAP=92s website for more information:http://icappatentbrokerage.co= m/forsale Ideas, it turns out, are a dime a dozen. Committing to an idea and putting massive energy into the idea , with the realization that the work may not even pay off... that is where the money is (or not)Article: 152948
On Nov 3, 1:18=A0pm, brent <buleg...@columbus.rr.com> wrote: > On Oct 31, 12:40=A0am, Dude Whocares <ipisg...@gmail.com> wrote: > > > > > > > US Patent 7,124,075 =93Methods and apparatus for pitch determination=94 > > will be auctioned as Lot 147 at the upcoming ICAP Patent Brokerage > > Live IP Action on November 17, 2011 at The Ritz Carlton, San > > Francisco. > > The patent addresses a core problem of signal processing in general, > > and speech signal processing in particular: period (fundamental > > frequency) determination of a (quasi)-periodic signal, or pitch > > detection problem in speech/audio signal processing. > > Patented nonlinear signal processing techniques originate from chaos > > theory and address known limitations of traditional linear signal > > processing methods like FFT or correlation. > > Patented methods are amenable to efficient implementation in both > > software and hardware (FPGAs, ASICs). > > Forward citations include Microsoft, Mitsubishi Space Software, > > Broadcom, Sharp and Teradata. > > Visit ICAP=92s website for more information:http://icappatentbrokerage.= com/forsale > > Ideas, it turns out, are a dime a dozen. =A0Committing to an idea and > putting massive energy into the idea , with the realization that the > work may not even pay off... that is where the money is (or not)- Hide qu= oted text - > > - Show quoted text - "Ideas" are not patentable novel and non-obvious workable solutions to long-standing industry problems are. As far as quitting your job and mortgaging your house to fully "commit" to an "idea": you are more than welcome to do it yourself (if your wife doesn't mind...) thanks but no thanksArticle: 152949
lexuancong wrote: > my project is draw circle , line , triagle in FPGA , display on VGA > ( only use verilog , don't use C) . i have many problems , and time is > running out . if you have data , code about it , please help me. I have implemented a VGA signal generator, line drawing and bit-blitting in VHDL: http://www.frank-buss.de/yagraphcon/index.html You could take a look at it, try to understand how it works (with ModelSim you can even single-step the VHDL code and watching how the registers changes) and then try to implement it yourself in Verilog. For circles there is a modified Bresenham algorithm. Triangles are trivial, if you don't need to fill it. If you need filled polygons, it gets a bit more interesting. -- Frank Buss, http://www.frank-buss.de piano and more: http://www.youtube.com/user/frankbuss
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