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I used to use a really nice, simple, browser-based timing diagram editor, and now I've forgotten the name and URL of this tool. Does anybody know which one I'm talking about? There was a text window to enter signal names and values as strings of text, like 10xz01C00, and then the waveforms would show up on the web page. You could save a diagram and get the URL so you could use the URL to retrieve it. I think it was something written by some guy in his spare time. Another nice thing I'd like is a tool to generate ASCII-art timing diagrams that I could insert into my code. They're a bit of a pain to draw directly.Article: 152651
On 9/22/2011 4:53 PM, Kevin Neilson wrote: > I used to use a really nice, simple, browser-based timing diagram > editor, and now I've forgotten the name and URL of this tool. Does > anybody know which one I'm talking about? There was a text window to > enter signal names and values as strings of text, like 10xz01C00, and > then the waveforms would show up on the web page. You could save a > diagram and get the URL so you could use the URL to retrieve it. I > think it was something written by some guy in his spare time. > Probably not the one you mean but google has something like what you want in their code section: http://code.google.com/p/wavedrom/ CharlieArticle: 152652
On Sep 23, 3:21=A0am, Charlie <charlieD...@verEYEzon.net> wrote: > On 9/22/2011 4:53 PM, Kevin Neilson wrote: > > > I used to use a really nice, simple, browser-based timing diagram > > editor, and now I've forgotten the name and URL of this tool. =A0Does > > anybody know which one I'm talking about? =A0There was a text window to > > enter signal names and values as strings of text, like 10xz01C00, and > > then the waveforms would show up on the web page. =A0You could save a > > diagram and get the URL so you could use the URL to retrieve it. =A0I > > think it was something written by some guy in his spare time. > > Probably not the one you mean but google has something like what you > want in their code section: > > http://code.google.com/p/wavedrom/ > > Charlie I don't know about the tool you are speaking about but the following FONTS http://www.pcserviceselectronics.co.uk/fonts/ are useful when making documentation. Very simple, just use those fonts in the wordprocessor. FabioArticle: 152653
On 22 Sep., 21:50, jleslie48 <j...@jonathanleslie.com> wrote: > the xilinx says it has 500,000 gates, > > the altera says it has > 22,320 Logic elements (LEs) > 594 Embedded memory (Kbits) > 66 Embedded 18 x 18 multipliers > 4 General-purpose PLLs > > so are these two fpga's comparable in size/ computing power/ ability > to support the same VHDL or what? Hi, The comparision of two types of FPGAs is not simple. Your statement about the Xilinx device is oversimplified. It is useful for comparisions of Xilinx devices of the same family, but nothing beyond that. Also this method has already been kind of "dropped" for more recent device families. For all Xilinx devices there are also informations available that are more comparable to the informations you have listed for the altera device. e.g for the S3E-500: 1,164 CLBs = 4,656 Slices of 2 LUts 2FFs and some Carry logic 360K BRAM 20 Multipliers 4 DCMs And for the othere informations consult the datasheets of both devices. VHDL is always the same, but the tools may have special support, that can cause incompatibilities. So the correct usage of some HDL is more or less depending on the skills of the engineer that is working with it. Have a nice synthesis EilertArticle: 152654
As already said the comparision is not simple but a starting point is a comparision of LUTs and flipflops. Even then you need to take account of variation in LUTs e.g. Spartan-6 has a 6 ip LUT which might be comparible to 2 x 4 ip LUT in a Spartan-3. If you design needs a lot of ram e.g. for video or multipliers for DSP these are also things to look at. Ultimately if your design, or part of it, is available you can always do a trial build. Both Xilinx and Altera have free versions of their tools which you could a trial even if the size of device you are interested in isn't supported in those versions just try in for a smaller one and get a logic size out of that. John Adair Enterpoint Ltd. - Home of the XC6SLX150 X2 Coprocessor Module. On Sep 22, 8:50=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > the xilinx says it has 500,000 gates, > > the altera says it has > 22,320 Logic elements (LEs) > 594 Embedded memory (Kbits) > 66 Embedded 18 x 18 multipliers > 4 General-purpose PLLs > > so are these two fpga's comparable in size/ computing power/ ability > to support the same VHDL or what?Article: 152655
On Sep 22, 12:50=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:
> the xilinx says it has 500,000 gates,
>
> the altera says it has
> 22,320 Logic elements (LEs)
> 594 Embedded memory (Kbits)
> 66 Embedded 18 x 18 multipliers
> 4 General-purpose PLLs
>
> so are these two fpga's comparable in size/ computing power/ ability
> to support the same VHDL or what?
The XC3S500E (this is an older family) is about 50% of the resources
as a EPC4CE22
XC3S500E EP4CE22
LE - 10,476 22,320
Memory - 360K 594K
Mult-18x18 - 20 66
PLL/DCM - 4 4
Max IO - 232 150
The XC3S1200E (same family) is closer in resources and the next size
up is about 50% larger:
XC3S1200E EP4CE22
LE - 19,512 22,320
Memory - 504K 594K
Mult-18x18 - 28 66
PLL/DCM - 4 4
Max IO - 304 150
The same modern family from Xilinx as an EPC4CE22 is the Spartan-6
line:
XC6S25 EP4CE22
LE - 24,051 22,320
Memory - 936K 594K
Mult-18x18 - 38 66
PLL/DCM - 6 4
Max IO - 266 150
Ed McGettigan
--
Xilinx Inc.
Article: 152656On Sep 23, 11:57=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > On Sep 22, 12:50=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > the xilinx says it has 500,000 gates, > > > the altera says it has > > 22,320 Logic elements (LEs) > > 594 Embedded memory (Kbits) > > 66 Embedded 18 x 18 multipliers > > 4 General-purpose PLLs > > > so are these two fpga's comparable in size/ computing power/ ability > > to support the same VHDL or what? > > The XC3S500E (this is an older family) is about 50% of the resources > as a EPC4CE22 > > =A0 =A0 =A0 =A0 =A0 =A0XC3S500E EP4CE22 > LE =A0 =A0 =A0 =A0 - 10,476 =A022,320 > Memory =A0 =A0 - =A0 360K =A0 =A0594K > Mult-18x18 - =A0 =A0 20 =A0 =A0 =A066 > PLL/DCM =A0 =A0- =A0 =A0 =A04 =A0 =A0 =A0 4 > Max IO =A0 =A0 - =A0 =A0232 =A0 =A0 150 > > The XC3S1200E (same family) is closer in resources and the next size > up is about 50% larger: > > =A0 =A0 =A0 =A0 =A0 XC3S1200E =A0EP4CE22 > LE =A0 =A0 =A0 =A0 - 19,512 =A022,320 > Memory =A0 =A0 - =A0 504K =A0 =A0594K > Mult-18x18 - =A0 =A0 28 =A0 =A0 =A066 > PLL/DCM =A0 =A0- =A0 =A0 =A04 =A0 =A0 =A0 4 > Max IO =A0 =A0 - =A0 =A0304 =A0 =A0 150 > > The same modern family from Xilinx as an EPC4CE22 is the Spartan-6 > line: > =A0 =A0 =A0 =A0 =A0 =A0 =A0XC6S25 EP4CE22 > LE =A0 =A0 =A0 =A0 - 24,051 =A022,320 > Memory =A0 =A0 - =A0 936K =A0 =A0594K > Mult-18x18 - =A0 =A0 38 =A0 =A0 =A066 > PLL/DCM =A0 =A0- =A0 =A0 =A06 =A0 =A0 =A0 4 > Max IO =A0 =A0 - =A0 =A0266 =A0 =A0 150 > > Ed McGettigan > -- > Xilinx Inc. Thanks for all the thoughts on this. I realize these things are still in their infancy, but the "computing power" in general terms should be comparable between different brands of FPGA's. I'm not looking for accuracy to 4 decimal places, but just a ballpark expectation. Ed's values seem to give good apples to apples values for comparision. My first project with fpga went well enough until I tried to fit it onto a cpld chip only to find that the CPLD chip was 1/1000th the size of the spartan 3E I was using as a development target. When something is 3 orders of magnitude different, I should be able to tell reasonably easy. So my walkaway from this thread is: in the future, a better "marker" for size is LE's instead of gates.Article: 152657
On 9/17/2011 10:44 AM, valtih1978 wrote: > Synthesis optimization people seem to like registers at I/O. > Particularly, in Xilinx manual: > > "The synthesis tools will not optimize across the Partition interface. > If an asynchronous timing critical path crosses Partition boundaries, > logic optimizations will not occur across the Partition boundary. To > mitigate this issue, add a register to the asynchronous signal at the > Partition boundary." > > I like the registers all over design. Though, they speak like it is game > inject a register in arbitrary place. One of the games is register retiming to improve Fmax. If I describe a 128 input OR gate without registers, my fmax will be very bad, and the tools can do nothing about it. If I pipeline the design with registers, syntheses can move the luts around to optimize Fmax. -- Mike TreselerArticle: 152658
Mike Treseler <mtreseler@gmail.com> wrote: (snip) >> "The synthesis tools will not optimize across the Partition interface. >> If an asynchronous timing critical path crosses Partition boundaries, >> logic optimizations will not occur across the Partition boundary. To >> mitigate this issue, add a register to the asynchronous signal at the >> Partition boundary." (snip) > One of the games is register retiming to improve Fmax. > If I describe a 128 input OR gate without registers, > my fmax will be very bad, and the tools can do nothing about it. > If I pipeline the design with registers, syntheses can move > the luts around to optimize Fmax. It would be nice if the tools could help placing of such registers. For the 128 input OR, I might know that it can have one pipeline register inside, but don't know where it should be. (My pipelines are usually more complicated than an OR gate, but the same idea applies.) One possibility would be to have a set of registers that are optional, such that the tools should leave them in if it improves Fmax, but omit them if it doesn't. It will take a while to converge, but still better than trial and error. -- glenArticle: 152659
I am designing a Spartan-6 pcb with DDR3 by way of Memory Control Block and with various video interfaces. Before I start with my own design, I thought I would look at other available designs, including the Xilinx SP605 design. I downloaded the design files and opened file 4199_SP605_brd_091909.brd with Allegro's Summer '09 viewer, that is, v15.7. There are top, bottom, and four inner signal layers that are nicely viewable by manipulating the display enables and colors. You can click on the info button to get net information, a clear advantage over Gerber files. I'll post some questions about the routes on these signal layers later but now I have a question about the inner power plane layers. These inner plane layers display as completely filled areas with no regard to vias. All the vias appear to connect to the planes whereas it's clear that a high proportion of vias should not. Now I'm an old EAGLE user and I remember that I had to click on the ratnest tool in order to get the polygon fills to "render". But I don't see any comparable button on the Allegro Free Viewer. Is it possible to get these via connections to show properly? Another issue is the plot. I can plot to my printer, that's good. But when I plot to a file, the file has a .PLT extension. I've already tried TotalCADConverter to get this into another form, a .BMP file, which did not work. All I got was one long line. Has any one converted these .PLT files successfully with free software? Thanks in advance, Brad Smallridge Ai VisionArticle: 152660
> Mike Treseler<mtreseler@gmail.com> wrote:
>> One of the games is register retiming to improve Fmax.
>> If I describe a 128 input OR gate without registers,
>> my fmax will be very bad, and the tools can do nothing about it.
>> If I pipeline the design with registers, syntheses can move
>> the luts around to optimize Fmax.
On 9/24/2011 10:42 AM, glen herrmannsfeldt wrote:
> It would be nice if the tools could help placing of such registers.
>
> For the 128 input OR, I might know that it can have one pipeline
> register inside, but don't know where it should be.
It doesn't matter, at least with quartus.
I can put a shift(n) register on all the outputs,
turn on reg dupe and reg retime, and let synthesis have a go at it.
> (My pipelines
> are usually more complicated than an OR gate, but the same idea
> applies.)
Mine too. The gate example was just for clarity.
> One possibility would be to have a set of registers that are optional,
> such that the tools should leave them in if it improves Fmax, but
> omit them if it doesn't.
Would be nice, but that's not how it is with quartus today.
Trial and error works OK with a reasonable starting guess for n.
-- Mike Treseler
Article: 152661This may be of interest to comp.arch.fpga: https://bitcointalk.org/index.php?topic=45532.msg543312Article: 152662
Mike Treseler <mtreseler@gmail.com> wrote: (snip, I wrote) >> It would be nice if the tools could help placing of such registers. >> For the 128 input OR, I might know that it can have one pipeline >> register inside, but don't know where it should be. > It doesn't matter, at least with quartus. > I can put a shift(n) register on all the outputs, > turn on reg dupe and reg retime, and let synthesis have a go at it. >> (My pipelines are usually more complicated than an OR gate, >> but the same idea applies.) > Mine too. The gate example was just for clarity. >> One possibility would be to have a set of registers that are optional, >> such that the tools should leave them in if it improves Fmax, but >> omit them if it doesn't. > Would be nice, but that's not how it is with quartus today. > Trial and error works OK with a reasonable starting guess for n. OK, one specific problem. The designs I am interested in are linear arrays of pipelined elements. I can optimize the individual element, but I also need to optimize their placement in the arrays. It might be that the tools can well optimize a linear (on chip) array of unit cells, but sometime it will get to the chip boundary and need to turn around. The paths needed at that point are likely longer, and so I might want to add additional registers. I don't know very well where those points are. In addition, there is the path from the I/O buffers to the first, and from the last to I/O buffers, which again have complications in timing and placement. Even more, last time I tried this with the Xilinx tools, adding extra registers where I thought they might help, the tools implemented the double register as SRL16 cells, (shift registers), instead of spacing them out as I had hoped. -- glenArticle: 152663
On 9/24/2011 3:28 PM, glen herrmannsfeldt wrote:
> OK, one specific problem. The designs I am interested in are
> linear arrays of pipelined elements. I can optimize the individual
> element, but I also need to optimize their placement in the arrays.
> It might be that the tools can well optimize a linear (on chip)
> array of unit cells, but sometime it will get to the chip boundary
> and need to turn around.
If the design does not fit in one FPGA, you are on your own.
> Even more, last time I tried this with the Xilinx tools, adding
> extra registers where I thought they might help, the tools implemented
> the double register as SRL16 cells, (shift registers), instead of
> spacing them out as I had hoped.
That means register retiming was not switched on.
Try a simpler example to see if ISE can do it at all.
To banish all SRL16s (or the altera equivalents)
add a reset input to the process.
Good luck.
-- Mike Treseler
Article: 152664I am looking for an affordable FPGA development board with TVP70025I Board. I am assuming that the board can take in VGA input and then pass the digitized data to FPGA. Is there such a board? Thanks.Article: 152665
Hi, I want to learn tcl in Modelsim for FPGA simulation. I find that there is a directory under modelsim named tcl_tutorial\solutions. But the traffic.do file cannot run with the following error message under dot line below. I have installed tcl/tk 8.6 on Windows XP. BTW, when I enter : help Tk It does give many Tk commands including winfo. What is wrong with my system? Thanks. Modelsim version is: ModelSim XE III/Starter 6.4b Is it disabled? ............ do traffic.do # Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008 # -- Loading package standard # -- Loading package std_logic_1164 # -- Compiling entity traffic # -- Compiling architecture simple of traffic # -- Compiling entity queue # -- Compiling architecture only of queue # -- Compiling entity tb_traffic # -- Compiling architecture only of tb_traffic # ** Error: invalid command name "winfo" # Error in macro ./traffic.do line 13 # invalid command name "winfo" # while executing # "winfo exists .traffic" # (procedure "draw_intersection" line 4) # invoked from within # "draw_intersection"Article: 152666
On 9/25/2011 5:33 PM, fl wrote: > do traffic.do > # Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 > 2008 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Compiling entity traffic > # -- Compiling architecture simple of traffic > # -- Compiling entity queue > # -- Compiling architecture only of queue > # -- Compiling entity tb_traffic > # -- Compiling architecture only of tb_traffic > # ** Error: invalid command name "winfo" > # Error in macro ./traffic.do line 13 > # invalid command name "winfo" > # while executing > # "winfo exists .traffic" Maybe a comment on line 12 wrapped to line 13Article: 152667
On 23 Sep., 18:18, jleslie48 <j...@jonathanleslie.com> wrote: > On Sep 23, 11:57=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > > > > > > On Sep 22, 12:50=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > the xilinx says it has 500,000 gates, > > > > the altera says it has > > > 22,320 Logic elements (LEs) > > > 594 Embedded memory (Kbits) > > > 66 Embedded 18 x 18 multipliers > > > 4 General-purpose PLLs > > > > so are these two fpga's comparable in size/ computing power/ ability > > > to support the same VHDL or what? > > > The XC3S500E (this is an older family) is about 50% of the resources > > as a EPC4CE22 > > > =A0 =A0 =A0 =A0 =A0 =A0XC3S500E EP4CE22 > > LE =A0 =A0 =A0 =A0 - 10,476 =A022,320 > > Memory =A0 =A0 - =A0 360K =A0 =A0594K > > Mult-18x18 - =A0 =A0 20 =A0 =A0 =A066 > > PLL/DCM =A0 =A0- =A0 =A0 =A04 =A0 =A0 =A0 4 > > Max IO =A0 =A0 - =A0 =A0232 =A0 =A0 150 > > > The XC3S1200E (same family) is closer in resources and the next size > > up is about 50% larger: > > > =A0 =A0 =A0 =A0 =A0 XC3S1200E =A0EP4CE22 > > LE =A0 =A0 =A0 =A0 - 19,512 =A022,320 > > Memory =A0 =A0 - =A0 504K =A0 =A0594K > > Mult-18x18 - =A0 =A0 28 =A0 =A0 =A066 > > PLL/DCM =A0 =A0- =A0 =A0 =A04 =A0 =A0 =A0 4 > > Max IO =A0 =A0 - =A0 =A0304 =A0 =A0 150 > > > The same modern family from Xilinx as an EPC4CE22 is the Spartan-6 > > line: > > =A0 =A0 =A0 =A0 =A0 =A0 =A0XC6S25 EP4CE22 > > LE =A0 =A0 =A0 =A0 - 24,051 =A022,320 > > Memory =A0 =A0 - =A0 936K =A0 =A0594K > > Mult-18x18 - =A0 =A0 38 =A0 =A0 =A066 > > PLL/DCM =A0 =A0- =A0 =A0 =A06 =A0 =A0 =A0 4 > > Max IO =A0 =A0 - =A0 =A0266 =A0 =A0 150 > > > Ed McGettigan > > -- > > Xilinx Inc. > > Thanks for all the thoughts on this. =A0 I realize these things are > still in their infancy, but the "computing power" in general terms > should be comparable between different brands of FPGA's. =A0I'm not > looking for accuracy to 4 decimal places, =A0but just a ballpark > expectation. =A0Ed's values seem to give good apples to apples values > for comparision. > > My first project with fpga went well enough until I tried to fit it > onto a cpld chip only to find that the CPLD chip was 1/1000th the size > of the spartan 3E I was using as a development target. =A0 When > something is 3 orders of magnitude different, I should be able to tell > reasonably easy. > > So my walkaway from this thread is: in =A0the future, a better "marker" > for size is LE's instead of gates. Hi, and again you are about to make the same mistake as before. Don't try to nail down the capabilities of such complex devices as FPGAs to a single number. And don't forget to include the skills of the engineer(s) in your calculation. Have a nice synthesis EilertArticle: 152668
To start with some defination of affordable would be useful. A student affordable budget is much different to that of say a millionaire. I have not seen a board with this chip available but someone in the group may know of one that I don't. There isn't a big choice in this area generally from what I have seen but I will say that could offer this as a service but I'm not sure it that counts as affordable. Typically we might charge GBP =A3500 / USD $800 to produce a custom module that fits one of our simple DIL Headers and fits many of our standard development boards and modules at this sort of technology level can be designed and manufactured by my team in a few days if that is necessary but more typically we turn these sorts of things in 2-4 weeks.. Our next newsletter will be talking more about this for people that get that. Another option some people use is to take some thing like a standard develpoment board for the TVP70025I produced by TI themselves and hand wire it to a standard development board. In this case it's not a really cheap as the TI board is about $400 from what I can see. If you really want to be cheap then you might be worth getting a free, or low cost, CAD package like say Eagle and producing a simple PCB design yourself. You might have a big learning curve on this and there can be large costs if you are not careful but there are a number of manufacturers aimed at prototype/ hobby markets. It might be worth looking up some of the groups more aimed at this sort of thing for better advice if this approach interests you. John Adair Enterpoint Ltd. On Sep 25, 9:57=A0pm, Test01 <cpan...@yahoo.com> wrote: > I am looking for an affordable FPGA development board with TVP70025I > Board. =A0I am assuming that the board can take in VGA input and then > pass the digitized data to FPGA. =A0Is there such a board? > > Thanks.Article: 152669
On 26/09/2011 01:33, fl wrote: > Hi, > I want to learn tcl in Modelsim for FPGA simulation. I find that there > is a directory under modelsim named tcl_tutorial\solutions. But the > traffic.do file cannot run with the following error message under dot > line below. I have installed tcl/tk 8.6 on Windows XP. > > BTW, when I enter : help Tk > > It does give many Tk commands including winfo. > > What is wrong with my system? Thanks. > > Modelsim version is: > ModelSim XE III/Starter 6.4b > > Is it disabled? AFAIK there is no TK support on the OEM/PE/DE versions. Hans. www.ht-lab.com > > > > ............ > do traffic.do > # Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 > 2008 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Compiling entity traffic > # -- Compiling architecture simple of traffic > # -- Compiling entity queue > # -- Compiling architecture only of queue > # -- Compiling entity tb_traffic > # -- Compiling architecture only of tb_traffic > # ** Error: invalid command name "winfo" > # Error in macro ./traffic.do line 13 > # invalid command name "winfo" > # while executing > # "winfo exists .traffic" > # (procedure "draw_intersection" line 4) > # invoked from within > # "draw_intersection"Article: 152670
jleslie48 <jon@jonathanleslie.com> writes: > So my walkaway from this thread is: in the future, a better "marker" > for size is LE's instead of gates. Certainly better, but in no way sufficient :) That'd be like choosing a micro based on DMIPS with no regard for peripherals, IO count, on-chip memory (volatile and non-volatile)... It's just that when you're already used to choosing micros - for your first-pass shortlisting - you already trade all those off without thinking conciously about it. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 152671
On Thursday, 22 September 2011 20:50:18 UTC+1, jleslie48 wrote:
> the xilinx says it has 500,000 gates,
>=20
> the altera says it has
> 22,320 Logic elements (LEs)
> 594 Embedded memory (Kbits)
> 66 Embedded 18 x 18 multipliers
> 4 General-purpose PLLs
>=20
> so are these two fpga's comparable in size/ computing power/ ability
> to support the same VHDL or what?
*Meaningful* "apples to apples" comparison of this type is impossible. Not =
only across vendors, but also across different architectures from the same =
vendor, where the "units" are supposedly the same.
You start out by considering gates, LEs and slices, which get you nowhere u=
seful -- it really doesn't give you any good indication on how efficient yo=
ur design is going to be mapped into the architecture, for example. (Counti=
ng FFs and LUTs isn't helpful because there are restrictions on how they ar=
e used due to bundling). Then the next thing is to try targeting your desig=
n for different architectures. But are the results meaningful? Did you lose=
performance due to a generic design? Did you use the same software? Same v=
ersion? Same settings? Did you correctly convert architecture specific prim=
itives (BRAMs, DSPs, etc.) across architectures? Does your code happen to b=
e optimized for one architecture but not the other? It's difficult for me t=
o imagine hearing satisfactory answers to some of these questions.
So what *can* you do? Look at the context of your application: your needs, =
your experience, and your budget. Which architecture has hard cores for wha=
t you are trying to build? Which vendor supplies readily available soft cor=
es ("IP") that you need? Do you have more experience with one of the vendor=
s? Did one of the vendors give you a better deal? Which device has a cheap =
dev kit you could use? Are free tools available for your target device? If =
you're a student, which vendor is your University using for their classes? =
And so on...
Once you answer those, that initial comparison wouldn't seem so important.
Article: 152672"Test01" <cpandya@yahoo.com> wrote in message news:9fcae308-233a-4826-b1a3-f954e9fac645@m5g2000vbe.googlegroups.com... >I am looking for an affordable FPGA development board with TVP70025I > Board. I am assuming that the board can take in VGA input and then > pass the digitized data to FPGA. Is there such a board? This board has video input and RGB/DVI output: http://www.bitec.ltd.uk/hsmc_quad_video.htmlArticle: 152673
Hello. I'm having trouble finding documentation on how to add timing constraints to this old design that I'm retargeting to another antifuse device (MX). Specifically, I need to know syntax and how to set up timing constraints with Actel's .DCF file. The design has an asynchronous bus interface and the simple constraints that you can add with the GUI are not sufficient. This documentation is probably 20 years old... Thanks in advance to any actel veterans out there. ToddArticle: 152674
Good day, I'm working now with Spartan3 PCI project using the pci32tlite core. But it doesn't support expansion ROM (onboard BIOS) from scratch. Where can I find free PCI IP-core which support expansion ROM. Or maybe someone has experience with adding support of expansion ROM to some of opencores.org PCI core... Big thanks for any help! best wishes, Anatol fpga[at]i.ua --------------------------------------- Posted through http://www.FPGARelated.com
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