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hello... i want to do image processing on SPARTAN-3 DSP TRAINER MODEL : MXS3FK-DSP fpga. i am using xilinx system generator software to build the logic. i am not able to find the way how to store the .bmp image on the above fpga. and how to interface the stored image with the logic built on the matlab simulink based xilinx system generator. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150951
Hi everybody,
I use a Lattice LFXP6C FPGA with Lattice Diamond EDI and Synplify Pro
synthesizer, and I have to design several projects dealings with various
elementary VHDL blocs like Clock divider, Counter, Edge detector, FIFO...
So I'm trying to develop my own package which is defining all of those
components. Therefore I have created a project with all the blocs' source
code and the package source code.
But when I try to synthesize this project, it seems that only one of the
entity is synthesized by SynplifyPro.
Here is two examples of my bloc's source code :
* Clock divider :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity slib_clock_div is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end slib_clock_div;
architecture rtl of slib_clock_div is
-- Signals
signal iQ : std_logic; -- Internal Q
signal iCounter : integer range 0 to RATIO-1; -- Counter
begin
-- Main process
CD_PROC: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= 0;
iQ <= '0';
elsif (CLK'event and CLK='1') then
iQ <= '0';
if (CE = '1') then
if (iCounter = (RATIO-1)) then
iQ <= '1';
iCounter <= 0;
else
iCounter <= iCounter + 1;
end if;
end if;
end if;
end process;
-- Output signals
Q <= iQ;
end rtl;
* Counter :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Counter
entity slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end slib_counter;
architecture rtl of slib_counter is
signal iCounter : unsigned(WIDTH downto 0); -- Counter register
begin
-- Counter process
COUNT_SHIFT: process (RST, CLK)
begin
if (RST = '1') then
iCounter <= (others => '0'); -- Reset counter register
elsif (CLK'event and CLK='1') then
if (CLEAR = '1') then
iCounter <= (others => '0'); -- Clear counter register
elsif (LOAD = '1') then -- Load counter register
iCounter <= unsigned('0' & D);
elsif (ENABLE = '1') then -- Enable counter
if (DOWN = '0') then -- Count up
iCounter <= iCounter + 1;
else -- Count down
iCounter <= iCounter - 1;
end if;
end if;
if (iCounter(WIDTH) = '1') then -- Clear overflow
iCounter(WIDTH) <= '0';
end if;
end if;
end process;
-- Output ports
Q <= std_logic_vector(iCounter(WIDTH-1 downto 0));
OVERFLOW <= iCounter(WIDTH);
end rtl;
* Package :
library ieee;
use ieee.std_logic_1164.all;
use work.all;
package stdlib is
----------------------------------------------------------------------
-- Component declarations
----------------------------------------------------------------------
component SLIB_CLOCK_DIV is
generic (
RATIO : integer := 4 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component SLIB_CLOCK_DIV;
component SLIB_COUNTER is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component SLIB_COUNTER;
end package stdlib;
* Synplify report :
************************************************************
** Synplify Pro **
************************************************************
synpwrap -prj "Std_Package_Standard_synplify.tcl" -log
"Std_Package_Standard.srf"
Copyright (C) 1992-2010 Lattice Semiconductor Corporation. All rights
reserved.
Lattice Diamond Version 1.1.01.50.42.10
==contents of Std_Package_Standard.srf
#Build: Synplify Pro for Lattice D-2010.03L-SP1, Build 142R, Aug 11 2010
#install: C:\lscc\diamond\1.1\synpbase
#OS: Windows_NT
#Hostname: XXXXXX
$ Start of Compile
#Wed Feb 23 10:50:54 2011
Synopsys VHDL Compiler, version comp510rc, Build 126R, built Jul 22 2010
@N|Running in 32-bit mode
Copyright (C) 1994-2010, Synopsys Inc. All Rights Reserved
@N: CD720
:"C:\lscc\diamond\1.1\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time
resolution to ns
@N:"C:\...\Standard\source\slib_counter.vhd":28:7:28:21|Top entity is set
to slib_counter.
VHDL syntax check successful!
@N: CD630
:"C:\...\Standard\source\slib_counter.vhd":28:7:28:21|Synthesizing
work.slib_counter.rtl
Post processing for work.slib_counter.rtl
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Feb 23 10:50:54 2011
Another issue is that I can't use the package in another project.
This second project has only the package source code (and it's own source
which use some elementary blocs). The check syntax and synthesize is ok,
but all the components from my package are replaced by a BlackBox and the
process abords with errors when translating the design.
* Here is the source code :
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.stdlib.all;
-- Serial UART
entity uart is
port (
..
);
end uart;
architecture rtl of uart is
..
-- Clock enable generation
component SLIB_CLOCK_DIV is
generic (
RATIO : integer := 8 -- Clock divider ratio
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CE : in std_logic; -- Clock enable input
Q : out std_logic -- New clock enable output
);
end component;
..
begin
..
UART_BG2: slib_clock_div generic map (RATIO => 8)
port map (
CLK => CLK,
RST => RST,
CE => iBaudtick16x,
Q => iBaudtick2x
);
..
end rtl;
*The warning/error I get :
..
@W: CD280 :"C:\...\UART\source\uart.vhd":208:14:208:27|Unbound component
SLIB_CLOCK_DIV mapped to black box
..
ERROR - ngdbuild: logical block 'UART_BG2' with type 'SLIB_CLOCK_DIV' is
unexpanded
So it seems that I'm doing it the wrong way !
I've made some research and it appears that I should create a VHDL Library,
but I didn't find any useful tutorial to describre this.
Can somebody explain me where are my mistakes ?
Why am I not able to synthesize all the entities of my package's project as
they are independants ? Is it possible to synthesize without a Top ?
What should I do in order to be able to compile my elementary blocs and
then easily reuse it in another projects ?
Thanks for your help !
Regards,
Victor.
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 150952>"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message >news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net... >>I am simulating multipliers [std_logic_vectors] with one factor containing >>'X' and the other has '0's, but the simulation gives me 'X'es as a result >>while I expected '0's. Is this a bug/weakness or is there any logical or >>technical reason at all for [dont' care]*zero<>zero? >> Im working with Altera tools. > >The only technological explanation I can think of is that '0' isn't really >zero. It's "low" and "low" multiplied with "dont' care" is undefined. Maybe >if I do integer conversion first, it will work? > Why have you got 'X's on one input? Why do you not want 'X's on the output? Is this a behavioural model simulation? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150953
>>On 2/23/2011 1:09 AM, salimbaba wrote: >> >>> All the inputs are synchronized with the state machine clock. It has >>> something to do with metastability of the signal that starts the state >>> machine because when i removed it, everything was in place. State >machine >>> was in the IDLE mode as it should be. >> >>That start signal is also an input. >>Is it synchronized? >> >> -- Mike Treseler >> >> >Yes it is synchronized. Ok i have solved the problem, in my opinion it must >be something to do with metastability of the start signal. I have solved it >by ANDing the start signal with a sync signal which i generate after 50 >clock cycles. So, it ensures that no glitches or anything like that passes >through and my state machines don't get triggered. Don't know if it's a >good thing to do but what ever floats the boat, right ? Also, if there's a >better way around lemme know.And also, if anyone knows why this is >happening other than what i think, kindly tell me that also. > > >thanks > Metastability is a random event. Its effects won't be consistent from one test to another. Delaying the ->Starting transition in your FSM might be the right solution to the wrong problem. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150954
[Original post elided] I suspect that you are confusing libraries and packages. A package can contain component declarations relating to multiple entities, bu it does not contain those entities and the corresponding architectures. Also, some synthesis tools - but perhaps not yours - are not very clever regarding multiple user-defined libraries (that is, other than 'work'). I suggest that you look in the tool documentation for a tutorial entitled something like "Working with libraries". You can share pre-compiled libraries between projects, but it may not be simple to do. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150955
I'm just taking over someone else's project and am running it on Cygwin/ISE 12.4 (it was previously building correctly on Linux/12.3). I'm building with a makefile; the first 2 steps are XST, then ngdbuild. 'make' reports that XST fails with an exit code of 1, but XST has actually produced ngc and syr files. The syr file reports no errors, and a few hundred warnings and infos. If I ignore the error code in the makefile, and carry on with ngdbuild, then ngdbuild reports no errors. Any ideas? Under what circumstances does XST return an error exit status? Thanks - DomArticle: 150956
>I'm just taking over someone else's project and am running it on >Cygwin/ISE 12.4 (it was previously building correctly on Linux/12.3). >I'm building with a makefile; the first 2 steps are XST, then >ngdbuild. > >'make' reports that XST fails with an exit code of 1, but XST has >actually produced ngc and syr files. The syr file reports no errors, >and a few hundred warnings and infos. If I ignore the error code in >the makefile, and carry on with ngdbuild, then ngdbuild reports no >errors. > >Any ideas? Under what circumstances does XST return an error exit >status? > >Thanks - > >Dom > You might get a faster/better answer asking on the Xilinx support forums, for instance: http://forums.xilinx.com/t5/Synthesis/bd-p/SYNTHBD --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150957
On Feb 23, 10:16=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >On 2/23/2011 1:09 AM, salimbaba wrote: > > >> All the inputs are synchronized with the state machine clock. It has > >> something to do with metastability of the signal that starts the state > >> machine because when i removed it, everything was in place. State > machine > >> was in the IDLE mode as it should be. =A0 > > >That start signal is also an input. > >Is it synchronized? > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Mike Treseler > > Yes it is synchronized. Ok i have solved the problem, in my opinion it mu= st > be something to do with metastability of the start signal. I have solved = it > by ANDing the start signal with a sync signal which i generate after 50 > clock cycles. So, it ensures that no glitches or anything like that passe= s > through and my state machines don't get triggered. Don't know if it's a > good thing to do but what ever floats the boat, right ? Also, if there's = a > better way around lemme know.And also, if anyone knows why this is > happening other than what i think, kindly tell me that also. > > thanks =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Let's put aside the sync signal and the AND gate, and get back to basics: is the START signal synchronized to the FSM clock, i.e., has it been passed through a couple of flip-flops clocked by the FSM clock before being applied to the FSM? Is the START signal the same as the reset signal? If not, has the reset signal been synchronized to the FSM clock? I'm concerned that you've solved the problem, or perhaps just moved it, without any real understanding of the underlying failure mechanism. And that rarely ends well. Bob Perlman Cambrian Design WorksArticle: 150958
On Thu, 24 Feb 2011 08:56:27 -0600, "RCIngham" >You might get a faster/better answer asking on the Xilinx support forums, >for instance: >http://forums.xilinx.com/t5/Synthesis/bd-p/SYNTHBD Thanks - I've just signed up. I had no idea there was a forum. All those pictures and colours and kudos and profiles and HTML have got be better than content, haven't they? :)Article: 150959
"Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net... >I am simulating multipliers [std_logic_vectors] with one factor containing 'X' and the other has >'0's, but the simulation gives me 'X'es as a result while I expected '0's. Is this a bug/weakness >or is there any logical or technical reason at all for [dont' care]*zero<>zero? > Im working with Altera tools. Morton, 'X' is 'don't know' so the simulator doesn't know the result of multiplying this with another value, forget that the other value is 0. You need to initialise all your inputs at power on to stop this. Nial.Article: 150960
> 'make' reports that XST fails with an exit code of 1, but XST has > actually produced ngc and syr files. The syr file reports no errors, > and a few hundred warnings and infos. If I ignore the error code in > the makefile, and carry on with ngdbuild, then ngdbuild reports no > errors. > > Any ideas? Under what circumstances does XST return an error exit > status? I've observed that XST isn't consistent with exit codes; for some errors it will 'exit 0' and on others it will 'exit 1' (IIRC it will exit 0 if it's a command line error). To be sure, I check if the ngc file ($(SYN_OBJS)) was generated: xst -ifn $(@D)/$(XST_FILE) @if test ! -f $(SYN_OBJS); then exit 2; fi Now, what you're saying is different: that XST exits with an error even though it produced its targets. I haven't seen that and I'm curious as to what you find in your investigation and if this bug can be safely ignored! cheers, saar.Article: 150961
> 'make' reports that XST fails with an exit code of 1, but XST has > actually produced ngc and syr files. The syr file reports no errors, > and a few hundred warnings and infos. If I ignore the error code in > the makefile, and carry on with ngdbuild, then ngdbuild reports no > errors. > > Any ideas? Under what circumstances does XST return an error exit > status? I've observed that XST isn't consistent with exit codes; for some errors it will 'exit 0' and on others it will 'exit 1' (IIRC it will exit 0 if it's a command line error). To be sure, I check if the ngc file ($(SYN_OBJS)) was generated: xst -ifn $(@D)/$(XST_FILE) @if test ! -f $(SYN_OBJS); then exit 2; fi Now, what you're saying is different: that XST exits with an error even though it produced its targets. I haven't seen that and I'm curious as to what you find in your investigation and if this bug can be safely ignored! cheers, saar.Article: 150962
> >Let's put aside the sync signal and the AND gate, and get back to >basics: is the START signal synchronized to the FSM clock, i.e., has >it been passed through a couple of flip-flops clocked by the FSM clock >before being applied to the FSM? > >Is the START signal the same as the reset signal? If not, has the >reset signal been synchronized to the FSM clock? > >I'm concerned that you've solved the problem, or perhaps just moved >it, without any real understanding of the underlying failure >mechanism. And that rarely ends well. > >Bob Perlman >Cambrian Design Works > Hey Bob, That's what i am afraid of because for now i have just kind of put it aside but i know that sometime in future, this thing will come up again, so i need a permanent solution not a way around like the one i have done.And regarding your questions, Yes the START signal is synced to FSM clock, 3 flip-flops in the way. RESET signal is also synced to FSM clock, since i had multiple clocks coming in to the design so i generated a reset synchronizer for each clock. And what to you mean by " Is the START signal the same as the reset signal?" So kindly help me out with it. You people have already done a lot and i really appreciate that =) thanks --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150963
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in message news:8snf99Fq2uU1@mid.individual.net... > "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message > news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net... >>I am simulating multipliers [std_logic_vectors] with one factor containing >>'X' and the other has '0's, but the simulation gives me 'X'es as a result >>while I expected '0's. Is this a bug/weakness or is there any logical or >>technical reason at all for [dont' care]*zero<>zero? >> Im working with Altera tools. > > Morton, 'X' is 'don't know' so the simulator doesn't know the result of > multiplying this with another value, forget that the other value is 0. The point is, what can 'X' be to make 'X'*0 not equal zero?Article: 150964
In article <06CdnZJ_uMNULPvQnZ2dnUVZ8hmdnZ2d@lyse.net>, Morten Leikvoll <mleikvol@yahoo.nospam> wrote: > >"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in >message news:8snf99Fq2uU1@mid.individual.net... >> "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message >> news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net... >>>I am simulating multipliers [std_logic_vectors] with one factor containing >>>'X' and the other has '0's, but the simulation gives me 'X'es as a result >>>while I expected '0's. Is this a bug/weakness or is there any logical or >>>technical reason at all for [dont' care]*zero<>zero? >>> Im working with Altera tools. >> >> Morton, 'X' is 'don't know' so the simulator doesn't know the result of >> multiplying this with another value, forget that the other value is 0. > >The point is, what can 'X' be to make 'X'*0 not equal zero? That's interesting that VHDL does this too. In verilog, 'X' AND 0 = 0 'X' OR 1 = 1 However for the multiply, it's as you indicated above: 'X' * 0 = 'X' Don't know what the language designers chose to do it this way. Good to know VHDL and verilog at least match. --MarkArticle: 150965
Interesting. I've just installed 12.4 on lin64, and ran exactly the same project. xst returned 0, and produced an syr that was essentially identical to the Cygwin/Windows version (I didn't get a chance to compare the ngc's). Lots of forward-backslash differences, some case differences, but no numbers different, apart from the LSB of some max frequencies. It does look like there might be a problem on the Windows XST. -DomArticle: 150966
"Mark Curry" <gtwrek@sonic.net> wrote in message news:4d66d8d2$0$10596$742ec2ed@news.sonic.net... > In article <06CdnZJ_uMNULPvQnZ2dnUVZ8hmdnZ2d@lyse.net>, > Morten Leikvoll <mleikvol@yahoo.nospam> wrote: >> >>"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in >>message news:8snf99Fq2uU1@mid.individual.net... >>> "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote in message >>> news:FuGdnUiJXNslvfvQnZ2dnUVZ8vGdnZ2d@lyse.net... >>>>I am simulating multipliers [std_logic_vectors] with one factor >>>>containing >>>>'X' and the other has '0's, but the simulation gives me 'X'es as a >>>>result >>>>while I expected '0's. Is this a bug/weakness or is there any logical or >>>>technical reason at all for [dont' care]*zero<>zero? >>>> Im working with Altera tools. >>> >>> Morton, 'X' is 'don't know' so the simulator doesn't know the result of >>> multiplying this with another value, forget that the other value is 0. >> >>The point is, what can 'X' be to make 'X'*0 not equal zero? > > That's interesting that VHDL does this too. In verilog, > 'X' AND 0 = 0 > 'X' OR 1 = 1 > > However for the multiply, it's as you indicated above: > 'X' * 0 = 'X' > > Don't know what the language designers chose to do it this > way. Good to know VHDL and verilog at least match. I have seen similar weirdness in spreadsheets. For OpenOffice Calc AND(NA();FALSE()) equals NA() and OR(NA();TRUE()) too, and NA()*0=NA(). I can understand the last one, since cells can be potential non-numeric in spreadsheets, but for std_logic_vectors the definition should be straight.Article: 150967
Hi RCIngham, I may be a bit confused as I'm a newbie in the FPGA world... So as I've found, I should set up a library. But I don't know how to do it. I didn't find any documentation about creating libraries and the Synplify Pro User Guide is not helpful on that topic ! I will try to find that kind of guide. Thanks for your answer. >[Original post elided] > >I suspect that you are confusing libraries and packages. A package can >contain component declarations relating to multiple entities, bu it does >not contain those entities and the corresponding architectures. > >Also, some synthesis tools - but perhaps not yours - are not very clever >regarding multiple user-defined libraries (that is, other than 'work'). I >suggest that you look in the tool documentation for a tutorial entitled >something like "Working with libraries". > >You can share pre-compiled libraries between projects, but it may not be >simple to do. > > >--------------------------------------- >Posted through http://www.FPGARelated.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150968
On Thu, 24 Feb 2011 10:11:24 +0100, "Morten Leikvoll" <mleikvol@yahoo.nospam> wrote: >I am simulating multipliers [std_logic_vectors] with one factor containing >'X' and the other has '0's, but the simulation gives me 'X'es as a result >while I expected '0's. Is this a bug/weakness or is there any logical or >technical reason at all for [dont' care]*zero<>zero? >Im working with Altera tools. You haven't given us enough information. What are you simulating? Is it a '*' operator, or is it your own implementation of a multiplier? Do you know where the X's are coming from? If you are actually simulating a '*' operator, then you need to know that VHDL doesn't define '*' on std_logic_vectors; it only defines it on physical types, ints, and reals. For these types, there is no X input. The numeric_std package has various signed/unsigned/natural multiplies, but not std_logic_vector multiplies. As Brian said, the package writer may have decided to special-case the situation where one input is all zeros, but why bother? Are you sure that all possible gate-level hardware implementations of a multiplier propagate a zero output in this case? Even if you are, there's no sense in hiding X's; you need X propagation so that you can detect and fix them. It's not the purpose of a simulation package to provide an exact copy of whatever simulation results your preferred implementation may end up with. Note that the numeric_std multiplies always set the result to all X's if any input bit is 'X'. BTW, if you do integer conversion first, as you suggest in another post, it won't 'work' either. If you use 'TO_01', you'll get a warning if you try to convert an 'X'. You can convert '0' to integer 0 if you want to, but that wont affect any of the numeric_std multiplies.Article: 150969
> The point is, what can 'X' be to make 'X'*0 not equal zero? You have to initialise the signal that is 'X' to either '1' or '0'. NialArticle: 150970
> The point is, what can 'X' be to make 'X'*0 not equal zero? Sorry, I might have mis-understood your question. It's not a mathematical question, in that zero * anything = 0. It's a functional simulation problem, the simulator probably parses the inputs to a function (without considering what the function is), says it doesn't know what the input is so it can't determine the output. To stop seeing the X's propogate through a design you have to initialise them at the start of the simulation. Nial.Article: 150971
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
writes:
> It's a functional simulation problem, the simulator probably parses the
> inputs to a function (without considering what the function is), says
> it doesn't know what the input is so it can't determine the output.
This does not take place at parse time.
At run time the simulator will pass the left and right values (which
can be ('U','X','0','1','Z','W','L','H','-') to the function. The
problem is the implementation of the "*" function that Morten (or some
library) has defined for std_logic_vector. This function should check
if one of the arguments are 0 and then return 0. If not the function
could be overloaded it to implement this behaviour.
> To stop seeing the X's propogate through a design you have to initialise
> them at the start of the simulation.
This is bad practice. X's are your friend. They will let you know
you're using unqualified data. State, control register, qualifiers
(e.g. cache valid bits), etc. should be reset using one or more reset
signals.
//Petter
--
.sig removed by request.
Article: 150972On 02/25/2011 02:32 PM, Nial Stewart wrote: >> The point is, what can 'X' be to make 'X'*0 not equal zero? > > Sorry, I might have mis-understood your question. > > It's not a mathematical question, in that zero * anything = 0. > > It's a functional simulation problem, the simulator probably parses the > inputs to a function (without considering what the function is), says > it doesn't know what the input is so it can't determine the output. That all depends on the simulation algorithm. There's no reason why it couldn't return 0 in this case. > To stop seeing the X's propogate through a design you have to initialise > them at the start of the simulation. It would be better if the simulator would be able to work with 'X' signals, and return sensible results. For instance, if you turn a computer on, the RAM memory will be initialized to a random state, and it will still work correctly every time it boots up. It would be nice if you could represent that unknown state by filling the memory with 'X' during a simulation, and see if the model will still run correctly. This requires that the simulator knows that X & 0 = 0, and X | 1 = 1, and as a consequence, that X * 0 = 0.Article: 150973
"Dom Bannon" <nospam@nospam.com> wrote in message news:la1fm6pel35182jhpkd5b19cvus3h28te7@4ax.com... > On Thu, 24 Feb 2011 10:11:24 +0100, "Morten Leikvoll" > <mleikvol@yahoo.nospam> wrote: > >>I am simulating multipliers [std_logic_vectors] with one factor containing >>'X' and the other has '0's, but the simulation gives me 'X'es as a result >>while I expected '0's. Is this a bug/weakness or is there any logical or >>technical reason at all for [dont' care]*zero<>zero? >>Im working with Altera tools. > > You haven't given us enough information. What are you simulating? Is > it a '*' operator, or is it your own implementation of a multiplier? > Do you know where the X's are coming from? This is a general builtin multiplying operator on std_logic_vector. The use has no meaning for this discussion. I am only using ieee.std_logic_1164 and ieee.std_logic_unsigned packages. > If you are actually simulating a '*' operator, then you need to know > that VHDL doesn't define '*' on std_logic_vectors; it only defines it > on physical types, ints, and reals. For these types, there is no X > input. In Quartus II (and its Modelsim tools) multiplication is obviously defined. Quartus infers DSP multipliers, and God knows what Modelsim does, but it does multiply. I haven't tried to convert to integer and back, but I believe that would work (althoug the code layout wouldn't look as nice). This is the std_logic_vector multiplying discussion. > The numeric_std package has various signed/unsigned/natural > multiplies, but not std_logic_vector multiplies. As Brian said, the > package writer may have decided to special-case the situation where > one input is all zeros, but why bother? Are you sure that all possible > gate-level hardware implementations of a multiplier propagate a zero > output in this case? Even if you are, there's no sense in hiding X's; > you need X propagation so that you can detect and fix them. It's not > the purpose of a simulation package to provide an exact copy of > whatever simulation results your preferred implementation may end up > with. > Note that the numeric_std multiplies always set the result to all X's > if any input bit is 'X'. That is what makes no (or little) sense. I am asking for any physical 'X' in the valid std_logic space that would make this 'X'. Not even a metastable factor would do that as long as the other factor is valid '0's. > BTW, if you do integer conversion first, as you suggest in another > post, it won't 'work' either. If you use 'TO_01', you'll get a warning > if you try to convert an 'X'. You can convert '0' to integer 0 if you > want to, but that wont affect any of the numeric_std multiplies. A warning I can live with. But I wonder what the invalid result will be.. Since integers cant go 'x' the result may end up with what I need. I prefer that to conditional simulation code.Article: 150974
On Fri, 25 Feb 2011 14:54:50 +0100, Petter Gustad
<newsmailcomp6@gustad.com> wrote:
>At run time the simulator will pass the left and right values (which
>can be ('U','X','0','1','Z','W','L','H','-') to the function. The
>problem is the implementation of the "*" function that Morten (or some
>library) has defined for std_logic_vector. This function should check
>if one of the arguments are 0 and then return 0. If not the function
>could be overloaded it to implement this behaviour.
Why? What is a 'std_logic_vector'? What does it encode? It could be an
IEEE float, for example. In this case, it's not true that
0*anything==0. 0 times infinity is NAN; 0 times NAN is NAN (according
to some, at least), and what about signed zero? Even some integer
representations (Perl?) include a NAN.
The OP is fixated on 0*anything = 0, but this is an application
problem; it's nothing to do with VHDL. VHDL defines multiply only for
physical, real, and integer types. Anything else is the designer's
problem; it's not VHDL's problem. The numeric_std multiply is not
"wrong". If Morten doesn't like it, he can just roll his own.
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