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In comp.arch.fpga Quadibloc <jsavard@ecn.ab.ca> wrote: (snip) > I keep hoping for an FPGA that would be suitable for replicating the > internal logic of an IBM 360/195, as an example, so that if I did > build a replica of a computer, I could have a reasonably efficient > implementation which would give performance at least roughly in the > ballpark of a Pentium - at least an early one. Does anyone know if the information needed to do that still exists? I would go for the 360/91, just a little be easier. -- glenArticle: 146051
Hello, I have a Spartan 3 Starter board. I used to program it with my parallel JTAG cable, but I now do my implementations on a laptop without a parallel port. I am in the market for a USB JTAG cable. Requirements: Xilinx ISE 11.1 running on Fedora 12. Any suggestions? Will the digilent cable suffice? Thanks in advance. -- Jason Thibodeau www.jayt.orgArticle: 146052
On Mar 5, 9:14=A0am, Andy Peters <goo...@latke.net> wrote: > Putting a processor inside an FPGA has proven to us to be a bigger PITA t= han it's worth. > Consider than instead of V4FX, you can use an S3AN and a standalone > PPC and you'll pay a whole lot less. Plus the various Freescale PPCs > have DDR memory and Ethernet and DMA controllers that don't suck, and > you're not stuck with crappy tools. Yes, you should always 'reality check' the alternatives. It can make sense if the resource really is 'free', but SRAM FPGA's still need external code memory, and when you look at those newest uC prices, they are LESS than SRAM!! We could use the A2F060, if the price and package are right. - but we consider it more a uC + CPLD, than a FPGA. -jgArticle: 146053
> > Yes, but at a slightly higher functional level. > > Chipscope/Signal Tap are for monitoring individual lines/groups (AFAIK). > Yes, now that I've seen the way the target works it appears to be a 4k > bank of 16-bit read/write registers. Yes, but you only need to implement the address span and data depth in the Target FPGA that's required. I've often used it with fewer than 8 target registers. Your synthesis tool should then optimise out any logic that isn't required. > > I'll add a page to the Web site lising the text of the Excel module > > tonight. This is probably the simplest way of explaining what's happening. > Sounds good. Thanks for making this available. OK, it's not a seperate page but I've added the VBA OnePinModule as a text file in Downloads with a note in Host Software. Please no sniggering about my software 'prowess', it took me a while to get it all going. NialArticle: 146054
On 02/27/2010 08:52 AM, John_H wrote: > On Feb 26, 4:52 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > wrote: >> Hello, >> >> I am using Xilinx ISE 11.1, and I need to place some components in >> certain areas of the FPGA. I have never done manual PaR, so here are a >> few questions: >> 1) Do I need to manually place each and every net? >> 2) Is it possible to just place 'blocks' of each component in a general >> area of CLB on the device, and let the PaR algorithms auto route any >> connecting nets? >> >> Thanks in advance, >> Jason > > You can also use the User Constraints File to explicitly place > individual elemens using a LOC constraint or associate many components > into an AREA_GROUP constraint. > > Check out the Constraints Guide at http://bit.ly/8YkuR9 for the > details. I am finally working on this, and I have a question. I am inside PlanAhead. I have created a Pblock names sensor_1. I am attempting to add all of instance U0, U1 and U2 to the pblock. I am starting with U0. I have instances such as: U0/count_clock_0, U0/count_clock_1 etc. I want to add ALL of U0 to the pblock I have created. Is there some wildcard i can use to add all the instances beginning with U0? Such as: hdi::pblock addInstance -project ring_sensor -floorplan floorplan_1 -name sensor_1 -instance U0/* -clearLocs yes This doesn't work, as it doesn't accept the wildcard. Should I just Shift+click until all of U0 is selected in the netlist window, and drag+drop from there? Thanks in advance. -- Jason Thibodeau www.jayt.orgArticle: 146055
> > It's obviously not universal enough! > So, does it work with OpenOffice ? No, the OpenOffice spreadsheet doesn't have any VBA capability as fair as I'm aware. > I could not see an example timing/protocol diagram ? It's _very_ simple. If you look at the Quick Start Guide section of the web page you'll see the process in the target FPGA that implements the read and writes functionality. That's all you need to worry about, all the rest of the functionality _should_ work end to end. (I can add a Modelsim screen capture to deomonstrate this but it's so simple this shouldn't be needed). > The other uses that spring to mind are > * Use with a Microcontroller, in which case a SW-pin version on the > target would be needed. > Might be as simple as a slow enough clock ? Aye perhaps, but do most uCs not have decent in-circuit debuggers etc these days? The serial clock speed is set via a constant in the 1 Pin Module design. This could be changed to something that can be set with an internal write, but I had to decide on a set of functionality to get done and tested and this was way down the list. > * Use with CPLDs, in this case, minimal-logic is the requirement. A minimal set of registers can be implemented in the target logic with about 170 logic elements. The interface could be modified to only transfer 1 byte at a time to reduce this further but there will be a limit as to how small it can be got and there probably aren't that many more designs that will be enabled by doing this. Again it was a question of drawing a line in the sand to get it done and tested. If you need something much smaller the 1 Pin Interface probably isn't your solution. Thanks for the feedback/queries, Nial.Article: 146056
Quadibloc wrote: > On Feb 8, 12:46 am, Mike Hore <mike_hore...@OVE.invalid.aapt.net.au> > wrote: >> (see below) wrote: >>> On 05/02/2010 18:19, in article >>> badc12c3-cb2b-4ce9-9543-237d60fc2...@o8g2000vbm.googlegroups.com, "Eric >>> Chomko" <pne.cho...@comcast.net> wrote: >>>> Has anyone created a copy machine of an old system using an FPGA? I >>>> was wondering if it would be possible to take an entire SWTPC 6800 and >>>> compile the schematics and have it run on an FPGA board.? Wouldn't >>>> even have to be the latest Xylinx product, I suspect. >>> I think such a project would valuable, and perhaps even more valuable if it >>> aimed to recreate a machine of the "heroic" era -- a 7094, an Atlas, or a >>> KDF9, say. Perhaps even a Stretch. >> A KDF9, maybe, but Stretch? You'd have to be seriously masochistic, or >> downright insane :-) > > I keep hoping for an FPGA that would be suitable for replicating the > internal logic of an IBM 360/195, as an example, so that if I did > build a replica of a computer, I could have a reasonably efficient > implementation which would give performance at least roughly in the > ballpark of a Pentium - at least an early one. > I'd like to see a Honeywell Multics machine done in FPGA. Doubt I'll ever have time, though.Article: 146057
Eric Chomko wrote: > On Mar 3, 7:06 pm, Greg Menke <guse...@comcast.net> wrote: >> Peter Flass <Peter_Fl...@Yahoo.com> writes: >>> Michael Wojcik wrote: >>>> Peter Flass wrote: >>>>> Hey! C's finally caught up to PL/I. Only took them 50 years, and then >>>>> of course all the features are just tacked-on in true C fashion, instead >>>>> of thought-through. >>>> Well, that's rather insulting to the members of WG14, who spent a >>>> decade designing those features. Fortunately, they published the >>>> Rationale showing that, in fact, they were thought through.[1] And a >>>> great deal of documentation describing the process is available in the >>>> archives.[2] >>>> If you'd care to show why you think otherwise, perhaps there would be >>>> some grounds for debate. >>> "The flexible array must be last"? >>> "sizeof applied to the structure ignores the array but counts any >>> padding before it"? >>> C is a collection of ad-hoc ideas. WG14 may have put a great deal of >>> thought into how to extend it without breaking the existing mosh, but >>> that's my point, it's still a mosh. >> iostream formatting operators, because we really need more operator >> overloading and no enhancements are too bizarre in service of making >> everything, (for particular values of everything), specialized? >> >> Oh but wait, you can compile, install and dig your way through Boost so >> as to avoid the fun & games of vanilla iostream. >> >> Thank goodness printf and friends are still around. > > More generally when speaking about C++, than goodness C is still > around. > I've said before, C started out as a fairly simple and clean language, with possibly a few rough spots. Unfortunately instead of accepting it on its own terms, and maybe coming up with "D", people tried to turn it into a real 3GL, but then it gets in its own way. It's lots of fun reading some of the Gnu stuff to see a language less readable than APL.Article: 146058
On Mar 5, 10:30=A0am, "Nial Stewart" >(I can add a Modelsim screen capture to deomonstrate this but it's so simp= le this shouldn't be needed). That could help broaden the use. > > The other uses that spring to mind are > > * Use with a Microcontroller, in which case a SW-pin version on the > > target would be needed. > > Might be as simple as a slow enough clock ? > > Aye perhaps, but do most uCs not have decent in-circuit debuggers > etc these days? Yes, but they do not all include communications channels, and it is quite rare to access the debug Flow from user code. There are numerous instances where a simple PC access to an operating embedded system, would be nice to have, (and the UART may be already committed.) -jgArticle: 146059
On Mar 5, 10:15=A0am, "Nial Stewart" > > OK, it's not a seperate page but I've added the VBA OnePinModule as > a text file in Downloads with a note in Host Software. I had a quick look - what is this file called ? -jgArticle: 146060
On Mar 4, 10:21=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Mar 5, 10:15=A0am, "Nial Stewart" > > > > OK, it's not a seperate page but I've added the VBA OnePinModule as > > a text file in Downloads with a note in Host Software. > > I had a quick look - what is this file called ? > > -jg In the Downloads section "VBA One Pin Module". NialArticle: 146061
On Mar 4, 7:42=A0am, Adam G=F3rski <totutousungors...@malpawp.pl> wrote: > Pete Fraser pisze: > > > > > I'm going to be travelling soon, and will continue to > > do FPGA design from the road. I'll need to get a > > new laptop for this. > > > Any thoughts? > > I think something based on the Core i7-620M might > > be fast enough and low power, but they seem rare. > > Looks like I'll probably end up with something with > > a Core i7-720QM or a Core i7-820QM. > > Anybody here have any experience with on of these > > machines? Is there another processor I should be looking at? > > > The obvious OS with a new machine would be Windows 7, > > 64-bit, but I'm not sure my software will run on that. > > I'm running ISE Foundation 10.1 (and don't plan on > > upgrading quite yet). I also use Modelsim XE, but will > > be upgrading to Modelsim PE or Aldec. > > > It's not clear what software runs on what OS. It seems > > that I might be safer with 32-bit XP for the Modelsim > > and the Xilinx software. Windows 7 Professional > > seems to have a downgrade option to XP. Does that > > mean I choose to install one or the other OS, or can > > I install both and switch between them? 7 Pro seems > > to have some sort of XP mode. Will that work for these > > tools? Is there a performance penalty over a real XP > > installation? Can I emulate XP 32-bit under W7 64-bit? > > > Thanks for your thoughts and suggestions. > > > Pete > > Use Remote desktop or similar . > You can have really powerful PC for fpga compilation this way. > If you have inet connection of course. > > Adam Way back when, this software was purchased (PC Anywhere sticks in my mind). Then I believe MS included it with WinXP, that was how IT used to "fix" my PC. But I see now it is back to being commercial software. This this software different somehow than the stuff they had in WinXP or is that gone again? RickArticle: 146062
On Mar 2, 2:28=A0pm, Eric Smith <space...@gmail.com> wrote: > > Reminds me of some of the players that tried to compete with Intel on > high-end x86 processors. =A0Only AMD has been successful at that. =A0 You call that success??? AMD is losing money hand over fist and there is no relief in sight! At one time they played leap frog with Intel in terms of who had the fastest parts, bragging rights and therefore higher average selling prices. But AMD has been sucking wind for more years than the cycles used to take. They are a full generation of process technology behind. They had to sell off their fabs to raise cash to stay afloat. Unless AMD has some really big trick up their sleeve (something better than a one time payment from Intel which makes up for maybe one year's losses) they are going to go the way of Zilog. Personally, I don't see them surviving, at least well enough to actually make an impact in the market. Intel may keep them around just to keep the FTC off their aggressive and illegal pricing backs. RickArticle: 146063
On Mar 5, 11:41=A0am, NialS <n...@nialstewartdevelopments.co.uk> wrote: > On Mar 4, 10:21=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > I had a quick look - what is this file called ? > > In the Downloads section "VBA One Pin Module". Hmm, a revisit and a couple of refreshes and voila! I also grabbed the .xls, and dropped it into OpenOffice 3.? It warns about macros, and seems to add a rem in front of everything (another protection?), but when I remove those, it shows glimmers of operation, but I think there may be VBA / OpenOffice.Basic variations. I can step some functions, so it seems likely this can be made to work on Open Office as well ? -jgArticle: 146064
> > In the Downloads section "VBA One Pin Module". > > Hmm, a revisit and a couple of refreshes and voila! > > I also grabbed the .xls, and dropped it into OpenOffice 3.? > > =A0It warns about macros, and seems to add a rem in front of everything > (another protection?), but when I remove those, it shows glimmers of > operation, but I think there may be VBA / OpenOffice.Basic variations. > I can step some functions, so it seems likely this can be made to work > on Open Office as well ? It would be great if it could. Does OO have the same User Form building abilities as Excel? NialArticle: 146065
On Mar 2, 4:28=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Mar 3, 12:22=A0am, Symon <symon_bre...@hotmail.com> wrote: > > > This lot seems to be revealing a bit more about their stuff. > > >http://www.mercurynews.com/breaking-news/ci_14493616 > > >http://www.tabula.com > > Time will tell.... > > meanwhile, over in the other corners, anyone remember Triscend ? > > Well, others are having a crack at the same market, but > slightly updated, for 2010. > > =A0See Cypress PSoC5 (Data, no open samples yet) and the just unveiled > Actel A2F200 (supposedly real silicon & Eval) > > =A0These both bundle a FLASH Cortex uC with Analog and FPGA fabric. > > =A0Sounds great on a marketing-lunch-napkin, but the fish-hook in this > has always been price, and the conflict of constrain of > Flash.Ram.cells. > > =A0The sampling smaller sibling, the PSoC3 has moved to ~$20 in price > indicators, and the A2F200 is showing ~$40 =A0(no indications yet of the > A2F060) > > =A0You can get a choice of ARM core, for $1-$3, and a choice of CPLD- > FPGA for $3-$6, so that single-package-premium really narrows down the > customers. > > -jg Yeah, I have been watching the Cypress stuff and I am not overly impressed. I guess the new stuff far outdoes the PSOC1, but at those prices they are addressing a totally different market and likely will only find a home in very space constrained designs. I just heard about the Actel parts and they seem interesting. But I bet they bring a seriously painful price. That will be the determiner. The PSOC3/5 and Actel SmartFusion parts are also very different in size with Actel SmartFusion coming in a 256 BGA at the smallest and the PSOC3/5 a 100 pin package at the largest IIRC. Other FPGAs don't do analog so well, but they can be used with a soft processor to compete with the low end of these parts. Rick RickArticle: 146066
On Mar 2, 8:03=A0pm, -jg <jim.granvi...@gmail.com> wrote: > On Mar 3, 12:22=A0am, Symon <symon_bre...@hotmail.com> wrote: > > > This lot seems to be revealing a bit more about their stuff. > > >http://www.mercurynews.com/breaking-news/ci_14493616 > > A better overview is herehttp://www.eetasia.com/ART_8800599499_499495_NT_= b33fb563_2.HTM > > =A0Some of what Tabula say, reads more like a patent dance, than any > technical explanation. > > =A0So, it is locally 1.6GHz, with time-sliced threads. > It might save Logic and routing, but it will have no config-memory > saving, and it ADDS the complexity of > rapid config multiplex. (not to mention power impacts) > > =A0We already have Achronix climing 1.5GHz PLDs since 2008, and XMOS > have 400-500Mhz hard-time-sliced cores shipping also. > > =A0Tabula have some rather quaint terminology, as they try to spin what > they do, but designers have always tried to do more serially & > pipeline, to save resource, if they can. > > =A0It seems their SW will do the 'thread slice & dice' for you, and that > may be the critical point. > > =A0If that works, and you can debug it, it could be useful. If it fails, > it will fail in a tangle. > > -jg Yeah, a lot of their success will depend on the tools. Not only do they need to work, they need to be usable. I am trying to think how to write VHDL for hardware that really is sequential as well as concurrent. RickArticle: 146067
On Mar 5, 12:15=A0pm, NialS > > I can step some functions, so it seems likely this can be made to work > > on Open Office as well ? > > It would be great if it could. > > Does OO have the same User Form building abilities as Excel? Well, I can see the source code, and the Form itself, and I can move/drag/edit the buttons and placements on the form, and I can see what looks like all the sources. But the chatter on actually using this with DLLs, seems ominously quiet.. it does not like the DLL syntax, and examples were not easy to find... Could be worth starting with something very simple, proof-of-pathway stuff, or you could look at Lazarus/fpc, which can also build command line versions ?Article: 146068
On Mar 5, 12:43=A0pm, rickman <gnu...@gmail.com> wrote: > On Mar 2, 8:03=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > > =A0It seems their SW will do the 'thread slice & dice' for you, and tha= t > > may be the critical point. > > > =A0If that works, and you can debug it, it could be useful. If it fails= , > > it will fail in a tangle. > > > -jg > > Yeah, a lot of their success will depend on the tools. =A0Not only do the= y need to work, they need to be usable. =A0I am trying to think how to wri= te VHDL for hardware that really is sequential as well as concurrent. > > Rick I'm exercising the XMOS devices currently, and they are certainly interesting devices. They have a truly hard/deterministic threaded core and some quite good tools. Sadly, the Docs are scattered and read like an in-joke. (and on a device as left-field as XMOS, knowing what it can & can't do, is important) I am currently seeing if a design that is CPLD+RAM, can work on XMOS. RAM in there is easy, (way more than any similar priced CPLD/FPGA) but hitting the speed targets in SW, is 'interesting', but by careful slice into threads, it might just make it. 4 threads come at zero speed cost, as do 32 bit datapaths. Tabula's approach seems a morph of this. It should work well on code that needs to be hard-deterministic, and that can serialize nicely to shrink logic. Something like Base-station math-ops would be a good market footprint, and it is unlikely to be low power. Memory&bandwidths will be the other key factors. -jgArticle: 146069
On 3/4/2010 12:46 PM, Eric Smith wrote: > time they ship product. Successful startups usually have something > that is *many* times better than the existing products, on some axis > almost entirely orthogonal to the prior metrics. > > Eric Mate, Ever wonder if you've been doing this too long? Did you write that last phrase with a straight face? Cheers, Syms.Article: 146070
On 3/4/2010 11:06 PM, rickman wrote: > to actually make an impact in the market. Intel may keep them around > just to keep the FTC off their aggressive and illegal pricing backs. > > Rick Yep. http://www.theregister.co.uk/2009/11/18/amd_to_pay_down_debt/Article: 146071
scott@slp53.sl.home (Scott Lurndal) writes: > Eric Chomko <pne.chomko@comcast.net> writes: > >>More generally when speaking about C++, than goodness C is still >>around. > > One can actually write very maintainable and quite performant applications > in C++ by restricting the subset of C++ the version 2.1 flavor (no STL, > no Templates, no Exceptions, no run-time typing). Basically C with classes. > > One can still use printf, snprintf, setjmp/longjmp etc, while reaping the > data hiding and inheritance/interface benefits of C++. > > I've worked on three different operating systems or hypervisors written in > such a restricted dialect. > > And yes, I think the iostream stuff is a useless abominable hack. > > scott C++ does make for a nice "type-safe linking" C compiler. The compile & link time type checking is an improvement, but no so much when it comes time to dig into the object code and symbol tables. Probably would also agree wrt classes etc, as clumsy as the C++ object model is, it improves on structs. But I think having exceptions around is of help- goto's out of nested code always make me feel unclean. Runtime typing in C++, now that is pretty funny! GregmArticle: 146072
> What size of designs are you working on? FWIW, I've had good luck > doing smaller stuff in WinXP running from the Bootcamp partition on a > MacBook using VMware. I've also gotten stuff built on an EEE901A with > WebPack 10.1 under EEEbuntu. I've also used a small Macbook for samll designs running Ubuntu in a VM. The nice thing about running ISE on Linux is that you can ssh -X into the VM and get it to display in the Mac's X server. -- mac the naïfArticle: 146073
I've tried to use an inout reg with quartus and it doesn't give a warning. However, I read on the internet that an inout port can only be a wire. Which one is true?Article: 146074
Michael Wojcik wrote: > Charles Richmond wrote: >> A "thunk" was *and* is a method for implementing "call by name". But a >> compiler providing "thunks" has *not* been written for some time now. > > That's rather dubious. > > We don't know that no one has written a compiler that provides > ALGOL-style thunks recently. To demonstrate that you'd have to prove a > negative. > > If we relax the definition to allow named as well as anonymous > functions, then someone could argue that get-accessors for properties > are thunks, and those are quite common in modern languages. > (Sorry this is a week late - I'm still catching up from being away) In functional languages with lazy evaluation (e.g. Haskell) arguments are passed unevaluated, so an actual argument that is an expression needs to be parcelled up as a piece of code and an environment in which is is to be evaluated (i.e the bindings of the free variables in the code). This amounts to a thunk. The only difference from call by name is that it doesn't require re-evaluation on every reference, as the absence of explicit assignment in the language guarantees that the value will not change between references in the same function invocation. --brian -- Wellington, New Zealand "I don't respond to Christopher Hitchens in public, on the general principle that you should never mud-wrestle with a pig because you both get filthy and the pig likes it." -- Tony Judt
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Compare FPGA features and resources
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