Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Jun 27, 8:56=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > and the VERY first design i used to benchark resource useage S3 vs V6 > it FROZE > > running delay-based LUT packing... > > goes forever.. hmm idea > > maybe it will finish by the time S6 become available? ;) Pfffft - glad I was not drinking coffee there!Article: 141551
On Jun 27, 1:38=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Jun 27, 8:56=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > > > and the VERY first design i used to benchark resource useage S3 vs V6 > > it FROZE > > > running delay-based LUT packing... > > > goes forever.. hmm idea > > > maybe it will finish by the time S6 become available? > > ;) Pfffft - glad I was not drinking coffee there! ok, here some comparison S3-area optimize 1447 slices S3-speed optimize 1482 slices S6-area optimize 606 slices S6-speed optimize 557 slices !? (only synthesis option changed) the design tested is a known 32 bit processor, well Xilinx is defenetly enhancing the marketing-gate strategy the SLICE count is more then ever un-comparable so more then ever need really run P&R on read designs before making any commitment of IP core utilizations AnttiArticle: 141552
On Sat, 27 Jun 2009 01:56:29 -0700 (PDT), Antti <Antti.Lukats@googlemail.com> wrote: >seems some V6 boards have been shipped, here > >http://sls.smugmug.com/gallery/5440422_Wj6jD#524855270_G47y9 Hmmm, there looks to be something very ... prototypish about the way that chip is mounted to the board especially compared with the nice clean publicity photo... http://www.xilinx.com/products/devkits/EK-V6-ML605-G-image.htm It remins me of a board I once saw, where the designer assumed a PLCC-100 in a PGA socket had the same pinout as the PGA-100 equivalent part, and didn't check... I have to wonder if that fat round cylinder hides a bundle of 1156 little wires ... ouch! are you sure "shipping" is actually an applicable word for this case? - BrianArticle: 141553
Hi :) for many years Xilinx has tried to HIDE the schematics of the USB Cable, but as of today Xilinx has made it public !!! really good news, no more guessing needed http://www.xilinx.com/support/answers/33028.htm from this page get the archieve, look in the schematics page 14 AnttiArticle: 141554
Hi Folks, I am currently in the process for selecting an FPGA for one of my projects. I have always used Xilinx FPGAs but now am considering using Altera. The Altera Cyclone III FPGAs looks like a very cost effective device but I have no idea how well it compares performance wise (will be used for DSP application) to a Spartan3E. I would be very grateful if someone would be able to provide me few pros and cons of Cyclone III. Thanks SudhirArticle: 141555
Antti <Antti.Lukats@googlemail.com> wrote: > Hi :) > for many years Xilinx has tried to HIDE the schematics of the USB > Cable, > but as of today Xilinx has made it public !!! > really good news, no more guessing needed > http://www.xilinx.com/support/answers/33028.htm > from this page get the archieve, look in the schematics page 14 Let's hope this schematic is a sign of openness and not a release flaw... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 141556
Antti.Lukats@googlemail.com wrote: > On Jun 27, 3:22 am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: >> -jg wrote: >>> On Jun 27, 4:29 am, "Antti.Luk...@googlemail.com" >>>> the above is not 1:MIO odds case or is it? >>>> now, i did include partial info, not only 11111 but also "just bad" >>>> bit file can damage >>>> i mean bit files that are INVALID, without proper CRC and trailer >>> See Ed's post. >>> Is this a case of a step-back in the Silicon, or a Step back in the >>> DOCs ? >>> Did they explicitly say the CRC check was bypassed ? >>> ["is possible to damage an FPGA with a badly corrupted bitstream, but >>> it takes more than a sync word followed by ones to do this. "] >>> Is that 'design-corrupted', but with a valid CRC ? >>> -jg >> Assuming that the bitstream information is correct up until the real >> configuration frame data starts, damage may occur with a corrupted >> bitstream after that point. Loading all ones can be particular >> problematic as most configuration cells are active high. >> >> Configuration of an FPGA is a continual process and as each frame is >> filled the data is written in to the actual configuration cells. If a >> corrupt bitstream starts connecting multiple drivers with different >> states to the same nets then contention can occur and damage may result >> if the contention is severe enough and left in that state for long >> enough. The CRC check at the end of the bitstream won't avoid the >> contention as it is already occurring in the device. >> >> Back in the original Virtex days, we had one customer that had poor >> source code control and communication between designers and board techs >> coupled with different die sizes on the same board. On more than one >> occasion the bitstreams were loaded into the wrong device leading to >> catastrophic failure of the device. This was fixed in all future >> families with additional header information and configuration state >> machine logic to prevent the wrong bitstream from being loaded. >> >> Spartan-6 is as robust in this area than previous Spartan families. >> >> Ed McGettigan >> -- >> Xilinx Inc. > > Ed, > > this can not be, see SYNC + 1111.... > will not even start the configuration as there is no valid pre-amble > and frame header !!!! Yes Antti, you are right. I said this in an earlier post that the current warning in the S-6 Configuration User Guide is wrong. We will fix this in the next revision. Ed McGettigan -- Xilinx Inc.Article: 141557
Brian Drummond wrote: > On Sat, 27 Jun 2009 01:56:29 -0700 (PDT), Antti <Antti.Lukats@googlemail.com> > wrote: > >> seems some V6 boards have been shipped, here >> >> http://sls.smugmug.com/gallery/5440422_Wj6jD#524855270_G47y9 > > Hmmm, there looks to be something very ... prototypish about the way that chip > is mounted to the board > > especially compared with the nice clean publicity photo... > http://www.xilinx.com/products/devkits/EK-V6-ML605-G-image.htm > > It remins me of a board I once saw, where the designer assumed a PLCC-100 in a > PGA socket had the same pinout as the PGA-100 equivalent part, and didn't > check... > > I have to wonder if that fat round cylinder hides a bundle of 1156 little wires > > ... ouch! > > are you sure "shipping" is actually an applicable word for this case? > The "smugmug" "spy" photos were taken of a ML605 board with a socket. The V-6 LX240T device in the photo is just sitting there on top of the socket. We are not selling/shipping the ML605 boards at this point, but our FAEs do have them for customer demos. The ML605 is also on the PCIe 2.0 integrator list. Ed McGettigan -- Xilinx Inc.Article: 141558
Uwe Bonnes wrote: > Antti <Antti.Lukats@googlemail.com> wrote: >> Hi :) > >> for many years Xilinx has tried to HIDE the schematics of the USB >> Cable, >> but as of today Xilinx has made it public !!! > >> really good news, no more guessing needed > >> http://www.xilinx.com/support/answers/33028.htm > >> from this page get the archieve, look in the schematics page 14 > > Let's hope this schematic is a sign of openness and not a release flaw... It is not a release flaw, but please observe the note in the upper right hand corner of the schematic. Ed McGettigan -- Xilinx Inc.Article: 141559
On Jun 27, 10:06=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > Uwe Bonnes wrote: > > Antti <Antti.Luk...@googlemail.com> wrote: > >> Hi :) > > >> for many years Xilinx has tried to HIDE the schematics of the USB > >> Cable, > >> but as of today Xilinx has made it public !!! > > >> really good news, no more guessing needed > > >>http://www.xilinx.com/support/answers/33028.htm > > >> from this page get the archieve, look in the schematics page 14 > > > Let's hope this schematic is a sign of openness and not a release flaw.= .. > > It is not a release flaw, but please observe the note in the upper right > hand corner of the schematic. > > Ed McGettigan > -- > Xilinx Inc. yes, thats fine, we have read it :) AnttiArticle: 141560
On Jun 27, 11:10=A0pm, "Antti.Luk...@googlemail.com" > ok, here some comparison > > S3-area optimize =A0 =A01447 slices > S3-speed optimize 1482 slices > S6-area optimize =A0 =A0 606 =A0slices > S6-speed optimize =A0557 =A0slices !? > > (only synthesis option changed) > > the design tested is a known 32 bit processor, > well Xilinx is defenetly enhancing the marketing-gate strategy > the SLICE count is more then ever un-comparable Any speed numbers to ut alongside those slice counts, and maybe a % of the smallest-family-member yardstick ?Article: 141561
I am using the FIFO Generator in Coregen to generate a FIFO that is 4x32k with Block Ram. I would expect that since the Virtex 5 block rams are 36 Kbit, this would take up 4 block rams, but Coregen estimates 8 block rams. This is significant since I'm designing an interleaver with 8 of the FIFOs. So I expected to use 8x4=32 (24%) not 8x8=64 (48%) of my SX50s block ram. I haven't synthesized the design yet. Is Coregen's estimate correct? Is there a restriction on the 36 Kbit ram usage that I missed? Thanks, JoeArticle: 141562
Hi, I want to expand unsigned 4*4 module to signed 16*16 module and cannot find any references. Who knows it please give me a help. Thank you. WengArticle: 141563
Weng Tianxiang wrote: > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > find any references. Post your 4*4.Article: 141564
"Mike Treseler" <mtreseler@gmail.com> wrote in message news:7akg5eF1tmmprU1@mid.individual.net... > Fredxx wrote: > >> At the same time blind reliance of simulators is just as bad. > > As is blind reliance on anything. > >> There is the old saying garbage in = garbage out. > > An rtl sim is a pretty good garbage filter. > It is only sufficient with a well-tested set of design rules. Hmm - perhaps you're interfacing with an external IC. Are you going to tell me you'd blindly write a testbench without confirming that your interface in real hardware is correctly understood? It's clear you've never got a PCI or PCIe interface working without resorting to the likes of chipscope, where reality doesn't even match signals as per standards. > >> In the past I have also come across instances where simulation has taken >> so >> long, and created such large files, that reality has been quicker with a >> few >> debugging flags in the code! > > I have worked on projects where a few debugging > flags in the code would never have found > all of the logical errors. Couldn't agree more. > > A good testbench doesn't produce large files. I was thinking of waveform files, where perhaps the simulation has to first wade though a million states to start providing data. > It reports pass or fail. You're just not living in the real world of FPGA design which ought to be a mix of simulation and reality. Anything else, and you are either assuming your test bench doesn't have any flaws, or just fumbling in the dark.Article: 141565
On Jun 27, 6:10=A0pm, Mike Treseler <mtrese...@gmail.com> wrote: > Weng Tianxiang wrote: > > I want to expand unsigned 4*4 module to signed 16*16 module and cannot > > find any references. > > Post your 4*4. Hi Mike, Here it is a Xilinx invention about 4*4 module. http://www.google.com/patents/about?id=3DaoQSAAAAEBAJ&dq=3Dpatent:6708191&a= s_drrb_ap=3Dq&as_minm_ap=3D0&as_miny_ap=3D&as_maxm_ap=3D0&as_maxy_ap=3D&as_= drrb_is=3Dq&as_minm_is=3D0&as_miny_is=3D&as_maxm_is=3D0&as_maxy_is=3D Configurable logic block with and gate for efficient multiplication in FPGAS by Xilinx Kenneth D. Chapman et al in FIG. 9, 16 and 17. WengArticle: 141566
It will depend on the configuration of the din and dout ports to how many block rams coregen will use. Have a look at the V5 libraries guide to see how a bram can be configured. JonArticle: 141567
What about the software required for the USB chip and CPLD? Is this included with ISE? JonArticle: 141568
On Jun 28, 12:59=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > What about the software required for the USB chip and CPLD? Is this > included with ISE? > > Jon yes, if you JUST replicate the hardware ISE should be able to update the CPLD well you need to preprogram the eeprom of course AnttiArticle: 141569
The FIFO(addr_cntrl_fifo_inst) has two completely irrelevant clocks, say Clock A(trn_clk_c) and Clock B(DDR2_CLK0). The frequency of Clock A is 250MHz(Period: 4ns), and Clock B is 266MHz(Period: 3.75ns). Now the problem comes when performing STA. The Timing Analyzer reports that: Slack: -10.394ns (requirement - (data path - clock path skew + uncertainty)) Source: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/Mram_RAM8_RAMC (RAM) Destination: addr_cntrl_fifo_inst/BU2/U0/grf.rf/mem/gdm.dm/dout_i_23 (FF) Requirement: 0.250ns Data Path Delay: 2.008ns (Levels of Logic =3D 0) Clock Path Skew: -8.259ns (3.005 - 11.264) Source Clock: trn_clk_c rising at 56.000ns Destination Clock: DDR2_CLK0 rising at 56.250ns For certain path crossing the different clock domains, the auto constraints turned out to be 0.25ns (4ns =96 3.75ns). This is impossible to achieve. What should I do to pass the STA?Article: 141570
On Jun 27, 3:39=A0pm, Sudhir Singh <Sudhir.Si...@email.com> wrote: > Hi Folks, > I am currently in the process for selecting an FPGA for one of my > projects. I have always used Xilinx FPGAs but now am considering using > Altera. The Altera Cyclone III FPGAs looks like a very cost effective > device but I have no idea how well it compares performance wise (will > be used for DSP application) to a Spartan3E. > I would be very grateful if someone would be able to provide me few > pros and cons of Cyclone III. > > Thanks > Sudhir it is matter of taste and preferences but if you compara S3E and C-III i see no reasons not to prefer C-III but as said its a question of taste, or possible corporate policy I would recommend C-III over S3E but my most argument is SPI multiboot capability C-III has it, S3E doesnt of course the amount of BRAM too smallest device CIII has 46 compared to 8K in S3E AnttiArticle: 141571
hi, im plannining to buy a vertex 2 based FPGA board. this is the link. http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,453&Prod=XUPV2P does this board worthy for the price of $299? CMOSArticle: 141572
On Jun 28, 3:42=A0pm, CMOS <manusha1...@gmail.com> wrote: > hi, > im plannining to buy a vertex 2 based FPGA board. this is the link. > > http://www.digilentinc.com/Products/Detail.cfm?NavPath=3D2,400,453&Prod..= . > > does this board worthy for the price of $299? > > CMOS absolutly, if you get it for $299! too bad Xilinx is no longer supporting Virtex-II with their ISE ISE 10.1 is the last version that offered V-II support, AnttiArticle: 141573
Fredxx wrote:
> Hmm - perhaps you're interfacing with an external IC. Are you going to tell
> me you'd blindly write a testbench without confirming that your interface in
> real hardware is correctly understood?
Standard interfaces are well documented.
Certainly I have to verify a few things on the bench,
but starting with a sim improves my odds.
> It's clear you've never got a PCI or PCIe interface working without
> resorting to the likes of chipscope, where reality doesn't even match
> signals as per standards.
We purchased a PCIe core that came with a testbench.
I just worked.
-- Mike Treseler
Article: 141574Mike Treseler wrote: > We purchased a PCIe core that came with a testbench. > I just worked. It
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z