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On Wed, 29 Jul 2009 10:25:49 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: >On Jul 28, 6:55 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Tue, 28 Jul 2009 15:12:35 -0700, "Joel Koltner" >> >> >> >> <zapwireDASHgro...@yahoo.com> wrote: >> >>http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif >> >> >Interesting, indeed. >> >> >Cypress had viable products but I'm convinced that management was the problem. >> >(I also remember they wanted a rather large premium for their CPLDs that were >> >sometimes only marginally better than the competition's.) >> >> >I don't know what Vantis's problem was, but at least after Lattive bought them >> >they kept a few of the parts around. >> >> >Intel doesn't have its heart in much of anything but their desktop CPUs -- >> >they consistently bring out interesting products and then discontinue them >> >just when they're starting to gain traction. >> >> >You're pretty much a pure Xilinx man these days, aren't you, John? >> >> Yes, although I occasionally use a 22V10 for glue logic and such. >> We've used MMI, Gould/AMI, Actel, TI, and Lattice in the past. >> >> We've been meaning to start using some CoolRunner type CPLDs for >> various things, but no compelling application has come up. >> >> Where the hell are the Spartan 6's? Nobody will tell me when we can >> get some. Sales reps fall off the face of the Earth when you ask that >> question. The best I can get is "available for purchase in September" >> and nobody knows what that means. > >So what else is new about Xilinx??? Same old, same old... > >I don't get all worked up about the latest and greatest tech in FPGA >chips. I am much more concerned with availability and price than I am >getting the smallest geometry or the most developed technology. So >much of that stuff is actually in the noise when building a product. >I care how well my vehicle moves, the MPG and how often it goes in the >shop. Why should I care how many cylinders, how many valves or even >if it is electric? > >With FPGAs, I care about if I can actually get them, will my design >fit (along with any future expansion allowance) and how much it costs, >optionally with what packaging if that matters in a given design. The >rest is in the noise including, for the top three, the tool set. Turns out the there *are* some engineering-sample S6's available, and it looks like we may get a few, so we can design them into a couple of new projects. Sadly, we are on the FPGA-addiction bandwagon. Every new gen of speed and goodies lets us pump up the performance of a product, or write an even-more-ludicrous proposal. In the current case, the S6/45 has two hard DRAM controllers, megabits of block ram, and 58 DSP slices, most of which resources we intend to gobble up. I can ask my FPGA guy for the most insane signal processing, and in a few hours it's done. JohnArticle: 142251
@Frank: > 7 24-bit counters would easily fit in registers in many FPGAs (e.g. > std_logic_vector signals in VHDL). You don't need any RAM at all, even no > internal block RAM. This makes the implementation much easier than using > external DDR SDRAM, if you are using VHDL and not some embedded system, > like NIOS or MicroBlaze. The thing is is that I need to readout the value of the counter every (say) microsecond or less, which is why I figured I would need a RAM buffer, the idea being I would fill the ram with the counter values then read it all out to the computer in one flash, then we restart the process with (ideally) as little dead time in between "runs". > I assume you are using some synthesized CPU? In NIOS it is possible to > include your own VHDL entities. They are compiled together with the rest of > the system to a netlist, which then can be loaded into the FPGA. I was planning on using the Microblaze synthesized CPU, which I understand is the Xilinx provided system. > Of course, would be much more fun to implement your own RS232 entity and > protocol, all in pure VHDL :-) The more I think about it, the more I think that doing something like this will be the way to go. I'm not died down to any one method yet, so changing tracks wouldn't be any trouble. @rickman: > What's wrong with using the PC to implement the web server? A web > server is a complex device when viewed from the gate level which is > typically several layers down from the level of web software. If you > intend to include an embedded processor in the FPGA, then you can run > any software you want. Mike explained that VHDL is not the sort of > software you would want to use to run a web application. The HDL > stands for "Hardware Description Language". Nowhere in there does it > indicate that it would be useful or remotely easy to implement a web > server. I figured I would use the web server on the FPGA board as my method of reading out the data (i.e. have the computer download some file from the webserver that contains the measurements taken. > The counters are perfect for an FPGA design. The idea of loading the > counts into a DDR ram and accessing them is now outside of the FPGA > and at the board level. Is there a reason not to use the internal > memory in the FPGA? Will this be running in batch mode where you run > the measurement for a while, stop and read out the results; or will > you be reading the results in real time as the measurement is being > made? If the latter, your comms has to keep up with the average rate > of the measurement and the ram is only a buffer to smooth out the > measurement data rate. Ideally I want to be reading the results in real time as the sources I'm triggering off of are expected to have extremely short durations (because pausing half a millisecond to break and read out the data could cause us to miss an event). Thus, the memory buffer would be put there so that we would never have to stop taking data and have the PC perpetually reading the DDR memory (containing the values of the counters after specific time intervals).This is, of course, assuming that the mean PC read rate is faster than the FPGA write rate. This does, however, raise the question of if this is the case, why not readout the counter values directly to the PC every microsecond (or so) as suggested by Frank? I'm assuming that there's a limit on how many times per second a computer can access (say) an Ethernet or serial jack (i.e if I can only look at my computer's serial port once per millisecond (example) I could not sample the counter values often enough, regardless of how fast it can then read data out) which is what inspired the idea of having a memory buffer. This last bit though, is much more speculative. Perhaps some tests are in order. -Sean.Article: 142252
On Jul 28, 3:00=A0pm, JimLewis <J...@SynthWorks.com> wrote: > > On the other hand, this particular item is something that I submitted > > to the VHDL standards group a few years back and was accepted at that > > time as a 'good' idea...maybe it made it into VHDL '08...if not theirs > > always VHDL 201x. > > Kevin, > Do you have a bug ID for it? =A0I was looking through the bugzilla > database and could not find it. > > Jim Jim, No I don't have a bug ID. I also haven't been able to locate anything specific but I'm pretty darn sure I went through the eda-stds.org link (http://www.eda-stds.org/vasg/#Enhancements) to submit the request. Based on other bits and pieces, I believe the request was submitted in 2005. Should another one be submitted to cover this case? FYI, as I mentioned back in 2005, the place where I think opens in port maps are most handy is when the VHDL code is generated by a CAD system and represent a PCBA netlist. When designing a board, it certainly is the case where you can legally have unconnected pins and those pins might happen to be bits of some 'bus' of related pins. Back in 2005, I had a device which happened to have a 24 bit data bus of which I was only using 16 bits and the part had no requirement to drive unused pins on that bus. On a side note, I also submitted a request for a totally different feature back in June 2008. On that one I got a reply back that said it had been assigned number 2132. The Bugzilla.mentor.com site says that bug #2132 does not exist so I have no idea what number that request have been refiled under or if that request has been lost or reached some other disposition. If you need any more info, I can forward you what I have on that one. Kevin JenningsArticle: 142253
Griffin wrote: > The thing is is that I need to readout the value of the counter every > (say) microsecond or less, which is why I figured I would need a RAM > buffer, the idea being I would fill the ram with the counter values > then read it all out to the computer in one flash, then we restart the > process with (ideally) as little dead time in between "runs". First you should think about your problem in more detail, like how fast your counters can be triggered, how fast you need to read it and for which time, all with hard numbers. Then you can plan better what you need. From the FPGA you can send RS232 data without dead time. Maximum standard speed usable with all modern PCs or USB adapters is 115200 baud. One stop bit and one start bit means you can transfer 11520 bytes per second. Some PCs provides higher baudrates. The PC has a FIFO, so no byte get lost. If your timing base on the FPGA side is good, you don't need a timestamp, because you can calculate it from the byte position in the received stream. You can implement a full duplex RS232 entity, then you can reset the counters from the PC. The whole concept should be really simple to implement. > I was planning on using the Microblaze synthesized CPU, which I > understand is the Xilinx provided system. If you need ethernet for the speed, this would be a good idea, because developing it on your own, or even trying to use some ethernet core from OpenCores, is not a good idea for a beginner. Caching in external RAM and transfering with RS232 would be easier with a CPU, too. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 142254
Hi all ,
This is Pradeep.
I am having now 4+ years of IT experience in Embedded and telecom
domain. (currently working in Verizon India,Hyderabad).
I would like to work on AI , please let me if you have any research
work related AI needs to work on. i am eagerly waiting for.
Please let me know if you have any so that i can start work on.
Please find the below curriculum vitae of mine.
Please suggest me in this regard,
please do reply...
--
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CURRICULUM VITAE
Pradeep Sanchana
E-mail: pradeep.sanchana@gmail.com
Objective:
My long-term goal is to be actively involved with research and
teaching in an area that I love. I look forward to such an involvement
in one of the aforementioned areas would be the crucial first step
towards this goal.
My research interests lie in the field of Artificial intelligence in
Computer Science. More specifically, I am interested in Human-Computer
Interaction as well as their applications. Other areas that interest
me are AI/Machine Learning and Fuzzy logic and interactive
visualization.
Experience summary:
Having 4+ years of experience in embedded systems and Telecom of IT
industry.
Organizational experience:
Sep 2007 =E2=80=93Till Date Working as Analyst in Embedded.
Verizon Data Services Pvt Ltd,Hyderabad.
Sep2005- Sep 2007 Worked as Sr. Software Engg in Embedded Tools
Development in KPIT Cummins Info Sys Ltd, Pune.
Mar2005=E2=80=93Aug 2005 Worked as a Trainee with Galieo Soft Pvt Ltd,
Bangalore.
Education:
Education Board/University Aggregate Year of passing
B.Tech(Electonics&Computers) JNTU, Hyderabad 65% 2004 (April)
Intermediate Board of Intermediate A.P 69.6% 2000
SSC Board of Secondary Education 72.87% 1998
Courses Undertaken
June 2004- Feb2005 Embedded Systems, Karvin Software Solutions,
Bangalore
Technical Skills:
Embedded Systems : Linux Internals, Renesas, ARM, Debuggers, GCC,
GDB
Programming Language : C, C++, Perl, Shell scripts, Assembly,
Makefile
Operating Systems : Linux, Windows, MS-DOS
Key Projects Undertaken:
Project#1 : INMP
Software : Solaris, CC
Duration : Sep 2007-Till date
Team size : Three
Company : Verizon Data Service India Pvt ltd, Hyderabad
Client : Verizon,US
Description
International Mediation Process Based on the Business rules this
process the Mdiation process of the call records. Whether to bill the
record or suspend the record or drop the record based on the criteria
and sent the billing records to specific down stream system.
Role:
=E2=80=A2 Solved in problem analyzing and writing some Business rules.
Project#2 : Interoperability between GNU-SH and Renesas-SH Compilers
Software : Linux, GCC
Duration : Jun 2006-Sep 2007
Team size : Three
Company : KPIT Cummins Infosystems Limited, Pune
Client : Renesas Technologies, Europe
Description
The ability of two or more components communicates properly, created
by different compilers to exchange information. Due to some mismatch
in the ABI difference in Renesas SHC and GNUSH we developed patch
ensures that arguments of data type =E2=80=98long long=E2=80=99 are passed =
on stack
for all SH targets thus following Renesas SHC ABI. Generation of
correct relocatable information with addend fields for linking GNUSH
relocatable with Renesas linker. Patch was developed for the same. The
complete interoperability was tested successfully for all library
functions, Hmon -7145, MPEGsim Workspace.
Role:
=E2=80=A2 Solved for problems in HMON-7145 with root cause analysis.
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Project#3 : Cross Toolchain Building, based on GNU
Software : Linux , GCC
Duration : Nov 2005-May 2006
Team : Three
Company : KPIT Cummins Infosystems Limited, Pune
Client : Renesas Technologies, Europe
Description
Building cross toolchain for Renesas targets (i.e SH ,H8300,M16C )
with latest GNU sources. Cross tools building for both Windows and
Linux platforms by applying latest patches to the sources. Building
simulator and GDB for the Renesas targets. And testing the toolchain
using DEJAGNU test suite. Written shell script for the same.
Role:
=E2=80=A2 I have done the Binary unification for little and big endian
toolcains based on GLIBC.
=E2=80=A2 I have received an appreciation award for successful completion o=
f
=E2=80=98Sh-linux=E2=80=99 project.
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Project#4 : Galieo Developer suite (Variables)
Software : Linux ,C
Duration : May 2005-Aug 2005
Team : Three
Company : Galieo Soft, Bangalore
Client : Galieo Soft
Description
Galieo Developer Suite is an embedded software developer
tool used for embedded developers using ARM architecture. This project
is used in Galieo developer suite for displaying total variables and
corresponding values in a function during debugging. We are taking
=E2=80=98.gxf=E2=80=99(Galieo Executable File rename of ELF) as an input fi=
le and
collecting the information needed for the variables and that
information is stored in separate file in specific format ,i.e.,
global variables of that function followed by variables and offset
values. While debugging select a function that will display variables
under that function and corresponding values in the function.
Role:
=E2=80=A2 Implemented function for collecting information needed from
the .gxf and by calculating the offset of the variable to store in
that file.
=E2=80=A2 Implemented functions to convert float and double values by takin=
g
binary as input.
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Academic Project:
Project Title : Image Restoration & Processing Techniques
Software : C++, DOS Platform
Duration : Dec 2003-Mar 2004
Team : Five
Description
This project used in many applications like satellite imaging,
astronomical imaging, poor quality portraits the imaging system
introduces a slight distortion. Often images are slightly blurred and
image restoration aims at the image. It is an attempt to reconstruct
an image that has been degraded by priori and posteriori knowledge of
degradation phenomena. It also deals with image processing techniques
like filtering for noise removal. And image compression to save
storage space as well as to save time for transmission. For this we
had gone through Fourier transforms.
Role:
=E2=80=A2 My contribution was in developing Image compression Module
Designing and developing.
=E2=80=A2 Implemented Run length encoding, Huffman coding.
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Research Papers/ Publications
=EF=83=98 National Symposium, 2004 : Digital Image Restoration
This paper got selected in National Symposium 2004 conducted by
Narayana Engineering College. Won 2nd Place.
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Extracurricular activities
I enjoy playing Violin and singing.
PERSONAL Details:
Languages known : English, Hindi, Telugu
Nationality : Indian
Sex : Male
Date of Birth : 25-Aug-1983
Martial status : Unmarried
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Thanks & Regards,
Pradeep Sanchana
Article: 142255On Jul 30, 9:31=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > On Jul 28, 3:00=A0pm, JimLewis <J...@SynthWorks.com> wrote: > > > > On the other hand, this particular item is something that I submitted > > > to the VHDL standards group a few years back and was accepted at that > > > time as a 'good' idea...maybe it made it into VHDL '08...if not their= s > > > always VHDL 201x. > > > Kevin, > > Do you have a bug ID for it? =A0I was looking through the bugzilla > > database and could not find it. > > > Jim > > Jim, > > No I don't have a bug ID. =A0I also haven't been able to locate anything > specific but I'm pretty darn sure I went through the eda-stds.org link > (http://www.eda-stds.org/vasg/#Enhancements) to submit the request. > Based on other bits and pieces, I believe the request was submitted in > 2005. > > Should another one be submitted to cover this case? =A0FYI, as I > mentioned back in 2005, the place where I think opens in port maps are > most handy is when the VHDL code is generated by a CAD system and > represent a PCBA netlist. =A0When designing a board, it certainly is the > case where you can legally have unconnected pins and those pins might > happen to be bits of some 'bus' of related pins. =A0Back in 2005, I had > a device which happened to have a 24 bit data bus of which I was only > using 16 bits and the part had no requirement to drive unused pins on > that bus. > > On a side note, I also submitted a request for a totally different > feature back in June 2008. =A0On that one I got a reply back that said > it had been assigned number 2132. =A0The Bugzilla.mentor.com site says > that bug #2132 does not exist so I have no idea what number that > request have been refiled under or if that request has been lost or > reached some other disposition. =A0If you need any more info, I can > forward you what I have on that one. > > Kevin Jennings Hi KJ, I think you are not only right on the output pins, but also right on the input pins. When a module is shared by several upper modules, there is a possibility that each upper module may have specific input pins other upper modules don't share, and when each upper module calls this module, they can leave unused input signals in OPEN state. When VHDL compiler meets input signals with open connection, reports an fatal error. This way more upper modules can share a based module with different number of input signals. Currently I have to supply DUMMY inputs which are ineffective in production, and non-productive in coding. When an input signal is connected to "OPEN', it means this input is never used in this module, and if used, it is a fatal error. It is a much clearer and clever idea to permit to use "OPEN" for input signals to a module too. WengArticle: 142256
The latest version of Xcell Journal in Ceros ebook (flash) format: http://cde.cerosmedia.com/1R4a5b56ace53ae012.cdeArticle: 142257
Maybe a constraints file missing... /Mikhail "Roger" <rogerwilson@hotmail.com> wrote in message news:DcOdnZz3NYz1x_LXnZ2dnUVZ8gWdnZ2d@brightview.co.uk... > Can anyone tell me what the following error messages mean please? > > ERROR:ProjectMgmt:357 - Problem updating Cs using the Transform Instance. > ERROR:ConstraintSystem:170 - No constraint database file was specified. > > Thanks, > > RogArticle: 142258
Mike Santarini wrote: > The latest version of Xcell Journal in Ceros ebook (flash) format: > http://cde.cerosmedia.com/1R4a5b56ace53ae012.cde why is it not simply in plain dumb google-able HTML or even PDF ?? Google does not index Flash, so it's a marketing failure. or a trap. -- http://ygdes.com / http://yasep.orgArticle: 142259
On Jul 17, 4:37=A0am, Alan Fitch <alan.fi...@spamtrap.com> wrote: > rickman wrote: > > <snip> > > > > > > > =A0 Mul: multiply > > =A0 =A0PORT MAP ( > > =A0 =A0 =A0SysClk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> SysClk, =A0-- Sys= tem clock, 12.288 MHz? > > =A0 =A0 =A0Start =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =3D> Start, =A0 =A0-- = Load multiplican and init result > > =A0 =A0 =A0Multiplicand =A0=3D> LinDat, > > =A0 =A0 =A0Multiplier =A0 =A0=3D> std_logic_vector(AudioGain), > > =A0 =A0 =A0Product(ProdHigh downto ProdHigh - MulOut'high) =A0 =A0 =A0 = =3D> MulOut, > > =A0 =A0 =A0Product(ProdHigh - MulOut'high - 1 downto 0) =A0=3D> OPEN, > > =A0 =A0 =A0Done =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=3D> Done > > =A0 =A0); > > > According to Ben Cohen book, the product can not be split this way > > using OPEN. =A0When I tried it with Synplicity it seems to accept this > > syntax. =A0Ben's book is a bit older and refers to the '93 standard. = =A0I > > believe there is a newer VHDL standard, 200x. =A0Is this something that > > has changed since '93 or is the Synplicity tool just being > > magnanimous? =A0Should I change it so that it will work with other tool= s > > or do most tools accept this? > > > Rick > > Hi Rick, > =A0 =A0it was legal to do that (split an array up on the left of the > association and leave parts of it open) in VHDL 87. It was made illegal > in VHDL 93, i.e either the whole array may be left unconnected, or every > element of the array must be associated, > > regards > Alan Hi Alan, I still have not had a chance (read that as "remembered") to look this up in Ben's book. But I am surprised that it would have been legal in '87 and made illegal in the '93 standard, unless there was some reason for it. Is there any complication to the tools that allowing this use of OPEN would create? I am not really familiar with the innards of how the tools work, but I believe things like the widths of busses are defined in an initial "compile" and then the modules are used in the "elaborate" phase. It might be an issue where a given module needs to be compiled once and then used in many places. I think the use of OPEN would cause the associated inputs and outputs to be dropped which can eliminate logic. Clearly you can't use a common module if different uses have different logic. Is that why using OPEN in this way was made illegal? RickArticle: 142260
Peter Alfke wrote:
>
> It is difficult to build reliable high-performance systems, if they
> are driven from an unreliable clock source.
>
It is difficult to design high-reliability systems, if the
vendor "ROM" primitives self destruct upon loss of clock.
If you are not going to fix the corruption problem, you should
at the very least provide a method of reloading the Block ROM
contents that is easier than {partial} reconfiguration.
The runtime Configuration port (CDI,CLK,CE) of the nifty
CFGLUT5 in the Virtex5's would be a good model for this.
Brian
Article: 142261Jim G. wrote: > > So you have a Phantom-Write pathway, that is essentially a make-before- > break analog switch ? > I am also surprised the Memory cell itself can drive to/from a read- > bus, usually those are orders of magnitude different loads ? > Aside: Every async SRAM I've ever used supported a CE permanently active mode of operation with a Taa specified from the last address transition; as glen h. pointed out earlier, these multiple address line transitions internally should create the same conditions for bit-line contention as in the problematic Block ROMz. From my own observations of BRAM/BROM corruption, and the notes posted by Allan H., I suspect there are actually two issues with the Xilinx BRAM address decoders: 1) address setup violation 2) runt clock pulses The multi-cycle address float read corruption I've seen in years past behaved like a metastable event, with low frequency, when I first observed it on a continuous data streaming application ( IIRC a flipped bit every hour or two with audio rate data ). The DCM clock startup corruption seemed much more frequent than this, so I suspect the BRAM address decoders can't handle whatever crud appears on the BRAM clock input ( short pulses, ??? ) when a DCM is in the throes of locking/unlocking. BrianArticle: 142262
> Mike Santarini wrote:
>> The latest version of Xcell Journal in Ceros ebook (flash) format:
>> http://cde.cerosmedia.com/1R4a5b56ace53ae012.cde
whygee wrote:
> why is it not simply in plain dumb google-able HTML or even PDF ??
Try clicking the pdf button at the top.
> Google does not index Flash, so it's a marketing failure. or a trap.
It didn't trap me, and it's not a data sheet.
And what's so great about having google tie the servers?
Anyway, it feels more like reading a real magazine.
-- Mike Treseler
Article: 142263Ben wrote: > > Actually, I was thinking of configuring multiple FPGAs from one SPI > flash, but I don't see any examples in the Spartan6 configuration > document. > I can't help with Spartan 6, but I've done this with Virtex 5. Some loss of hair was required to make this work, see Dec 2008 comp.arch.fpga thread "V5 JTAG download weirdness" http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/2a291d5c38a= bbd3c - mode jumper to easily change the mode pins from SPI to JTAG - the use of cascaded done requires first preloading a dummy bitstream via JTAG to each FPGA before downloading the Impact SPI flash programming core - JTAG FPGA download didn't work for me unless double clutching the downloads: last slave -> ... -> first slave -> master -> first slave ... last slave ------------------- Xilinx Virtex5 SPI serial flash connections are shown here: XAPP951 v1.2 Configuring Xilinx FPGAs with SPI Serial Flash http://www.xilinx.com/support/documentation/application_notes/xapp974.pdf figure 2, page 4 caution: no mention in Figure 2 of the need for a mode pin jumper!!! ------------------- The V5 SPI master->slave cascade is mentioned, but not directly pictured, here: UG191 v3.7 Virtex-5 FPGA Configuration User Guide http://www.xilinx.com/support/documentation/user_guides/ug191.pdf Page 68: " " SPI Serial Daisy Chain " " In a serial daisy chain application, the leading device can be " in SPI mode and all downstream devices in Slave Serial mode. " In this case, all configuration bitstreams can be stored inside " one SPI device. The bitstream format for master and slave serial " daisy chains is exactly the same. See =93Serial Daisy Chains=94 for " details. " ------------------- Although nominally about parallel configuration, the following V5 application note is a bit newer, and mentions the problems with mode selection ( note 5, figure 2, page 5) and the Impact issues with cascaded done ( "Caution!" on page 25 ) : XAPP973 v1.3 Indirect Programming of BPI PROMs with Virtex-5 FPGAs http://www.xilinx.com/support/documentation/application_notes/xapp973.pdf have fun, BrianArticle: 142264
On Jul 30, 4:09=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote: > On Jul 30, 9:31=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > Hi KJ, > I think you are not only right on the output pins, but also right on > the input pins. > I was talking about inputs, outputs and inouts. > When a module is shared by several upper modules, there is a > possibility that each upper module may have specific input pins other > upper modules don't share, and when each upper module calls this > module, they can leave unused input signals in OPEN state. When VHDL > compiler meets input signals with open connection, reports an fatal > error. > Input pins in a module that are not part of a bus and that are not used in certain applications simply need to have an initializer applied to them. xyz: in std_ulogic :=3D '0'; If the user then does not connect up anything to 'xyz' it will be treated as a '0' since that's what the initializer sets it to...no errors. The problem comes in when 'xyz' is a *vector* and not all of the bits in the vector are used in certain applications. > This way more upper modules can share a based module with different > number of input signals. Currently I have to supply DUMMY inputs which > are ineffective in production, and non-productive in coding. > <snip> > It is a much clearer and clever idea to permit to use "OPEN" for input > signals to a module too. > If you're talking about scalars and not vectors, then look into using initializers on the input pins instead. KJArticle: 142265
rickman wrote: > On Jul 17, 4:37 am, Alan Fitch <alan.fi...@spamtrap.com> wrote: >> rickman wrote: >> >> <snip> >> >> >> >> >> >>> Mul: multiply >>> PORT MAP ( >>> SysClk => SysClk, -- System clock, 12.288 MHz? >>> Start => Start, -- Load multiplican and init result >>> Multiplicand => LinDat, >>> Multiplier => std_logic_vector(AudioGain), >>> Product(ProdHigh downto ProdHigh - MulOut'high) => MulOut, >>> Product(ProdHigh - MulOut'high - 1 downto 0) => OPEN, >>> Done => Done >>> ); >>> According to Ben Cohen book, the product can not be split this way >>> using OPEN. When I tried it with Synplicity it seems to accept this >>> syntax. Ben's book is a bit older and refers to the '93 standard. I >>> believe there is a newer VHDL standard, 200x. Is this something that >>> has changed since '93 or is the Synplicity tool just being >>> magnanimous? Should I change it so that it will work with other tools >>> or do most tools accept this? >>> Rick >> Hi Rick, >> it was legal to do that (split an array up on the left of the >> association and leave parts of it open) in VHDL 87. It was made illegal >> in VHDL 93, i.e either the whole array may be left unconnected, or every >> element of the array must be associated, >> >> regards >> Alan > > Hi Alan, > > I still have not had a chance (read that as "remembered") to look this > up in Ben's book. But I am surprised that it would have been legal in > '87 and made illegal in the '93 standard, unless there was some reason > for it. Is there any complication to the tools that allowing this use > of OPEN would create? I am not really familiar with the innards of > how the tools work, but I believe things like the widths of busses are > defined in an initial "compile" and then the modules are used in the > "elaborate" phase. It might be an issue where a given module needs to > be compiled once and then used in many places. I think the use of > OPEN would cause the associated inputs and outputs to be dropped which > can eliminate logic. Clearly you can't use a common module if > different uses have different logic. > > Is that why using OPEN in this way was made illegal? > > Rick Hi Rick, I don't know why it changed. The key phrase is at the end of section 1.1.1.2 in the VHDL93 standard "It is an error if some of the subelements of a composite formal port are connected and others are either unconnected or unassociated." I don't think it's to do with compilation and elaboration - you can leave all elements of a composite port disconnected or not in different parts of the design, it's just you can't leave some of them disconnected and others not. I had a quick look at the issue reports here: http://www.vhdl.org/isac/IRs-VHDL-87/ but couldn't find the explanation for the change, regards Alan -- Alan Fitch Senior Consultant Doulos – Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: alan.fitch@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com ------------------------------------------------------------------------ This message may contain personal views which are not the views of Doulos, unless specifically stated.Article: 142266
Hi Mike, in case your problem is still an issue... I am just writing up a product spec for a customer and your issue came to mind: Do you have XRES connect to ground through a 10 KOhm resistor? There is a description to this pin on page 2-32 (and a few other distributed places) in the current EC/ECP handbook. Regards, CharlesArticle: 142267
hi i am new to fpga and i am using system generator for dsp for vhdl code generation but during synthesizing i got following error can anyone help me ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/d ds_v5_0/comp0.core_instance0/hset, RLOC=X8Y1) which require the combination of the following symbols into a single SLICE component: FLOP symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU331" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N1146) FLOP symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU333" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N1152) LUT symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU531" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2627) MULTAND symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU532" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2629) MUXCY symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU533" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2630) XORCY symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU534" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2464) LUT symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU526" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2622) MULTAND symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU527" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2624) MUXCY symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU528" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2625) XORCY symbol "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co mp0.core_instance0/BU529" (Output Signal = Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N2463) Unable to pack register Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/BU333 because of connectivity restrictions. The register failed to be packed in FFX for the following reasons: The signal Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/N1146 can not use the BX pin because of other resources in the slice. The register Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/BU333 is unable to use the F LUT as a route through. The register failed to be packed in FFY for the following reasons: The register Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com p0.core_instance0/BU331 already occupies FFY. Please correct the design constraints accordingly.Article: 142268
My first question is: is it possible to make conversion from JAVA language to C/C++ language ? I'm using starter kit spartan-3e Ethernet and I have written a program in JAVA language in order to send a BitMap file to a memory built into the fpga. I used UDP protocol and it's working very well ! So my second question is: Can anyone help me to do the same work but using C++ builder6 or translate my JAVA source to a c++ builder source (of course using UDP protocol)? Thank you.Article: 142269
>On Jun 28, 12:59=A0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: >> What about the software required for the USB chip and CPLD? Is this >> included with ISE? >> >> Jon > >yes, if you JUST replicate the hardware >ISE should be able to update the CPLD >well you need to preprogram the eeprom of course > >Antti > The content of EEPROM can be read by a simple IC programmer, but there's two problem2,first, how ISE update the CPLD? When conncet cable to host? Or I need to programm the CPLD in ISE? Second, the Cypress USB controller need programmed or not?Article: 142270
Couldn't you use an unconstrained vector port? Of course whatever bits you do want to hook up must be contiguous. And it does not help with record types. And if you did allow open portions of vectored port associations (in some past/future version) would that work with unconstrained ports? Maybe that's where it ran afoul in the first place. AndyArticle: 142271
On Jul 30, 1:44=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Griffin wrote: > > The thing is is that I need to readout the value of the counter every > > (say) microsecond or less, which is why I figured I would need a RAM > > buffer, the idea being I would fill the ram with the counter values > > then read it all out to the computer in one flash, then we restart the > > process with (ideally) as little dead time in between "runs". > > First you should think about your problem in more detail, like how fast > your counters can be triggered, how fast you need to read it and for whic= h > time, all with hard numbers. Then you can plan better what you need. > Will do. > > I was planning on using the Microblaze synthesized CPU, which I > > understand is the Xilinx provided system. > > If you needethernetfor the speed, this would be a good idea, because > developing it on your own, or even trying to use some ethernet core from > OpenCores, is not a good idea for a beginner. Caching in external RAM and > transfering with RS232 would be easier with a CPU, too. > Your help is very much appreciated. The trick here is is that I'm not sure how to implement and actually use IPs with a synthesized CPU, which is what I must look into I guess. Essentially, I understand the project build process until one gets to the Xilinx SDK. The way I understand it, the SDK allows one to apply C and C++ code to an FPGA project. Can anyone point me in the right direction for use of the SDK to implement IPs such as memory interfaces and ethernet controllers (i.e. a good reference document, a working example of something doing one of these things, etc.) Thanks in advance! SeanArticle: 142272
On Jul 31, 3:48=A0pm, "markman" <mark...@163.com> wrote: > >On Jun 28, 12:59=3DA0pm, "maxascent" <maxasc...@yahoo.co.uk> wrote: > >> What about the software required for the USB chip and CPLD? Is this > >> included with ISE? > > >> Jon > > >yes, if you JUST replicate the hardware > >ISE should be able to update the CPLD > >well you need to preprogram the eeprom of course > > >Antti > > The content of EEPROM can be read by a simple IC programmer, but there's > two problem2,first, how ISE update the CPLD? When conncet cable to host? > Or I need to programm the CPLD in ISE? > =A0Second, the Cypress USB controller need programmed or not? just program the eeprom ISE does the rest :) some german guys have tested it already.. AnttiArticle: 142273
Looks like you have conflcting location constraints. Try unchecking Use RLOC Constraints in Map properties. This is not a good solution in the long run though (unless the design is not very demanding), because it might affect resulting performance and routability. Ultimately, you need to understand why you ended up with conflicting constraints and either change something in the core generation process or to edit them manually. /Mikhail "omair50" <omair_sarwar50@yahoo.com> wrote in message news:B-OdnQ0RV-2Zde_XnZ2dnUVZ_hednZ2d@giganews.com... > hi i am new to fpga and i am using system generator for dsp for vhdl code > generation but during synthesizing i got following error can anyone help > me > > ERROR:Pack:679 - Unable to obey design constraints > > (MACRONAME=Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/d > ds_v5_0/comp0.core_instance0/hset, RLOC=X8Y1) which require the > combination > of the following symbols into a single SLICE component: > FLOP symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU331" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N1146) > FLOP symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU333" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N1152) > LUT symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU531" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2627) > MULTAND symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU532" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2629) > MUXCY symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU533" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2630) > XORCY symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU534" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2464) > LUT symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU526" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2622) > MULTAND symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU527" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2624) > MUXCY symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU528" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2625) > XORCY symbol > > "Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/co > mp0.core_instance0/BU529" (Output Signal = > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N2463) > Unable to pack register > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/BU333 because of connectivity restrictions. The > register > failed to be packed in FFX for the following reasons: The signal > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/N1146 can not use the BX pin because of other > resources in > the slice. The register > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/BU333 is unable to use the F LUT as a route through. > The > register failed to be packed in FFY for the following reasons: The > register > > Top_l/CustomLogic_l/u_sysgen_wrapper/U_sysgen/sysgen_dut/fpga_x0/dds_v5_0/com > p0.core_instance0/BU331 already occupies FFY. Please correct the > design > constraints accordingly. > >Article: 142274
On Jul 31, 11:42=A0am, Andy <jonesa...@comcast.net> wrote: > Couldn't you use an unconstrained vector port? Not when you don't have control of the design that you're interfacing with that you also don't happen to want to connect up all the I/O to. The specific example that I gave earlier in the thread is... "When designing a board, it certainly is the case where you can legally have unconnected pins and those pins might happen to be bits of some 'bus' of related pins. Back in 2005, I had a device which happened to have a 24 bit data bus of which I was only using 16 bits and the part had no requirement to drive unused pins on that bus." Since the VHDL file for the netlist for the PCBA is written by the schematic capture ECAD tool, I don't have direct control of that VHDL file other than to modify something on the schematic for the board. One work around would be to make one pin nets for each of the pins that are 'unused'. Now the ECAD tool will write out a netlist with everything attached...the downside here is that when doing board design, 'one pin nets' are usually a form of design error. Intentionally adding noise to this check by creating one pin nets just to satisfy a simulation tool is counter-productive. There are other work arounds, with their own particular disadvantages as well. One could also be further removed from the PCBA design in that maybe you don't have design control of the PCBA, you're simply the recipient of the design in which case the work around is manual edits to the VHDL netlist for the board. > And it does not help with record types. > Record types don't need any help, they can be defaulted by the usual method of supplying an initializer on the entity. The problem is with vectors (of any type). > And if you did allow open portions of vectored port associations (in > some past/future version) would that work with unconstrained ports? > Maybe that's where it ran afoul in the first place. > Maybe...but in the process of making this change they created a situation where a common hardware design situation (i.e. unconnected pins on a chip) can not be modelled. Sometimes some may forget that the 'H' in VHDL stands for hardware. Kevin Jennings
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