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Messages from 142175

Article: 142175
Subject: Re: Daisychaining fpga with SPI flash?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Tue, 28 Jul 2009 08:33:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
> I've read about daisy chaining fpgas with Platform flash, but is daisy
> chaining fpgas possible with SPI flash?
> The documents at Xilinx seems to give only examples of single fpga
> configuration with SPI flash.

no, you cant use multiply SPI flash in chained mode
(you may configure more than one FPGA from one SPI flash)

well, some newer FPGA's include multi SPI support,

* Spartan-6
* Lattice-SC
* Achronix Speedster

all support multiply SPI flash in __parallel__ wiring
(maybe some others too, i do not know all )

Antti

Article: 142176
Subject: Re: Lattice EC - some .bit files not loading from SPI flash
From: gabor <gabor@alacron.com>
Date: Tue, 28 Jul 2009 08:46:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 5:42=A0am, Mike Harrison <m...@whitewing.co.uk> wrote:
> On Tue, 28 Jul 2009 10:50:48 +0200, Charles Gardiner <inva...@invalid.inv=
alid> wrote:
> >Hi Mike,
>
> >at what frequency is your SPI running. You can configure this in the
> >*.lpf file or of course in the Design Planner. The actual frequency used
> >is process/batch dependent since it uses an internal PLL. I think
> >Lattice have specified an inaccuracy of 30%. Does it still fail if you
> >set the load frequency to the lowest value?
>
> Default - 2.5MHz.
> I've tried setting it faster and =A0do see the SPI rate increase once con=
fig starts, so it is seeing
> some of the datastream.
>
> >Other ideas:
> >-----------
> >I always put 10K pull-ups to 3.3V on the lines to and from the SPI
> >flash. Have you tied any unused flash inputs? (e.g. WP/HOLD to 3.3V on
> >Atmel parts)
>
> >You can also read a status register over the JTAG port with the Lattice
> >USB thingy and ispVM. Is anything 'interesting' set in this if you read
> >it after flash load fails? I've forgotten the exact feature/function in
> >ispVM. I'll have mine hooked up later today so I'll take a look and post
> >back.
>
> >Regards,
> >Charles
>
> I've now tried retargetting the project to a LFEC6 and loaded it on a Lat=
tice devboard with the same
> result so AFAICS it looks like it's a software issue generating a bad CRC=
 on the bit file.

If you have an earlier version of ispLever, you can try it to see if
the
CRC problem is a software bug.  I tend to leave older versions of the
tools around so I don't need to "upgrade" existing projects in order
to make minor changes.  All of my EC/ECP (not ECP2 or newer) were
built
using ispLever 6.x versions.  Never seen this problem myself.

Regards,
Gabor

Article: 142177
Subject: Re: Daisychaining fpga with SPI flash?
From: Ben <leowyuan@gmail.com>
Date: Tue, 28 Jul 2009 08:47:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 11:33=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > I've read about daisy chaining fpgas with Platform flash, but is daisy
> > chaining fpgas possible with SPI flash?
> > The documents at Xilinx seems to give only examples of single fpga
> > configuration with SPI flash.
>
> no, you cant use multiply SPI flash in chained mode
> (you may configure more than one FPGA from one SPI flash)
>
> well, some newer FPGA's include multi SPI support,
>
> * Spartan-6
> * Lattice-SC
> * Achronix Speedster
>
> all support multiply SPI flash in __parallel__ wiring
> (maybe some others too, i do not know all )
>
> Antti

Actually, I was thinking of configuring multiple FPGAs from one SPI
flash, but I don't see any examples in the Spartan6 configuration
document.
They give only the Platform flash example, which use pins like INIT_B
and PROG_B instead of MOSI in SPI.
Is the connection similar to the slave serial mode one using Platform
flash, and do you know of any examples?

Article: 142178
Subject: Re: Daisychaining fpga with SPI flash?
From: Ben <leowyuan@gmail.com>
Date: Tue, 28 Jul 2009 08:48:58 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 11:47=A0pm, Ben <leowy...@gmail.com> wrote:
> On Jul 28, 11:33=A0pm, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > > I've read about daisy chaining fpgas with Platform flash, but is dais=
y
> > > chaining fpgas possible with SPI flash?
> > > The documents at Xilinx seems to give only examples of single fpga
> > > configuration with SPI flash.
>
> > no, you cant use multiply SPI flash in chained mode
> > (you may configure more than one FPGA from one SPI flash)
>
> > well, some newer FPGA's include multi SPI support,
>
> > * Spartan-6
> > * Lattice-SC
> > * Achronix Speedster
>
> > all support multiply SPI flash in __parallel__ wiring
> > (maybe some others too, i do not know all )
>
> > Antti
>
> Actually, I was thinking of configuring multiple FPGAs from one SPI
> flash, but I don't see any examples in the Spartan6 configuration
> document.
> They give only the Platform flash example, which use pins like INIT_B
> and PROG_B instead of MOSI in SPI.
> Is the connection similar to the slave serial mode one using Platform
> flash, and do you know of any examples?

Sorry, I mean master serial mode.

Article: 142179
Subject: Re: Daisychaining fpga with SPI flash?
From: gabor <gabor@alacron.com>
Date: Tue, 28 Jul 2009 08:49:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > I've read about daisy chaining fpgas with Platform flash, but is daisy
> > chaining fpgas possible with SPI flash?
> > The documents at Xilinx seems to give only examples of single fpga
> > configuration with SPI flash.
>
> no, you cant use multiply SPI flash in chained mode
> (you may configure more than one FPGA from one SPI flash)
>
> well, some newer FPGA's include multi SPI support,
>
> * Spartan-6
> * Lattice-SC
> * Achronix Speedster
>
> all support multiply SPI flash in __parallel__ wiring
> (maybe some others too, i do not know all )
>
> Antti

I'm not sure that was what he was asking.  If you have a single
SPI flash big enough to hold all the bitstreams you can daisy
chain the FPGA's (not the flash chips).  One FPGA is in SPI master
mode and the others in serial slave mode.  Should be shown in the
configuration UG.

Article: 142180
Subject: Re: Daisychaining fpga with SPI flash?
From: Ben <leowyuan@gmail.com>
Date: Tue, 28 Jul 2009 09:00:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote:
> On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <Antti.Luk...@googlemail.com> wrote:
> > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > > I've read about daisy chaining fpgas with Platform flash, but is dais=
y
> > > chaining fpgas possible with SPI flash?
> > > The documents at Xilinx seems to give only examples of single fpga
> > > configuration with SPI flash.
>
> > no, you cant use multiply SPI flash in chained mode
> > (you may configure more than one FPGA from one SPI flash)
>
> > well, some newer FPGA's include multi SPI support,
>
> > * Spartan-6
> > * Lattice-SC
> > * Achronix Speedster
>
> > all support multiply SPI flash in __parallel__ wiring
> > (maybe some others too, i do not know all )
>
> > Antti
>
> I'm not sure that was what he was asking. =A0If you have a single
> SPI flash big enough to hold all the bitstreams you can daisy
> chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master
> mode and the others in serial slave mode. =A0Should be shown in the
> configuration UG.

Yes, I see this line "Another alternative is to use SPI mode for the
first device. The daisy-chain data is still sent out through DOUT in
SPI mode."
Well, this is in the Serial Daisy Chain section and they use a Xilinx
Platform Flash PROM.

Article: 142181
Subject: Re: iCore7 vs Core2 simulation & FPGA tool performance?
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 28 Jul 2009 16:04:32 GMT
Links: << >>  << T >>  << A >>
On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:

> On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
> 
>> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
>> <schvantzkoph@yahoo.com> wrote:
>> 
>>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx and
>>>Altera FPGA tools?
>> 
>> I'd also be very interested in Core7 vs Phenom II performance too (45nm
>> AMD ie Phenom II 955 etc.)
> 
> 
> We just got a new i7 machine for FPGA builds.  It tested at just over
> twice as fast as our high-end AMD box that was 2-3 years old.
> 
> I will publish the results in this ng within a week or two, assuming I
> can ever get the licensing for ISE 11.2 running on it.  (Thanks Xilinx,
> flexlm was a really good move.)
> 
> Regards,
> Allan

What's the clock rate on each machine? iCore7 motherboards and processors 
are twice as expensive as Core2 motherboards and processors, and 
mainstream Core2s have a higher clock rate than iCore7s, so the clock 
rate normalized performance is what's important.

Article: 142182
Subject: Re: Has anyone tried to install a Xilinx floating license? The
From: OutputLogic <evgenist@gmail.com>
Date: Tue, 28 Jul 2009 09:22:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
> After installing 11.1 I got another shock: projects are now not
> backwards compatible with older versions of ISE. The project is
> converted to the new format and gets a .xise extension. This will
> significantly complicate collaboration as all users will need 11.1!


It's much easier to work with the .xise because it is in text format.
Users wanted this for a long time; finally the changes can be tracked
in the source control software.
I figured that ISE is still using the same .ise binary internally.
When you open an .xise in the project navigator the first thing it
does is converts it to the .ise format. I tried using that .ise from
11.1 in ISE 10.x and it worked (perhaps somebody could provide a case
when it doesn't).


Evgeni

Article: 142183
Subject: Re: Daisychaining fpga with SPI flash?
From: "Antti.Lukats@googlemail.com" <Antti.Lukats@googlemail.com>
Date: Tue, 28 Jul 2009 09:24:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 7:00=A0pm, Ben <leowy...@gmail.com> wrote:
> On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote:
>
>
>
>
>
> > On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com"
>
> > <Antti.Luk...@googlemail.com> wrote:
> > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > > > I've read about daisy chaining fpgas with Platform flash, but is da=
isy
> > > > chaining fpgas possible with SPI flash?
> > > > The documents at Xilinx seems to give only examples of single fpga
> > > > configuration with SPI flash.
>
> > > no, you cant use multiply SPI flash in chained mode
> > > (you may configure more than one FPGA from one SPI flash)
>
> > > well, some newer FPGA's include multi SPI support,
>
> > > * Spartan-6
> > > * Lattice-SC
> > > * Achronix Speedster
>
> > > all support multiply SPI flash in __parallel__ wiring
> > > (maybe some others too, i do not know all )
>
> > > Antti
>
> > I'm not sure that was what he was asking. =A0If you have a single
> > SPI flash big enough to hold all the bitstreams you can daisy
> > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master
> > mode and the others in serial slave mode. =A0Should be shown in the
> > configuration UG.
>
> Yes, I see this line "Another alternative is to use SPI mode for the
> first device. The daisy-chain data is still sent out through DOUT in
> SPI mode."
> Well, this is in the Serial Daisy Chain section and they use a Xilinx
> Platform Flash PROM.- Hide quoted text -
>
> - Show quoted text -

Xilinx FPGA configuration controller has special function to BYPASS
config data
so you can stream it from the first device and use for any purpose you
need
(as config another FPGA as example)

it is ir-relevant if the configuration comes from platform flash or
spi flash

or, you can use another approuch what i used with lattice FPGA
as soon as FIRST FPGA is configured, it ROUTES the spi flash
out to some downstream FPGA config interface and starts generating
SPI clock, this "user config controller" is very small and doesnt take
much resources

Antti





Article: 142184
Subject: Re: iCore7 vs Core2 simulation & FPGA tool performance?
From: Jason Zheng <Xin.Zheng@jpl.nasa.gov>
Date: Tue, 28 Jul 2009 09:42:08 -0700
Links: << >>  << T >>  << A >>
On 28 Jul 2009 16:04:32 GMT
General Schvantzkoph <schvantzkoph@yahoo.com> wrote:

> On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:
> 
> > On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
> > 
> >> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
> >> <schvantzkoph@yahoo.com> wrote:
> >> 
> >>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
> >>>and Altera FPGA tools?
> >> 
> >> I'd also be very interested in Core7 vs Phenom II performance too
> >> (45nm AMD ie Phenom II 955 etc.)
> > 
> > 
> > We just got a new i7 machine for FPGA builds.  It tested at just
> > over twice as fast as our high-end AMD box that was 2-3 years old.
> > 
> > I will publish the results in this ng within a week or two,
> > assuming I can ever get the licensing for ISE 11.2 running on it.
> > (Thanks Xilinx, flexlm was a really good move.)
> > 
> > Regards,
> > Allan
> 
> What's the clock rate on each machine? iCore7 motherboards and
> processors are twice as expensive as Core2 motherboards and
> processors, and mainstream Core2s have a higher clock rate than
> iCore7s, so the clock rate normalized performance is what's important.

Clock rates is just an artificial number; I'd be more interested in
performance normalized to non-recurring cost (purchase price) and
operating cost (power consumption).

Article: 142185
Subject: Re: PAR runs successfully, simulation fails
From: "arik" <ariff.arsh@gmail.com>
Date: Tue, 28 Jul 2009 11:44:45 -0500
Links: << >>  << T >>  << A >>
>Hi, i'm using ise 9.2i for my design, and the PAR runs successfully
meeting
>all my constraints with no timing errors, but the simulation reports
>multiple warnings of hold/setup violation, what is the problem?
>
>
>
Hi,
Please check whether the violated paths are constrained/not.
if constrained then check if they were constrained as false
paths/unrelated.




Article: 142186
Subject: Different behavior of FSM in same simulation
From: "glnazar" <gabriel.nazar2@gmail.com>
Date: Tue, 28 Jul 2009 11:44:50 -0500
Links: << >>  << T >>  << A >>
Hi!

I'm having a small problem with simulations using Xilinx ISE 11.1. In my
code there are some FSM which were declared like:

process(clk, rst)
begin
    if rst = '1' then
        state <= IDLE;
    elsif clk'event and clk='1' then
        case state is
            when IDLE =>
                if start = '1' then
                    state <= NEXT_STATE;
                end if;
    [...]

With start being an entity port. Now, when running a behavior simulation,
I get different results for this code when it's in the top level block
(which receives its stimuli from the simulation testbench file) and when
it's in an inner block of the design (which receives stimuli from other
blocks). More specifically, the transition to NEXT_STATE happens in the
same cycle start is raised to 1 in the top level block, but will only
happen in the next cycle (when start already is 0) in inner blocks. I'm
thinking, considering the real circuit will have delays, that the second
behavior makes more sense. However, in the behavioral simulation, all
combinational logic have zero delay, and so the changes in the signals
happen in the same time - the least I expected was that the response of all
circuits would be coherent.
So, anyone got and explanation for this? Maybe a way to make all circuits
behave the same way?

Thank you!
P.S.: I'm simulating using the ISim software included with ISE 11.1.



Article: 142187
Subject: Re: Different behavior of FSM in same simulation
From: Andy <jonesandy@comcast.net>
Date: Tue, 28 Jul 2009 10:54:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
Watch out for delta delays on your clock between the top level and
lower levels (i.e. from an assignment of one clock signal from
another). The delta delay incurred by the clock will cause it not to
see inputs on the same clock cycle in RTL simulation.

Andy

Article: 142188
Subject: Re: iCore7 vs Core2 simulation & FPGA tool performance?
From: General Schvantzkoph <schvantzkoph@yahoo.com>
Date: 28 Jul 2009 17:54:32 GMT
Links: << >>  << T >>  << A >>
On Tue, 28 Jul 2009 09:42:08 -0700, Jason Zheng wrote:

> On 28 Jul 2009 16:04:32 GMT
> General Schvantzkoph <schvantzkoph@yahoo.com> wrote:
> 
>> On Tue, 28 Jul 2009 15:22:25 +0000, Allan Herriman wrote:
>> 
>> > On Sun, 26 Jul 2009 10:28:03 -0700, Muzaffer Kal wrote:
>> > 
>> >> On 26 Jul 2009 16:23:16 GMT, General Schvantzkoph
>> >> <schvantzkoph@yahoo.com> wrote:
>> >> 
>> >>>Has anyone benchmarked Core7 vs Core2 on NCverilog, Questa, Xilinx
>> >>>and Altera FPGA tools?
>> >> 
>> >> I'd also be very interested in Core7 vs Phenom II performance too
>> >> (45nm AMD ie Phenom II 955 etc.)
>> > 
>> > 
>> > We just got a new i7 machine for FPGA builds.  It tested at just over
>> > twice as fast as our high-end AMD box that was 2-3 years old.
>> > 
>> > I will publish the results in this ng within a week or two, assuming
>> > I can ever get the licensing for ISE 11.2 running on it. (Thanks
>> > Xilinx, flexlm was a really good move.)
>> > 
>> > Regards,
>> > Allan
>> 
>> What's the clock rate on each machine? iCore7 motherboards and
>> processors are twice as expensive as Core2 motherboards and processors,
>> and mainstream Core2s have a higher clock rate than iCore7s, so the
>> clock rate normalized performance is what's important.
> 
> Clock rates is just an artificial number; I'd be more interested in
> performance normalized to non-recurring cost (purchase price) and
> operating cost (power consumption).

Within an architecture CPU clock rate is the one thing that's directly 
proportional to performance. Memory performance has a small effect on 
performance, but in the age of multi-megabyte caches it's a distinctly 
second order effect. Price is something that you worry about at the time 
of purchase, the price that someone else paid for their system is 
completely irrelevant. What I want to know is the relative performance of 
Core2 vs iCore7 on a few important applications specifically NCverilog, 
which is where I spend 98% of my time, and the Xilinx and Altera FPGA 
tools. My current fastest machine is a 3GHz Core2 overclocked to 4GHz 
(I'm using a heatsink the size of Volkswagen). The motherboard for that 
system is $115 these days and the CPU is $168. A 2.66Ghz iCore7 is $280, 
a 3GHz iCore7 is $569 and an iCore7 motherboard is in the neighborhood of 
$250. If the clock for clock NCVerilog performance of an iCore7 is really 
2X a Core2 then it makes sense to buy one assuming that I can get a 
similar overclock on the iCore7. If it's only 30% then it doesn't make 
sense because it's unlikely that a 2.66GHz iCore7 can be overclocked to 
the same clock as a 3GHz Core2.

Article: 142189
Subject: Re: Xilinx ISE 11.x lossage
From: Andy Peters <google@latke.net>
Date: Tue, 28 Jul 2009 11:28:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 25, 11:36=A0pm, "MikeWhy" <boat042-nos...@yahoo.com> wrote:
> "Andy Peters" <goo...@latke.net> wrote in message
>
> news:89bb1088-36f1-435c-8107-284367a3ac23@13g2000prl.googlegroups.com...
> The project is in an svn repo. The great thing about this now-deleted
> feature was that it boiled the ISE project file down to a couple of
> tcl scripts which are scc-friendly. The only other things in the repo
> are the sources and a .ucf.
>
> =3D=3D=3D=3D=3D=3D=3D=3D=3D
> The <project>.xise file serves the need, without exporting or importing.

True indeed, but if your project originated in the earlier version of
the tools, it still needs to be recreated.

I opened a WebCase, and the support person was able to figure out
exactly how to use the tcl shell to import the previous version's
script and make it into a proper .xise project file.

> Now if only I can get it to stop polluting the project root with all thos=
e
> generated files.

Yeah, well, you should be happy that you don't have to keep your HDL
sources in the same directory as all of the project cruft! (How long
did it take Xilinx to figure that out?)

-a-

Article: 142190
Subject: Re: Xilinx ISE 11.x lossage
From: Andy Peters <google@latke.net>
Date: Tue, 28 Jul 2009 11:32:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 27, 8:35=A0am, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:
> On Fri, 24 Jul 2009 10:08:19 -0700, Andy Peters wrote:
> > On Jul 24, 1:17=A0am, luudee <rudolf.usselm...@gmail.com> wrote:
> >> On Jul 23, 12:36=A0am, Andy Peters <goo...@latke.net> wrote:
>
> >> > I installed the full-up Xilinx ISE 11.x tools on a spare machine so =
I
> >> > could give it a test-drive. (We have a site license.)
>
> >> ...
>
> >> > I opened a WebCase, which I suspect will be ignored like every other
> >> > WebCase.
>
> >> > -a
>
> >> Well, Andy, I hate to say that, but it is your own fault. Perhaps you
> >> are a new user ...
>
> > No, actually, I've being doing this for a long time -- remember XACT?
>
> >> Using anything but only the fundamental features of the tools is askin=
g
> >> for trouble. Even when just using the fundamental tools like "map
> >> <option>" in a perl script you will see that they tend to rename and
> >> change the way some switches work from release to release.
>
> > I realize that things change all the time, which is why I like to
> > minimize my dependency on the tools. But unfortunately, that's not
> > always possible. And this little archiving feature was one of Xilinx'
> > better ideas, which is probably why they shitcanned it.
>
> I have one word for you, cvs. I would never use a vendor specific source
> control system when there are so many first class open source choices
> available. I prefer good old cvs because it's transparent, i.e. it
> doesn't use any binary databases it just uses the regular file system and
> a few text base files. It's also completely reliable across platforms,
> all of my systems are Linux based while my partner uses cygwin on XP and
> we have no problem sharing files. You could also use svn or git, I don't
> like svn and I've never tried git but they are all free and packaged with
> the major distros so you can make your own choice.

Actually, as I've noted in other posts in this thread, I use
Subversion.

My point was that the old .ise file couldn't reasonably live in the
repo, and that Xilinx added a feature called Project | Source Control
| Import/Export boiled the binary ISE project file down to a couple of
tcl scripts, which are revision-control friendly. It is unfortunate
that Xilinx chose to put this feature in a menu item called "Source
Control" when it really has nothing to do with scc.

-a

Article: 142191
Subject: Re: Daisychaining fpga with SPI flash?
From: gabor <gabor@alacron.com>
Date: Tue, 28 Jul 2009 11:44:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 12:24=A0pm, "Antti.Luk...@googlemail.com"
<Antti.Luk...@googlemail.com> wrote:
> On Jul 28, 7:00=A0pm, Ben <leowy...@gmail.com> wrote:
>
>
>
> > On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote:
>
> > > On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com"
>
> > > <Antti.Luk...@googlemail.com> wrote:
> > > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:
>
> > > > > I've read about daisy chaining fpgas with Platform flash, but is =
daisy
> > > > > chaining fpgas possible with SPI flash?
> > > > > The documents at Xilinx seems to give only examples of single fpg=
a
> > > > > configuration with SPI flash.
>
> > > > no, you cant use multiply SPI flash in chained mode
> > > > (you may configure more than one FPGA from one SPI flash)
>
> > > > well, some newer FPGA's include multi SPI support,
>
> > > > * Spartan-6
> > > > * Lattice-SC
> > > > * Achronix Speedster
>
> > > > all support multiply SPI flash in __parallel__ wiring
> > > > (maybe some others too, i do not know all )
>
> > > > Antti
>
> > > I'm not sure that was what he was asking. =A0If you have a single
> > > SPI flash big enough to hold all the bitstreams you can daisy
> > > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master
> > > mode and the others in serial slave mode. =A0Should be shown in the
> > > configuration UG.
>
> > Yes, I see this line "Another alternative is to use SPI mode for the
> > first device. The daisy-chain data is still sent out through DOUT in
> > SPI mode."
> > Well, this is in the Serial Daisy Chain section and they use a Xilinx
> > Platform Flash PROM.- Hide quoted text -
>
> > - Show quoted text -
>
> Xilinx FPGA configuration controller has special function to BYPASS
> config data
> so you can stream it from the first device and use for any purpose you
> need
> (as config another FPGA as example)
>
> it is ir-relevant if the configuration comes from platform flash or
> spi flash
>
> or, you can use another approuch what i used with lattice FPGA
> as soon as FIRST FPGA is configured, it ROUTES the spi flash
> out to some downstream FPGA config interface and starts generating
> SPI clock, this "user config controller" is very small and doesnt take
> much resources
>
> Antti

Actually at least for ECP2, SPI config of multiple parts is easy
with Lattice.  The first FPGA is in SPI master mode and the
subsequent FPGA's are in serial slave mode.  First FPGA CCLK
is both  SPI clock and downstream CCLK for serial config.  The
tricky part with lattice is figuring out how to merge the
bitstreams into the single SPI PROM (you need the "Universal
File Writer" for this).

Regards,
Gabor

Article: 142192
Subject: Re: PAR runs successfully, simulation fails
From: gabor <gabor@alacron.com>
Date: Tue, 28 Jul 2009 11:46:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 12:44=A0pm, "arik" <ariff.a...@gmail.com> wrote:
> >Hi, i'm using ise 9.2i for my design, and the PAR runs successfully
> meeting
> >all my constraints with no timing errors, but the simulation reports
> >multiple warnings of hold/setup violation, what is the problem?
>
> Hi,
> Please check whether the violated paths are constrained/not.
> if constrained then check if they were constrained as false
> paths/unrelated.

Nine times out of ten, setup and hold violations stem from
the testbench not meeting the constraints given to the
place & route tools.  It does no good to meet constraints
if the external world doesn't meet them, too.

Article: 142193
Subject: Re: Different behavior of FSM in same simulation
From: gabor <gabor@alacron.com>
Date: Tue, 28 Jul 2009 11:49:47 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Jul 28, 1:54=A0pm, Andy <jonesa...@comcast.net> wrote:
> Watch out for delta delays on your clock between the top level and
> lower levels (i.e. from an assignment of one clock signal from
> another). The delta delay incurred by the clock will cause it not to
> see inputs on the same clock cycle in RTL simulation.
>
> Andy

Don't forget to have hold time in your testbench signals.  You
don't need delays, just a dependency on the clock edge.  If you
generate both the clock and the start signal together, you should
expect the timing you're seeing.  If start depends on clock'event
then you should see the behavior of the lower level module.

Article: 142194
Subject: Re: Using OPEN in port map
From: JimLewis <Jim@SynthWorks.com>
Date: Tue, 28 Jul 2009 12:00:23 -0700 (PDT)
Links: << >>  << T >>  << A >>
> On the other hand, this particular item is something that I submitted
> to the VHDL standards group a few years back and was accepted at that
> time as a 'good' idea...maybe it made it into VHDL '08...if not theirs
> always VHDL 201x.

Kevin,
Do you have a bug ID for it?  I was looking through the bugzilla
database and could not find it.

Jim


Article: 142195
Subject: ISE error messages
From: "Roger" <rogerwilson@hotmail.com>
Date: Tue, 28 Jul 2009 21:07:04 +0100
Links: << >>  << T >>  << A >>
Can anyone tell me what the following error messages mean please?

ERROR:ProjectMgmt:357 - Problem updating Cs using the Transform Instance.
ERROR:ConstraintSystem:170 - No constraint database file was specified.

Thanks,

Rog 

Article: 142196
Subject: Re: Lattice EC - some .bit files not loading from SPI flash
From: Mike Harrison <mike@whitewing.co.uk>
Date: Tue, 28 Jul 2009 22:14:04 +0100
Links: << >>  << T >>  << A >>
On Tue, 28 Jul 2009 08:46:07 -0700 (PDT), gabor <gabor@alacron.com> wrote:

>On Jul 28, 5:42 am, Mike Harrison <m...@whitewing.co.uk> wrote:
>> On Tue, 28 Jul 2009 10:50:48 +0200, Charles Gardiner <inva...@invalid.invalid> wrote:
>> >Hi Mike,
>>
>> >at what frequency is your SPI running. You can configure this in the
>> >*.lpf file or of course in the Design Planner. The actual frequency used
>> >is process/batch dependent since it uses an internal PLL. I think
>> >Lattice have specified an inaccuracy of 30%. Does it still fail if you
>> >set the load frequency to the lowest value?
>>
>> Default - 2.5MHz.
>> I've tried setting it faster and  do see the SPI rate increase once config starts, so it is seeing
>> some of the datastream.
>>
>> >Other ideas:
>> >-----------
>> >I always put 10K pull-ups to 3.3V on the lines to and from the SPI
>> >flash. Have you tied any unused flash inputs? (e.g. WP/HOLD to 3.3V on
>> >Atmel parts)
>>
>> >You can also read a status register over the JTAG port with the Lattice
>> >USB thingy and ispVM. Is anything 'interesting' set in this if you read
>> >it after flash load fails? I've forgotten the exact feature/function in
>> >ispVM. I'll have mine hooked up later today so I'll take a look and post
>> >back.
>>
>> >Regards,
>> >Charles
>>
>> I've now tried retargetting the project to a LFEC6 and loaded it on a Lattice devboard with the same
>> result so AFAICS it looks like it's a software issue generating a bad CRC on the bit file.
>
>If you have an earlier version of ispLever, you can try it to see if
>the
>CRC problem is a software bug.  I tend to leave older versions of the
>tools around so I don't need to "upgrade" existing projects in order
>to make minor changes.  All of my EC/ECP (not ECP2 or newer) were
>built
>using ispLever 6.x versions.  Never seen this problem myself.
>
>Regards,
>Gabor

Good idea, unfortunately 6.x does not appear to be available on the Lattice website - only the
service packs

Article: 142197
Subject: cool chart
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Tue, 28 Jul 2009 14:52:54 -0700
Links: << >>  << T >>  << A >>

http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif


John


Article: 142198
Subject: Re: cool chart
From: "Joel Koltner" <zapwireDASHgroups@yahoo.com>
Date: Tue, 28 Jul 2009 15:12:35 -0700
Links: << >>  << T >>  << A >>
> http://i.cmpnet.com/eetimes/news/09/07/1565chart_pg18.gif

Interesting, indeed.

Cypress had viable products but I'm convinced that management was the problem. 
(I also remember they wanted a rather large premium for their CPLDs that were 
sometimes only marginally better than the competition's.)

I don't know what Vantis's problem was, but at least after Lattive bought them 
they kept a few of the parts around.

Intel doesn't have its heart in much of anything but their desktop CPUs --  
they consistently bring out interesting products and then discontinue them 
just when they're starting to gain traction.

You're pretty much a pure Xilinx man these days, aren't you, John?




Article: 142199
Subject: Re: Used Cyclone EP1C6 boards
From: "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at>
Date: Wed, 29 Jul 2009 00:22:17 +0200
Links: << >>  << T >>  << A >>
> Hi all,
>
> I have a bunch of used FPGA boards available. They have been replaced
> in a product by a similar board that has additional NAND Flash.
> Here are the details of the board:
>
> * Altera Cyclone EP1C6Q240 FPGA
> * 512 KB FLASH (for FPGA configuration and program code)
> * 1 MB fast SRAM
> * ByteBlasterMV port
> * Watchdog with LED
> * EPM7064 PLD to load FPGA from FLASH (on watchdog reset)
> * Voltage regulator (1V5)
> * Crystal clock (20 MHz) at the PLL input (up to 640 MHz internal)
> * Serial interface (MAX3232)
> * 56 general purpose IO pins
>
> Price is EUR 99,-
>
> See: http://www.jopdesign.com/cyclone/index.jsp
>

I forgot to say that all boards are fully tested. Furthermore, as
beeing used without problem in the production for some time this
served even as a reliability test ;-)

Cheers,
Martin 





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