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Hi,
I'm trying to run Synplify pro with multiple constraint files in one
tcl script, say rev1 with constraint test_1.sdc only while rev2 with
constraint test_2.sdc only. I write the code as
set seq {1 2}
foreach num $seq {
set pre [expr $num-1]
impl -add rev_$num
add_file -constraint test_$num.sdc
project_file -remove test_$pre.sdc
project -log_file rev_$num/$num.srr
set_option -result_file rev_$num/rev_$num.edf
impl -active rev_$num
project -run
# project_file -remove test_$num.sdc
open_file -edit_file $num.srr
}
what confused me is that when synplify runs, I can see two
implemenations are added. Synplify runs with rev_1 first then rev_2.
But no constraint file is added to the project. Can anybody help me to
find the problem? thanks.
Article: 141326Hi, I'm trying to read the DNA of a Spartan3A-DSP chip over JTAG. The datasheet gives very little information about this. I found the IR code, the note that ISC_ENABLE must be loaded before ISC_DNA, and also that ISC_ENABLE implies a shutdown. With nothing more than this information, I tried to implement it. It works when the chip is not yet loaded with a bitstream. However, if it is, then I read only zeroes instead of the DNA. Since I have no documentation about how exactly the ISC_ENABLE command works, I tried two things: a) load ISC_ENABLE and directly afterwards load ISC_DNA b) load ISC_ENABLE, then loop 12x or 10000x or 100000x RUN-TEST/IDLE, and then load ISC_DNA. Neither of these improved anything. I could not find any documentation that clarifies this. Unfortunately IMPACT (10.1) doesn't seem to read the DNA either, so I can't record and inspect an SVF either. Does anyone here have more information about ISC_DNA or ISC_ENABLE? Regards, MarcArticle: 141327
> One thing I was wondering about with the bus switches: I want to be > able to interface with standard 3.3V PCI as well as 5.0V PCI. I > believe I cannot do both at the same time, so it is either one or the > other. Can I just put a switch on my board that will connect either > 3.3V ref or 5V ref to the bus switches to determine which mode I am > in? I don't want to be in 5V mode all the time, because if I want to > master a 3.3V peripheral PCI device, 5V PCI signaling might burn up > the peripheral. Anyone have any thoughts here? Have a look at the IDT Quickswitches I mentioned previously. These aren't voltage translators as such as FETs that are biased so that if either of the inputs rise above a cetain threshold the FET resistance increases. If you consider the PCI bus side as the input then the FPGA side is effectively 'clamped' to whatever threshold you set (via reference pins). This can then be used with both the 5V and 3.3V PCI buses. NialArticle: 141328
Marc Jet <jetmarc@hotmail.com> wrote:
> Hi,
> I'm trying to read the DNA of a Spartan3A-DSP chip over JTAG.
> The datasheet gives very little information about this. I found the
> IR code, the note that ISC_ENABLE must be loaded before ISC_DNA, and
> also that ISC_ENABLE implies a shutdown.
> With nothing more than this information, I tried to implement it. It
> works when the chip is not yet loaded with a bitstream. However, if
> it is, then I read only zeroes instead of the DNA.
> Since I have no documentation about how exactly the ISC_ENABLE command
> works, I tried two things:
> a) load ISC_ENABLE and directly afterwards load ISC_DNA
> b) load ISC_ENABLE, then loop 12x or 10000x or 100000x RUN-TEST/IDLE,
> and then load ISC_DNA.
> Neither of these improved anything. I could not find any
> documentation that clarifies this. Unfortunately IMPACT (10.1)
> doesn't seem to read the DNA either, so I can't record and inspect an
> SVF either.
My code in xc3sprog has:
switch(family)
{
case 0x11: /* XC3SA*/
case 0x13: /* XC3SAN*/
case 0x1c: /* SC3SADSP*/
{
byte data[8];
jtag->shiftIR(&ISC_DNA);
jtag->shiftDR(0, data, 64);
io->cycleTCK(1);
if (*(long long*)data != -1LL)
/* ISC_DNA only works on a unconfigured device, see AR #29977*/
printf("DNA is 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
data[0], data[1], data[2], data[3],
data[4], data[5], data[6], data[7]);
break;
}
}
--
Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 141329
On Jun 18, 4:58=A0pm, skyworld <chenyong20...@gmail.com> wrote:
> Hi,
>
> I'm trying to run Synplify pro with multiple constraint files in one
> tcl script, say rev1 with constraint test_1.sdc only while rev2 with
> constraint test_2.sdc only. I write the code as
>
> set seq {1 2}
>
> foreach num $seq {
> =A0 =A0 =A0 =A0 set pre [expr $num-1]
> =A0 =A0 =A0 =A0 impl -add rev_$num
> =A0 =A0 =A0 =A0 add_file -constraint test_$num.sdc
> =A0 =A0 =A0 =A0 project_file -remove test_$pre.sdc
> =A0 =A0 =A0 =A0 project -log_file rev_$num/$num.srr
> =A0 =A0 =A0 =A0 set_option -result_file rev_$num/rev_$num.edf
> =A0 =A0 =A0 =A0 impl -active rev_$num
> =A0 =A0 =A0 =A0 project -run
> # =A0 =A0 =A0 project_file -remove test_$num.sdc
> =A0 =A0 =A0 =A0 open_file -edit_file $num.srr
>
> }
>
> what confused me is that when synplify runs, I can see two
> implemenations are added. Synplify runs with rev_1 first then rev_2.
> But no constraint file is added to the project. Can anybody help me to
> find the problem? thanks.
My purpose is to try if I can get better result with different
constraint. There are several clocks in my design, I can't use
"set_option -frequency $freq" to assign different frequency to
different clock, my idea is to write different constraint files with
different constraint file and run to see if I can get better result.
But now it seems this doesn't work. Can anybody help me? thanks.
Article: 141330
skyworld wrote:
> My purpose is to try if I can get better result with different
> constraint. There are several clocks in my design,
I make separate entities for each clock and
make Fmax for each of those first.
Then I connect the modules using "known good"
synchronization blocks.
-- Mike Treseler
Article: 141331seems its coming soon, a file xp3.v exist and it is larger than xp2.v so there are more features in XP3 :) im guessint it about same as ECP3 just flash based AnttiArticle: 141332
On Jun 10, 7:28=A0pm, "Manfred" <octavian_machi...@yahoo.com> wrote: > Hi all, > I'm having the following problem: I'm trying to interface a XUP Virtex-II > Pro Development System with a CMOS camera, and the output voltage on the > board's expansion connectors is 2.5V for logic '1', no matter what > IOSTANDARD is specified in the ucf file. I understand this is because the > Vcco for the io bank is 2.5V. (However, in the schematic it shows that fo= r > the IO Banks that relate to the expansion connectors, Vcco=3D3.3V.) > My question is if it possible to change the Vcco supply voltage by any > sw/hw means. > Thank you in advance. I am having the same issue, but for a different application. I need 3.3V LVTTL outputs, which the expansion points are supposed to be according to the documentation, but when I measure the outputs against a 3.3V device, they are too low and resemble 2.5V LVCMOS.Article: 141333
On Jun 19, 12:57=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > skyworld wrote: > > My purpose is to try if I can get better result with different > > constraint. There are several clocks in my design, > > I make separate entities for each clock and > make Fmax for each of those first. > Then I connect the modules using "known good" > synchronization blocks. > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler Hi Mike, thanks for your reply. Well, there is something different to me. My design is a larger one, which implement several IPs with a lot of glue logics. I can't try "seperate entities for each clock" because I need to fit the design into FPGA. thanks. skyworldArticle: 141334
?? "Tommy Thorn" <tommy.thorn@gmail.com> ??????:32f98629-60fc-47a5-9ab0-3dde9301fa8c@c9g2000yqm.googlegroups.com... On Jun 8, 1:25 am, rickman <gnu...@gmail.com> wrote: > On Jun 8, 3:19 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > I wrote: > > > In fact, all the options for getting that > > > extra write port pretty much annul the performance benefits of running > > > multiple instructions. (And I haven't even started talking about the > > > bypass network and the hazard detection here). > > > rickman kibitzed: > > > > You can use two write ports on block rams. They can be hard to infer, > > > but they can always be instantiated. > > > Your register files are write-only? You can't have two write ports to > > a memory block if you need to read arbitrary locations as well. > > > Unfortunately there isn't any one good solution, tough there are some > > options. For example : > > - Time multiplexing (there goes the benefit of superscalar), > > - Banking (Complicated and performance depends on few conflicts), > > - Inferred from logic (expensive, but sometimes the best option), and > > - "Distributed": represent each location as the sum of parts (one > > cycle extra write latency and uses a lot of memory blocks, eg. 2w4r = > > 10 blocks). > > > Tommy > > I think you are mistaken. LOL. You preceed to ... > The read and write must share an address, ... confirm what I wrote. > but you can do either a read or a write on either clock cycle on each > port. If you need dual ported ram that can do both read and write > simultaneously, you can run the RAM at *double speed* and in effect > multiplex it. The very list option I listed. > I doubt that the block ram in FPGAs will be the speed > limiting factor even when running at a double speed clock. Doubt as much as you like. I've been there and got the T-shirt. TommyArticle: 141335
yumo55 "Tommy Thorn" <tommy.thorn@gmail.com> ??????:32f98629-60fc-47a5-9ab0-3dde9301fa8c@c9g2000yqm.googlegroups.com... On Jun 8, 1:25 am, rickman <gnu...@gmail.com> wrote: > On Jun 8, 3:19 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > > > > I wrote: > > > In fact, all the options for getting that > > > extra write port pretty much annul the performance benefits of running > > > multiple instructions. (And I haven't even started talking about the > > > bypass network and the hazard detection here). > > > rickman kibitzed: > > > > You can use two write ports on block rams. They can be hard to infer, > > > but they can always be instantiated. > > > Your register files are write-only? You can't have two write ports to > > a memory block if you need to read arbitrary locations as well. > > > Unfortunately there isn't any one good solution, tough there are some > > options. For example : > > - Time multiplexing (there goes the benefit of superscalar), > > - Banking (Complicated and performance depends on few conflicts), > > - Inferred from logic (expensive, but sometimes the best option), and > > - "Distributed": represent each location as the sum of parts (one > > cycle extra write latency and uses a lot of memory blocks, eg. 2w4r = > > 10 blocks). > > > Tommy > > I think you are mistaken. LOL. You preceed to ... > The read and write must share an address, ... confirm what I wrote. > but you can do either a read or a write on either clock cycle on each > port. If you need dual ported ram that can do both read and write > simultaneously, you can run the RAM at *double speed* and in effect > multiplex it. The very list option I listed. > I doubt that the block ram in FPGAs will be the speed > limiting factor even when running at a double speed clock. Doubt as much as you like. I've been there and got the T-shirt. TommyArticle: 141336
"rickman" <gnuarm@gmail.com> ??????:85c11a38-633d-4953-a21b-633167228274@s28g2000vbp.googlegroups.com... On Jun 9, 10:18 pm, john <jprovide...@yahoo.com> wrote: > On Jun 9, 5:42 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > > > > > > rickman wrote: > > > >> Why do you think there is no delay in the real part? No matter where > > >> you measure it, there will be some delay. > > > > True, but the exact delay is unknown until place and route. I prefer > > > to to leave it as a delta delay for the description and let synthesis > > > fill in the real value for STA or backanno. > > > > -- Mike Treseler > > > Why? What does it hurt to have a short stand-in delay in the functional > > simulation model. It has already been pointed out that it makes > > debugging > > a little easier, especially for the less trained. > > > ---Matthew Hicks > > Why does it hurt? Supposing you've got a bad clocking scheme that > would show a problem in > unit simulation if the part was modeled like all the other behavioral > code? The delay could mask > a potential problem that could be a nightmare to debug in the FPGA. > > John Providenza I'm not following. What sort of problem would this delay mask? What bad clocking scheme would be hidden by a signal delay? RickArticle: 141337
czlj9999 "??" <czlj9999@163.com> 写入消息新闻:h1ev28$s0r$1@news.cn99.com... > ?? > "Tommy Thorn" <tommy.thorn@gmail.com> > ??????:32f98629-60fc-47a5-9ab0-3dde9301fa8c@c9g2000yqm.googlegroups.com... > On Jun 8, 1:25 am, rickman <gnu...@gmail.com> wrote: >> On Jun 8, 3:19 am, Tommy Thorn <tommy.th...@gmail.com> wrote: >> >> >> >> > I wrote: >> > > In fact, all the options for getting that >> > > extra write port pretty much annul the performance benefits of >> > > running >> > > multiple instructions. (And I haven't even started talking about the >> > > bypass network and the hazard detection here). >> >> > rickman kibitzed: >> >> > > You can use two write ports on block rams. They can be hard to infer, >> > > but they can always be instantiated. >> >> > Your register files are write-only? You can't have two write ports to >> > a memory block if you need to read arbitrary locations as well. >> >> > Unfortunately there isn't any one good solution, tough there are some >> > options. For example : >> > - Time multiplexing (there goes the benefit of superscalar), >> > - Banking (Complicated and performance depends on few conflicts), >> > - Inferred from logic (expensive, but sometimes the best option), and >> > - "Distributed": represent each location as the sum of parts (one >> > cycle extra write latency and uses a lot of memory blocks, eg. 2w4r = >> > 10 blocks). >> >> > Tommy >> >> I think you are mistaken. > > LOL. You preceed to ... > >> The read and write must share an address, > > ... confirm what I wrote. > >> but you can do either a read or a write on either clock cycle on each >> port. If you need dual ported ram that can do both read and write >> simultaneously, you can run the RAM at *double speed* and in effect >> multiplex it. > > The very list option I listed. > >> I doubt that the block ram in FPGAs will be the speed >> limiting factor even when running at a double speed clock. > > Doubt as much as you like. I've been there and got the T-shirt. > > Tommy >Article: 141338
I've been trying to understand the differences between the simultaneous switching guidelines on the S3E and S3A parts. I've gone back and fourth a few times now with Xilinx tech support but so far the replies have been less than satisfactory, so maybe someone here can help me. When I compare the guidelines for these two families, it appears that, for the same I/O standard, the older S3E parts support about twice as many SSO outputs per VCCO/GND pair as the newer S3A parts. Even stranger, the S3A parts in BGA packages are just a little or in many cases no better than the leaded packages in terms of allowed outputs/pair (while for the S3E parts, the BGA packages are about 2-3x better than the leaded parts). Seems like it would be a lot harder to implement, say, a wide high-speed memory interface with an S3A than with an S3E. Could something about the package and/or chip design of the S3As really be that much different than the S3Es? Or maybe the measurement methodology changed from the S3E to the S3A? Any insight is appreciated. - JayArticle: 141339
On Jun 19, 9:14=A0am, skyworld <chenyong20...@gmail.com> wrote: > On Jun 19, 12:57=A0am, Mike Treseler <mtrese...@gmail.com> wrote: > > > skyworld wrote: > > > My purpose is to try if I can get better result with different > > > constraint. There are several clocks in my design, > > > I make separate entities for each clock and > > make Fmax for each of those first. > > Then I connect the modules using "known good" > > synchronization blocks. > > > =A0 =A0 =A0 =A0 =A0 -- Mike Treseler > > Hi Mike, > > thanks for your reply. Well, there is something different to me. My > design is a larger one, which implement several IPs with a lot of glue > logics. I can't try "seperate entities for each clock" because I need > to fit the design into FPGA. thanks. > > skyworld In fact I can finish these jobs through GUI. But with GUI you can't do synthesis automatically. That is the way why I insist on doing so. Now I was stopped because no matter which way I try to use , with "foreach" loop or run the script sequentially, the synplify seems to: 1) search how many processes are there in the script; 2) "enum" these process to project at very first time and use the last constraint file as the only constraint file for all processes; 3) run these process sequentially. Can anybody tell me how can I do this synthesis correctly?Article: 141340
Hi, My computer has Modelsim Altera web version installed. Now, I want to use Xilinx tools (ISE 9.2i) with System Generator and Modelsim XE. For the black box function, ModelsimXE always cannot work because it installs altera, but not Xilinx, library after correctly call: # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl. # Loading project NiosII_stratixII_2s60_standard_sim I exec ModelsimXE III 6.4b at the Windows Vista does not work in the same way. But, at the Xilinx ISE, Modelsim XE III works normal. Even though I uninstall ModelsimAE, the above problem still exists. Could you tell me which settings can correct that? Thanks,Article: 141341
On Jun 19, 1:53=A0am, Jay K <jke...@gmail.com> wrote: > I've been trying to understand the differences between the > simultaneous switching guidelines on the S3E and S3A parts. =A0I've gone > back and fourth a few times now with Xilinx tech support but so far > the replies have been less than satisfactory, so maybe someone here > can help me. =A0When I compare the guidelines for these two families, it > appears that, for the same I/O standard, the older S3E parts support > about twice as many SSO outputs per VCCO/GND pair as the newer S3A > parts. =A0Even stranger, the S3A parts in BGA packages are just a little > or in many cases no better than the leaded packages in terms of > allowed outputs/pair (while for the S3E parts, the BGA packages are > about 2-3x better than the leaded parts). =A0Seems like it would be a > lot harder to implement, say, a wide high-speed memory interface with > an S3A than with an S3E. =A0Could something about the package and/or > chip design of the S3As really be that much different than the S3Es? > Or maybe the measurement methodology changed from the S3E to the S3A? > Any insight is appreciated. > > - Jay The only obvious change would be the rise / fall time on the I/O's. It's unlikely that the I/O lead inductances would be different between two device families in the same package. On the other hand it could be that there is less power/GND lead inductance in the S3E (multiple wire bonds for example). All this is just guessing. You'd think you could get a straight answer from the horses mouth :-) Regards, GaborArticle: 141342
Is there a "set_dont_touch" equaivalent version of Xilinx Xst attribute. Or is it only in synopsys?.Article: 141343
Have you looked at: http://www.digilentinc.com/Data/Products/XUPV2P/xupv2p-sch.pdf ??? AustinArticle: 141344
On Jun 19, 8:41=A0am, austin <aus...@xilinx.com> wrote: > Have you looked at: > > http://www.digilentinc.com/Data/Products/XUPV2P/xupv2p-sch.pdf > > ??? > > Austin Looks like perhaps the schematic is incorrect if you see 2.5v on a pin in a bank whose Vcco is 3.3v! Should email Digilent... AustinArticle: 141345
"fl" <rxjwg98@gmail.com> wrote in message news:cb3c50e6-4af9-402e-b4ab-20395b0d0615@u10g2000vbd.googlegroups.com... > Hi, > My computer has Modelsim Altera web version installed. Now, I want to > use Xilinx tools (ISE 9.2i) with System Generator and Modelsim XE. For > the black box function, ModelsimXE always cannot work because it > installs altera, but not Xilinx, library after correctly call: > # Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl. > # Loading project NiosII_stratixII_2s60_standard_sim > > I exec ModelsimXE III 6.4b at the Windows Vista does not work in the > same way. > > > But, at the Xilinx ISE, Modelsim XE III works normal. > > Even though I uninstall ModelsimAE, the above problem still exists. Are you sure everything is deleted, in general files that have been modified (pref.tcl?) are not deleted. Is the Altera version still in your search path? Are you using an old Modelsim.ini file with library mappings pointing to the Altera ones? If you get completely stuck and can't fix it then after saving your registry do a search for: HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim and rename the modelsim entry to something else. This has helped me in the past when I changed some settings and couldn't get the original settings back (even after a re-install). When you restart Modelsim it should rebuild this entry. This worked for me on XP, I have no idea if this works on Vista though! Hans. www.ht-lab.com > Could you tell me which settings can correct that? Thanks,Article: 141346
Hi,
I have to instantiate (not inference) two FDRSE elements in my VHDL-
Code.
FDRSE1 should have active-high set/reset.
FDRSE2 should have active-low set/reset.
This is the instantiation code from the Libraries Guide:
FDRSE_inst : FDRSE
generic map (INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => Q, -- Data output
C => C, -- Clock input
CE => CE, -- Clock enable input
D => D, -- Data input
R => R, -- Synchronous reset input
S => S -- Synchronous set input
);
In this instantiation code, there is no possibility to configure the
set/reset polarity.
My two questions are:
1. How to instantiate a FDRSE with active-high set/reset
2. How to instantiate a FDRSE with active-low set/reset
Thanks in advance,
Mark Lenz
Article: 141347
skyworld wrote:
> In fact I can finish these jobs through GUI.
> But with GUI you can't do synthesis automatically.
What is the error message?
If the IP cores are the problem, talk to the vendor.
-- Mike Treseler
Article: 141348
On Fri, 19 Jun 2009 09:50:27 -0700 (PDT)
lenz19@gmx.de wrote:
> Hi,
>
> I have to instantiate (not inference) two FDRSE elements in my VHDL-
> Code.
>
> FDRSE1 should have active-high set/reset.
> FDRSE2 should have active-low set/reset.
>
> This is the instantiation code from the Libraries Guide:
>
> FDRSE_inst : FDRSE
> generic map (INIT => '0') -- Initial value of register ('0' or '1')
> port map (
> Q => Q, -- Data output
> C => C, -- Clock input
> CE => CE, -- Clock enable input
> D => D, -- Data input
> R => R, -- Synchronous reset input
> S => S -- Synchronous set input
> );
>
> In this instantiation code, there is no possibility to configure the
> set/reset polarity.
>
> My two questions are:
>
> 1. How to instantiate a FDRSE with active-high set/reset
> 2. How to instantiate a FDRSE with active-low set/reset
>
> Thanks in advance,
> Mark Lenz
>
1. You just did.
2. R => not R, S => not S
Out of curiosity, why would you need to be directly instantiating
flops? I've found very few situations where that's actually the right
answer (ripple counters, etc).
--
Rob Gaddi, Highland Technology
Email address is currently out of order
Article: 141349
On Jun 19, 10:49=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 19 Jun 2009 09:50:27 -0700 (PDT)
>
>
>
> len...@gmx.de wrote:
> > Hi,
>
> > I have to instantiate (not inference) two FDRSE elements in my VHDL-
> > Code.
>
> > FDRSE1 should have active-high set/reset.
> > FDRSE2 should have active-low =A0set/reset.
>
> > This is the instantiation code from the Libraries Guide:
>
> > FDRSE_inst : FDRSE
> > generic map (INIT =3D> '0') -- Initial value of register ('0' or '1')
> > port map (
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Q =A0 =A0=3D> Q, =A0 =A0 =A0-- Data=
output
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 C =A0 =A0=3D> C, =A0 =A0 =A0-- Cloc=
k input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CE =3D> CE, =A0 =A0-- Clock enable =
input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 D =A0 =3D> D, =A0 =A0 =A0-- Data in=
put
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 R =A0 =3D> R, =A0 =A0 =A0-- Synchro=
nous reset input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 S =A0 =3D> S =A0 =A0 =A0 -- Synchro=
nous set input
> > );
>
> > In this instantiation code, there is no possibility to configure the
> > set/reset polarity.
>
> > My two questions are:
>
> > 1. How to instantiate a FDRSE with active-high set/reset
> > 2. How to instantiate a FDRSE with active-low =A0set/reset
>
> > Thanks in advance,
> > Mark Lenz
>
> 1. You just did.
> 2. R =3D> not R, S =3D> not S
>
> Out of curiosity, why would you need to be directly instantiating
> flops? =A0I've found very few situations where that's actually the right
> answer (ripple counters, etc).
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order
I believe XST will not directly infer DDR output flops. At least it
didn't used to be
able to do this. I've always had to instantiate DDR output flops.
John Providenza
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