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Just implemented the shift-register reset. Worked like a champ! Thanks :) But I still want to know why the state machine didn't start in its initial state after configuration....Article: 143951
On Nov 4, 2:51=A0pm, ed <ed.agu...@gmail.com> wrote: > Just implemented the shift-register reset. Worked like a champ! > Thanks :) > > But I still want to know why the state machine didn't start in its > initial state after configuration.... A typical scenario is this: 1) Global Set & Reset is released at the end of configuration, asynchronous to any clock in the design and with variable delay throughout the device. 2) Your state machine is "released" from its initial state, one bit of the state variable at a time. If your clock is slow you might see the release of reset to all bits in the same clock period MOST of the time. 3) If not all bits start up at once, your next state can be different for different bits of the state variable. In the case of a one-hot state machine, this can lead to a zero-hot or multiple-hot state. The effects of asynchronous start-up is magnified when the the clock is at a higher speed and/or the state logic is placed over a large area of the device. Regards, GaborArticle: 143952
There are a lot of ways to achieve logic size reductions I have seen reductions of 30-50% on customer designs achieved here with a lot of expert knowledge but does depend on the original design. So starting with the some simple things: (1) Play with state machine encoding selection - changing a 1-hot to sequential can save a lot. (2) Play with speed and size settings. They don't always do exactly as the name suggests. (3) In the Xilinx mapping make sure you have setting to use i/o registers. (4) Consider SRL16 to replace shift register chains. Removing a reset term will often let the synthesiser do this for you. Can save a lot. Beyond these simply looking at how the design is implemented and restructuring can save more but that is a much more complex subject. Try the simple first as you don't need much. John Adair Enterpoint Ltd. - Home of Craignell. The DIL FPGA Module. On 4 Nov, 14:27, "bjzhan...@gmail.com" <bjzhan...@gmail.com> wrote: > Hi,recently,I receive a task to add another new function to the > project previously finished,but the problem is that the old project > have consume about 5K of total 7K LUTs,and the new function need about > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > someone give some advice about the logic optimization,the chip is > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1.Article: 143953
austin <austin@xilinx.com> wrote:
>All,
>
>I was puzzled that they used a push of the 65nm technology node (to
>60nm).
>
>It is a huge investment for a FPGA device company to launch a new
>family, and to launch one with "the old" technology node means that
>the latest technology node is guaranteed to beat you on price, power,
>and/or performance (since 90nm, we do not get to choose all three, we
>are at best a two out of three for a new node).
>
>True, S6 is optimized for power (first time we have ever used a low
>power process from a foundry), so bragging about performance is one
>way to shout very loudly "we sure burn a lot more power!"
>
>When we asked customers what their number one need was for S6, it was
>"lower the power!"
>
>I know that many like to use the latest Spartan node to replace the
>previous Virtex node (lower their bill of materials costs), but
>frankly, S6 was designed for a new markets, and not intended to
>cannibalize Virtex 5 sockets.
That raises the question: Can we expect to see a new Spartan series
with more speed?
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 143954On Nov 5, 12:58=A0am, n...@puntnl.niks (Nico Coesel) wrote: > austin <aus...@xilinx.com> wrote: > >All, > > >I was puzzled that they used a push of the 65nm technology node (to > >60nm). > > >It is a huge investment for a FPGA device company to launch a new > >family, and to launch one with "the old" technology node means that > >the latest technology node is guaranteed to beat you on price, power, > >and/or performance (since 90nm, we do not get to choose all three, we > >are at best a two out of three for a new node). > > >True, S6 is optimized for power (first time we have ever used a low > >power process from a foundry), so bragging about performance is one > >way to shout very loudly "we sure burn a lot more power!" > > >When we asked customers what their number one need was for S6, it was > >"lower the power!" > > >I know that many like to use the latest Spartan node to replace the > >previous Virtex node (lower their bill of materials costs), but > >frankly, S6 was designed for a new markets, and not intended to > >cannibalize Virtex 5 sockets. > > That raises the question: Can we expect to see a new Spartan series > with more speed? > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"If it doesn't fit, use a bigg= er hammer!" > -------------------------------------------------------------- i would like to see the spartan with ARM core first Xilinx should have inhouse silicon of it already if they are aiming to release it as planned AnttiArticle: 143955
On Wed, 04 Nov 2009 05:42:30 -0600, "gentel" <gentel86@163.com> wrote: >hi,all > >I am trying to target the XUP by Digilent with my big application. My >settings are almost there, but for some reason I get the following output: > >.. > >Address Map for Processor microblaze > (0x0000000-0x5fffffff) DDR_256MB_64Mx64_rank2_row13_col10_cl2_5 sopb > > (0x0000000-0x000ffff) dlmb_cntrl slmb > (0x0000000-0x000ffff) ilmb_cntrl slmb > (0x40600000-0x4060ffff) RS232_Uart_1 sopb > (0x41400000-0x4140ffff) debug module sopb > > ERROR:Data2MEM:33 - Matching ADDRESS_SPACE for code segment #4 not found >in 'sys >tem_stub_bd.bmm'. > Code segment #4 occupies [0x50000000:0x5002B357] >thanks for your help.. > At least three problems here: (1) you have mapped 1.5GB of address space onto 256MB of DDR memory. That'll work but may not do what you want. (2) Some of that space is also mapped onto peripherals. Reading from those regions will definitely not work. (3) DATA2MEM inserts data into the bitfile used to configure the FPGA. It follows that the memory being configured must be internal to the FPGA. Yet according to the address map it is mapped into the DDR module.. - BrianArticle: 143956
>On Wed, 04 Nov 2009 05:42:30 -0600, "gentel" <gentel86@163.com> wrote: >thanks for your reply,i got something wrong. the DDR memmory is (0x50000000-0x5fffffff).but,what should i do if i put the software and hardware bits into the board???? >>hi,all >> >>I am trying to target the XUP by Digilent with my big application. My >>settings are almost there, but for some reason I get the following output: >> >>.. >> >>Address Map for Processor microblaze >> (0x0000000-0x5fffffff) DDR_256MB_64Mx64_rank2_row13_col10_cl2_5 sopb >> >> (0x0000000-0x000ffff) dlmb_cntrl slmb >> (0x0000000-0x000ffff) ilmb_cntrl slmb >> (0x40600000-0x4060ffff) RS232_Uart_1 sopb >> (0x41400000-0x4140ffff) debug module sopb >> >> ERROR:Data2MEM:33 - Matching ADDRESS_SPACE for code segment #4 not found >>in 'sys >>tem_stub_bd.bmm'. >> Code segment #4 occupies [0x50000000:0x5002B357] >>thanks for your help.. >> > >At least three problems here: >(1) you have mapped 1.5GB of address space onto 256MB of DDR memory. That'll >work but may not do what you want. > >(2) Some of that space is also mapped onto peripherals. Reading from those >regions will definitely not work. > >(3) DATA2MEM inserts data into the bitfile used to configure the FPGA. It >follows that the memory being configured must be internal to the FPGA. Yet >according to the address map it is mapped into the DDR module.. > >- Brian > --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.comArticle: 143957
On Nov 5, 12:04=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > i would like to see the spartan with ARM core first > Xilinx should have inhouse silicon of it already if they are aiming to > release it as planned Triscend revisited ? A key question is not the core, but what memory they put around it ? Plenty of ARM cores out there, that have memory included (they are called Microcontrollers!) - and the choice is growing. -jgArticle: 143958
On Nov 5, 7:25=A0am, -jg <jim.granvi...@gmail.com> wrote: > On Nov 5, 12:04=A0pm, Antti <antti.luk...@googlemail.com> wrote: > > > > > i would like to see the spartan with ARM core first > > Xilinx should have inhouse silicon of it already if they are aiming to > > release it as planned > > Triscend revisited ? > > A key question is not the core, but what memory they put around it ? > > Plenty of ARM cores out there, that have memory included > (they are called Microcontrollers!) =A0- and the choice is growing. > > -jg well ARM+CPLD is again announced now too, its called PSoC 5 cortex-M3 + small CPLD AnttiArticle: 143959
Hi, you did not mentioned how much resources is consumed if you compile the new design. Sometimes the sythesis and p&r tools are able to do wanderfull optimalizations jobs. So I would suggest (maybe you have already done), that you first implement the design and look if the constraints are met. If not, than I would try to use PlanAhead or something to run several optimalization strategies through night to see if map and par will be able to do the job. Do not forget about alowing the global optimalization in the map. Also remember that p&r works little differently on the full designs and on the designs with a free. So it is not true that 5+2.5 = 7.5A Jan On Wed, 4 Nov 2009, bjzhangwn@gmail.com wrote: > Hi,recently,I receive a task to add another new function to the > project previously finished,but the problem is that the old project > have consume about 5K of total 7K LUTs,and the new function need about > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > someone give some advice about the logic optimization,the chip is > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1. >Article: 143960
"bjzhangwn@gmail.com" <bjzhangwn@gmail.com> writes: > Hi,recently,I receive a task to add another new function to the > project previously finished,but the problem is that the old project > have consume about 5K of total 7K LUTs,and the new function need about > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > someone give some advice about the logic optimization,the chip is > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1. If you are unfamiliar with the project, it can help to know which parts of the current design are using the most resources, so you know where to target your optimisations. I wrote a tool to help with visualising this (for a design I had to chop in half to fit the new stuff in). You can read about it here: http://www.conekt.net/fpgaoptim.html Drop me an email if you want a download link... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 143961
both free samples and 49$ starterkit available, my should be airborn right now somewhere between Paris and my place. The CPLD is small, 190MC, but it still much more then the 16MC availabel in ADI's ADuCs or ST's uPSD devices. PSoC 5, Cortex based devices will probably only be available next year AnttiArticle: 143962
>I was puzzled that they used a push of the 65nm technology node (to > 60nm). > It is a huge investment for a FPGA device company to launch a new > family, and to launch one with "the old" technology node means that > the latest technology node is guaranteed to beat you on price, power, > and/or performance (since 90nm, we do not get to choose all three, we > are at best a two out of three for a new node). TSMCs problems at 40nm are pretty well documented. Cheers, JonArticle: 143963
On Wed, 04 Nov 2009 19:14:12 -0600, "gentel" <gentel86@163.com> wrote: >>On Wed, 04 Nov 2009 05:42:30 -0600, "gentel" <gentel86@163.com> wrote: >>thanks for your reply,i got something wrong. the DDR memmory is >(0x50000000-0x5fffffff).but,what should i do if i put the software and >hardware bits into the board???? what do you mean by putting bits into the board? If you mean loading the DDR memory with this code segment after power-up, the usual approach is to write a bootstrap loader - which has to be mapped into internal memory - which loads this segment from non-volatile storage (e.g. flash memory, or possibly Ethernet or even the UART. Alternatively, map this entire segment into internal memory, if there is enough memory. Or re-write it to use less space. - BrianArticle: 143964
Torfinn Ingolfsen wrote: > Antti wrote: >> Hi >> >> Altera is promising 25% more fabric speed than S6 with their new >> Cyclone IV > > And us hobbyist types are wondering: will Altera give us a _free_ > development environment for Linux this time? > (just in case anyone from Altera drops in here occasionally). There's a beta version available (I haven't tried it - I just noticed it on their web site when wandering about).Article: 143965
David Brown <david@westcontrol.removethisbit.com> wrote: > Torfinn Ingolfsen wrote: > > Antti wrote: > >> Hi > >> > >> Altera is promising 25% more fabric speed than S6 with their new > >> Cyclone IV > > > > And us hobbyist types are wondering: will Altera give us a _free_ > > development environment for Linux this time? > > (just in case anyone from Altera drops in here occasionally). > There's a beta version available (I haven't tried it - I just noticed it > on their web site when wandering about). Any link (if you talk about a Linux version of Quartus II Web Edition Software) A search for linux "web edition" on the Altera site brings some hits, but I didn't see something downloadable... Thanks -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 143966
On Nov 5, 11:55=A0am, Kastil Jan <ikas...@stud.fit.vutbr.cz> wrote: > Hi, > you did not mentioned how much resources is consumed if you compile the > new design. Sometimes the sythesis and p&r tools are able to do wanderful= l > optimalizations jobs. So I would suggest (maybe you have already done), > that you first implement the design and look if the constraints are met. > If not, than I would try to use PlanAhead or something to run several > optimalization strategies through night to see if map and par will be abl= e > to do the job. Do not forget about alowing the global optimalization in > the map. > > Also remember that p&r works little differently on the full designs and o= n > the designs with a free. So it is not true that 5+2.5 =3D 7.5A > > Jan > > =A0 On Wed, 4 Nov 2009, bjzhan...@gmail.com wrote: > > > Hi,recently,I receive a task to add another new function to the > > project previously finished,but the problem is that the old project > > have consume about 5K of total 7K LUTs,and the new function need about > > 2.5K LUTs,so I must optimize the old logic but I have no idea,can > > someone give some advice about the logic optimization,the chip is > > spartan3,the synthesis tool is synplify9.4 pro,P&R tool is 10.1. I agree with Jan. I have experienced this. Many times the Slices were not fully used. So, the additional logics can use the existing slice and the overall resource count will be less than 7.5K.Article: 143967
Hello! I am trying to use partial reconfiguration to change the contents of BRAM belonging to USER IP. I am able to read the BRAM FRAME, but not able to write (details about frame contents below). XPS 10.1 (lin64) OPB_HWICAP 1.10a, FPGA Virtex 4(xc4vlx25) Here is the example: Buffer after frame read: XHwIcap_DeviceReadFrameV4(&hwicap,1,2,2,1,0); Target BRAM content was initialized with all 1s. Which can be seen from buffer words 93 to 102. So the buffer is read ok! NO| Buffer word contents 0 30008001 1 0000000d 2 ffffffff 3 ffffffff 4 30008001 5 00000007 6 20000000 7 20000000 8 30008001 9 00000004 10 20000000 11 20000000 12 20000000 13 30002001 14 00508041 15 28006053 16 20000000 17 20000000 18 00000000 19 00000000 . . . 72 49cf8943 73 fa0eebe8 74 c20eb84d 75 63db694d 76 0000991d 77 4d938a80 78 e6e4cf41 79 df21db17 80 55d627a6 81 0070978d 82 00000000 83 49cf8943 84 fa0eebe8 85 c20eb84d 86 63db694d 87 0000991d 88 4d938a80 89 e6e4cf41 90 df21db17 91 55d627a6 92 0070978d 93 ffffffff 94 ffffffff 95 ffffffff 96 ffffffff 97 0000ffff 98 ffffff80 99 ffffffff 100 ffffffff 101 ffffffff 102 00ffffff 103 00000000 For example that I want to change one word of BRAM contents I changed word 99 to of the frame buffer to 0f0f0f0f. Buffer after frame write XHwIcap_DeviceWriteFrameV4(&hwicap,1,2,2,1,0); 0 30008001 1 0000000d 2 ffffffff 3 ffffffff 4 30000001 5 0000defc 6 20000000 7 20000000 8 30012001 9 10042fdd 10 30018001 11 0167c093 12 30002001 13 00508041 14 30008001 15 00000001 16 20000000 17 30004052 18 00000000 19 00000000 . . . 72 49cf8943 73 fa0eebe8 74 c20eb84d 75 63db694d 76 0000991d 77 4d938a80 78 e6e4cf41 79 df21db17 80 55d627a6 81 0070978d 82 00000000 83 49cf8943 84 fa0eebe8 85 c20eb84d 86 63db694d 87 0000991d 88 4d938a80 89 e6e4cf41 90 df21db17 91 55d627a6 92 0070978d 93 ffffffff 94 ffffffff 95 ffffffff 96 ffffffff 97 0000ffff 98 ffffff80 99 0f0f0f0f 100 ffffffff 101 ffffffff 102 00ffffff 103 00000000 Now I want to check if the word 99 is realy reconfigured i read the same frame again. Buffer after frame read: XHwIcap_DeviceReadFrameV4(&hwicap,1,2,2,1,0); 0 30008001 1 0000000d 2 ffffffff 3 ffffffff 4 30008001 5 00000007 6 20000000 7 20000000 8 30008001 9 00000004 10 20000000 11 20000000 12 20000000 13 30002001 14 00508041 15 28006053 16 20000000 17 20000000 18 00000000 . . . 72 49cf8943 73 fa0eebe8 74 c20eb84d 75 63db694d 76 0000991d 77 4d938a80 78 e6e4cf41 79 df21db17 80 55d627a6 81 0070978d 82 00000000 83 49cf8943 84 fa0eebe8 85 c20eb84d 86 63db694d 87 0000991d 88 4d938a80 89 e6e4cf41 90 df21db17 91 55d627a6 92 0070978d 93 ffffffff 94 ffffffff 95 ffffffff 96 ffffffff 97 0000ffff 98 ffffff80 99 ffffffff 100 ffffffff 101 ffffffff 102 00ffffff 103 00000000 The word 99 was not configured!!! I tried to reconfigure LUT contents in the same way and succeeded. Maybe my bitgen options are incorect, or BRAM content is protected? BITGEN: -b -g ActiveReconfig:Yes -g CclkPin:PULLUP -g TdoPin:PULLNONE -g M1Pin:PULLUP -g DonePin:PULLUP -g DriveDone:No -g StartUpClk:JTAGCLK -g DONE_cycle:4 -g GTS_cycle:5 -g M0Pin:PULLUP -g M2Pin:PULLUP -g ProgPin:PULLUP -g TckPin:PULLUP -g TdiPin:PULLUP -g TmsPin:PULLUP -g DonePipe:No -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:NONE #-m -g Persist:No Hope to get some answers, LegatArticle: 143968
Jon, Yes, TSMC is having some yield issues (at 45/40nm). But, yield issues comes "with the territory." It isn't the first time, and it won't be the last time. In IC Design, the choice of technology was made three years ago, so yield was not a factor in the choice for C4. Ranting about a yield issue is not good for business, as you never know who might be next, and it isn't anyone at Altera's fault that TSMC has those issues (for the moment). Oh, I like that: C4! Like the powerful explosive... the FPGA guaranteed to make a bang! I digress. Back to idle speculation. I believe that Altera was faced with our release of S6, both with and without transceivers, and realized they needed something in order to compete. It did not take a rocket scientist to see where the low cost FPGA families would have transceivers in the future three years ago. AustinArticle: 143969
Uwe Bonnes wrote: > David Brown <david@westcontrol.removethisbit.com> wrote: >> Torfinn Ingolfsen wrote: >>> Antti wrote: >>>> Hi >>>> >>>> Altera is promising 25% more fabric speed than S6 with their new >>>> Cyclone IV >>> And us hobbyist types are wondering: will Altera give us a _free_ >>> development environment for Linux this time? >>> (just in case anyone from Altera drops in here occasionally). > >> There's a beta version available (I haven't tried it - I just noticed it >> on their web site when wandering about). > > Any link (if you talk about a Linux version of Quartus II Web Edition Software) > > A search for linux "web edition" on the Altera site brings some hits, but I > didn't see something downloadable... > > Thanks Follow the links for downloading the web edition of quartus: <https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp> I'm not working on FPGA development at the moment, but I like to keep track of what's new. If you try out the software, it would be nice to hear in this newsgroup how it goes. mvh., DavidArticle: 143970
Agreed, but the design I'm implementing is a Physically Unclonable Function, which specifically calls for a ring oscillator. -Sam Kerr On Tue, 3 Nov 2009, Rob Gaddi wrote: > On Mon, 2 Nov 2009 09:20:45 -0500 > Sam Kerr <stkerr@purdue.edu> wrote: > >> [snip a ring oscillator] > > You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum > total < $0.10 in quantity), you could have a much easier to work with > clock source. > > -- > Rob Gaddi, Highland Technology > Email address is currently out of order >Article: 143971
David Brown wrote: > Follow the links for downloading the web edition of quartus: > > <https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp> Ah! Thanks! Downloading as I write this. I run Ubuntu (which is not on the supported os list), but I'll try anyway and report how it goes. > I'm not working on FPGA development at the moment, but I like to keep > track of what's new. If you try out the software, it would be nice to > hear in this newsgroup how it goes. If it works in Ubuntu at all, I'll try it out to see how it works. -- Torfinn Ingolfsen, NorwayArticle: 143972
On Nov 5, 7:43=A0pm, Sam Kerr <stk...@purdue.edu> wrote: > Agreed, but the design I'm implementing is a Physically Unclonable > Function, which specifically calls for a ring oscillator. > > -Sam Kerr > > > > On Tue, 3 Nov 2009, Rob Gaddi wrote: > > On Mon, 2 Nov 2009 09:20:45 -0500 > > Sam Kerr <stk...@purdue.edu> wrote: > > >> [snip a ring oscillator] > > > You know, for one pin, a tinylogic schmitt trigger, an R, and a C (sum > > total < $0.10 in quantity), you could have a much easier to work with > > clock source. > > > -- > > Rob Gaddi, Highland Technology > > Email address is currently out of order wau, a real PUF designer! :) and how is it looking? There are plenty of tricks possible, but i bet its not so easy to make it really reliable AnttiArticle: 143973
On Nov 5, 6:06=A0pm, austin <aus...@xilinx.com> wrote: > Jon, > > Yes, TSMC is having some yield issues (at 45/40nm). =A0But, yield issues > comes "with the territory." =A0It isn't the first time, and it won't be > the last time. =A0In IC Design, the choice of technology was made three > years ago, so yield was not a factor in the choice for C4. > > Ranting about a yield issue is not good for business, as you never > know who might be next, and it isn't anyone at Altera's fault that > TSMC has those issues (for the moment). > > Oh, I like that: =A0C4! Like the powerful explosive... =A0the FPGA > guaranteed to make a bang! > > I digress. =A0Back to idle speculation. > > I believe that Altera was faced with our release of S6, both with and > without transceivers, and realized they needed something in order to > compete. =A0It did not take a rocket scientist to see where the low cost > FPGA families would have transceivers in the future three years ago. > > Austin I was wondering who brings out the "explosiveness" of the new cyclones :) well, for the moment Spartan-6 looks better than C4 as there is better choice of packages as Altera is no longer offering 8x8 mm packages, Xilinx had no 8x8 in S3A what was a mistake but Xilinx has re-introduced 8x8 packages in S6 again sure, what is fun is the QFN148 packaged for Serdes enabled Cyclone, I would love to see S6 QFN68 with serdes :) AnttiArticle: 143974
"Sam Kerr" <stkerr@purdue.edu> wrote in message news:alpine.WNT.2.00.0911020916180.1072@stkerr-Vista... > I'm trying to create a ring oscillator for my FPGA design but I've run > into some problems. Namely, it doesn't seem like any oscillation is > occurring. I've hooked up the output signal to LEDs and the serial port, > but neither of these shows any oscillations. > Here you might find useful reference design: A. Maiti, R. Nagesh, A. Reddy, P. Schaumont, "Physical Unclonable Function and True Random Number Generator: a Compact and Scalable Implementation," 19th Great Lakes Symposium on VLSI (GLSVLSI 2009), May 2009. http://rijndael.ece.vt.edu/schaum/papers/2009glsvlsi.pdf > > A few things I think might be happening is that the oscillation is so fast > I just can't see it, the oscillation is too fast for the board, it's > getting optimized out during synthesis, or (probably) my Verilog file is > implemented incorrectly. > Constraining inverter's output signals with 'KEEP' attribute will do the job. Also, the oscillation frequency for 3 INVs can reach 450-500MHz (when implemented in V5). Regards, Krzysztof
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