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lolita.tangier@gmail.com wrote:
> I have a SoC and I will be able to Synthesize and implement it in the
> FPGA ( Spartan 3).
> now, I want to send a sequence of bytes to the FPGA (Spartan 3) for
> test a Soc that I have implement in this fpga, but I don=92t know if
> there is a way to send from ISE Xilinx to the FPGA.
I would send the bytes first in simulation.
-- Mike Treseler
Article: 140851On May 27, 12:37=A0am, Petter Gustad <newsmailco...@gustad.com> wrote: > Andreas Ehliar <ehliar-nos...@isy.liu.se> writes: > > It is straight forward in Verilog as well. This is taken from an Ethern= et > > CRC32 module I wrote a long time ago: > > <snipped code> > > But that's not any poly at any length... Andreas's code snippet shows the point fairly well. It's not hard to expand his to have "polynomial" as an input to the module as well, and the data length and polynomial length as parameters. It's much easier to read his and understand what's happening - for me at least. Without comments, one can puzzle out the polynomial, and other CRC parameters fairly easily from the code. Try that with the machine generated code. I've inherited machine generated code like these in the past a few times. Comments are great, but often get out of date / incomplete / etc. Next design, we need to match the CRC in software for some reason. "What's the polynomial?" the SW engineer asks. "I dunno." HW guy replies, "So-and-so ran some tool on the net, and out popped this code...". --MarkArticle: 140852
On May 26, 1:13=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 26, 2:58 pm, Andy Peters <goo...@latke.net> wrote: > > > > > On May 26, 7:46 am, jleslie48 <j...@jonathanleslie.com> wrote: > > > > On May 22, 8:23 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 22, 5:55 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > > On Fri, 22 May 2009 14:20:59 -0700 (PDT), jleslie48 > > > > > > <j...@jonathanleslie.com> wrote: > > > > > >On May 22, 5:26 pm, doug <x...@xx.com> wrote: > > > > > > >> Only FFs have reset. > > > > > > >that doesn't mean anything to me. =A0maybe I inlcuded too much c= ode in > > > > > >the snippet, =A0the only part of the code > > > > > >that is causing the issue I believe is this: > > > > > > >----------------------------------------------------------------= ------------------- > > > > > > =A0 type reg_file_type is array (2**W-1 downto 0) of > > > > > > =A0 =A0 =A0 =A0std_logic_vector(B-1 downto 0); > > > > > > =A0 signal array_reg: reg_file_type; > > > > > >----------------------------------------------------------------= ------------------- > > > > > > >the error message in question has no issue with the reset. =A0it= s > > > > > >complaining about <array_reg> > > > > > > The "warning" is just telling you that it couldn't map your "arra= y" to > > > > > memory. Doug has said the reason that couldn't be done probably w= as > > > > > that you have some code which says: > > > > > > if (reset) > > > > > array <=3D 0 > > > > > > or something similar. As "only ffs have reset" this "array" can't= be > > > > > mapped to memory. If you have code like this, remove it, add an > > > > > initial statement to clear array instead and try again. > > > > > -- > > > > > Muzaffer Kal > > > > > > DSPIA INC. > > > > > ASIC/FPGA Design Services > > > > > >http://www.dspia.com > > > > > Thank you, that makes sense. =A0I'll have to check. > > > > C:\jon\fpga_uartjl_01\Pchu_cc02\ms_d04\source>grep -in -B3 -A3 > > > array_reg fifo.vhd > > > > 23-architecture arch of fifo is > > > 24- =A0 type reg_file_type is array (2**W-1 downto 0) of > > > 25- =A0 =A0 =A0 =A0std_logic_vector(B-1 downto 0); > > > 26: =A0 signal array_reg: reg_file_type; > > > 27- =A0 signal w_ptr_reg, w_ptr_next, w_ptr_succ: > > > 28- =A0 =A0 =A0std_logic_vector(W-1 downto 0); > > > 29- =A0 signal r_ptr_reg, r_ptr_next, r_ptr_succ: > > > -- > > > 39- =A0 process(clk,reset) > > > 40- =A0 begin > > > 41- =A0 =A0 if (reset=3D'1') then > > > 42: =A0 =A0 =A0 =A0array_reg <=3D (others=3D>(others=3D>'0')); > > > 43- =A0 =A0 elsif (clk'event and clk=3D'1') then > > > 44- =A0 =A0 =A0 =A0if wr_en=3D'1' then > > > 45: =A0 =A0 =A0 =A0 =A0 array_reg(to_integer(unsigned(w_ptr_reg))) > > > 46- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 <=3D w_data; > > > 47- =A0 =A0 =A0 =A0end if; > > > 48- =A0 =A0 end if; > > > 49- =A0 end process; > > > 50- =A0 -- read port > > > 51: =A0 r_data <=3D array_reg(to_integer(unsigned(r_ptr_reg))); > > > 52- =A0 -- write enabled only when FIFO is not full > > > 53- =A0 wr_en <=3D wr and (not full_reg); > > > 54- > > > > Ok, so here's all the code pertaining to array_reg, specifically line= s > > > 42, 45, and 51. =A0From what I can understand, it seems that the > > > professionals here are concerned about line 42; the one resulting fro= m > > > the reset signal. =A0What would be the correct way to implement this > > > concept? > > > Simply delete the asynchronous reset stuff in lines 41 and 42, and > > change the "elsif" on line 43 to a simple "if." > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_reg)) > > > but we ain't in C world any more... > > > Indeed -- think HARDWARE. > > > Since you are describing a FIFO, there's no need to reset the memory. > > Simply resetting the read and write pointers effectively clears the > > memory. You will never read from an empty FIFO and a FIFO write > > guarantees that you read valid data. > > > -a > > quite right, > > the other process has: > =A0 process(clk,reset) > =A0 =A0begin > =A0 =A0 =A0 if (reset=3D'1') then > =A0 =A0 =A0 =A0 =A0w_ptr_reg <=3D (others=3D>'0'); > =A0 =A0 =A0 =A0 =A0r_ptr_reg <=3D (others=3D>'0'); > =A0 =A0 =A0 =A0 =A0full_reg <=3D '0'; > =A0 =A0 =A0 =A0 =A0empty_reg <=3D '1'; > > and as my pointers get reset who cares about the data. =A0System > resources went dramatically down as a result of the changes, I'm glad the suggestion worked for you! > however > two warnings are now being generated that were never there before: > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing > resources. If you are trying to use local clocking techniques, > evaluate the placement of the clock's source and loads to ensure it > meets the guidelines for local clocking. Otherwise, consider placing > this clock on a dedicated clock routing resource. For more information > on clock routing resources, see the target architecture's user guide. > > WARNING Route - CLK Net:clk_7812hz is being routed on general routing > resources. If you are trying to use local clocking techniques, > evaluate the placement of the clock's source and loads to ensure it > meets the guidelines for local clocking. Otherwise, consider placing > this clock on a dedicated clock routing resource. For more information > on clock routing resources, see the target architecture's user guide. > > I can't imagine why these are showing up as a result of "fixing" the > other error. Sounds like the clock signals are coming into the FPGA on non-clock pins. You probably didn't see this error before because the original warnings/complaints were issued by XST (the synthesis tool) and you went no further. Now that the source synthesizes, the place and route tools take over, and the warning you get is issued by the router. Check your UCF and pin selection. -aArticle: 140853
hi
I know $memreadh, $memreadb are used to read data from a text file. I
have used a memory file for reading data.
reg [0:7] mem[1:500];
initial
$memreadh("input.mem", mem);
In this case, .mem file is created in Xilinx ISE only. But, if I want
to use .txt or .dat files, what is the syntax.
I mean, we should give any path to a file whre it is stored. If so,
tell me whre the file should be saved. I am usign Xilinx Ise. So,
should it be saved in xilinx ise installation files??
Similarly, what is the verilog command for writing data to a text
file.
what is the difference between fread and $memreadh??
Will the module programs with $memreadh, $memreadb, fread, fwrite
tasks be synthesized??
Please let me know these anss.
Thanks
Article: 140854Hi, I didn't find any information concerning cyclone3 device and other serial flash connection thant the Altera ones. I would like to implement a cyclone3 FPGA with an AT45DB serial flash but find nowhere some explanation on this point. Does anybody already try to do this? or does anybody have a paper on this? THanks in advance NadArticle: 140855
How precise do you need to be? What other clocks do you have in the system? /Mikhail "jleslie48" <jon@jonathanleslie.com> wrote in message news:3848ac2e-9bc7-48f4-9fa0-5ca327a44c8a@r34g2000vbi.googlegroups.com... > on a spartan 3e, the DCM speaks to havein a high-resolution phase > shifting function, but it goes on and says the DCM has a wide > frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > locked? > > The idea is this, I have a 2MHz signal coming in on a pin, and I want > to mimic that signal on an internal std_logic pin with the idea that > if the 2MHz signal on the incoming pin is ever lost, the internal > std_logic pin continues the original timing as if nothing has > happened. > > Any suggestions? >Article: 140856
On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 <jon@jonathanleslie.com> wrote: >on a spartan 3e, the DCM speaks to havein a high-resolution phase >shifting function, but it goes on and says the DCM has a wide >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase >locked? > >The idea is this, I have a 2MHz signal coming in on a pin, and I want >to mimic that signal on an internal std_logic pin with the idea that >if the 2MHz signal on the incoming pin is ever lost, the internal >std_logic pin continues the original timing as if nothing has >happened. > >Any suggestions? Implement your own NCO. Basically run a high resolution counter with high speed clock and detect at which count the 2MHz signal is toggling (both edges if need be) and generate an internal signal at the same count. Now even if the external signal disappears you have the count (phase) already and you can keep generating the internal signal. You can use this internal signal either as a clock source (ie a divided clock) or as an enable to its downstream logic. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 140857
hi
module test_readmemory(
);
reg [0:7] mem [1:30];
initial
$readmemb("memory.mem",mem);
always @(mem)
$display("mems= %b,%b,%h,%h", mem[1],mem[10],mem[15],mem[30]);
endmodule
The file memory.mem contains these data
209
210
211
211
212
212
212
211
211
212
213
213
213
213
213
212
213
213
213
213
212
213
212
212
212
213
212
211
211
211 While simulating this design in xilinx ise, some times I am
getting error "ERROR:Simulator - Failed to link the design. Check to
see if any previous simulation executables are still running."
what is this error. how to eliminate it.
and sometimes I am getting outputs 8'h09, 8'h12, 8'h13, 8'h11
In the input file, mem[1] = 209 but output i am getting is 8'h09
mem[10]=212 but output iam getting is 8'12
similarly mem[15] and mem[30].
8 binary numbers are sufficient to represent upto 256. But, why I am
getting like this??
Please let me know asap
thanks
Article: 140858Hi, I have just published the code, which accesses the Virtual JTAG instances in the Altera FPGAs, in the fully Open Source environment (Python+urJTAG). The archive is available here: http://groups.google.pl/group/alt.sources/browse_thread/thread/58acd8b31ea5bd0d It contains the Python code, and the simple VHDL code, which allows just enumeration of the Virtual JTAG instances, and then blinking the leds via the JTAG DR register... However this code may be easily extended to more serious things... I hope that someone may find it usefull. -- BR, WojtekArticle: 140859
Mark wrote: > On May 27, 12:37 am, Petter Gustad <newsmailco...@gustad.com> wrote: >> Andreas Ehliar <ehliar-nos...@isy.liu.se> writes: >>> It is straight forward in Verilog as well. This is taken from an Ethernet >>> CRC32 module I wrote a long time ago: >> <snipped code> >> >> But that's not any poly at any length... > > Andreas's code snippet shows the point fairly well. It's > not hard to expand his to have "polynomial" as an input to > the module as well, and the data length and polynomial length > as parameters. > > It's much easier to read his and understand what's happening - > for me at least. Without comments, one can puzzle out the > polynomial, and other CRC parameters fairly easily from the code. > Try that with the machine generated code. Automatically generated comments should be just fine. However, there's no need to put the two approaches against each other like that. If synthesis tools were ideal, there would be no need for a tool such as Easics' CRC Tool. It was developed in the mid 90s because we found that the for-loop approach caused large synthesis run-times and inefficient results in cases like: * wide polynomials * wide data widths * CRC embedded in a large FSM What CRC Tool actually does is a dedicated XOR-based optimization. The synthesis improvements were quite dramatic. Whether this is still the case, and for which synthesis tools, I don't know. I can imagine that some synthesis tools contain specific XOR-based optimization engines by now, which would possibly remove the need for CRC Tool. It all comes down to understanding the capabilities of your synthesis tool. Jan -- Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com Python as a HDL: http://www.myhdl.org VHDL development, the modern way: http://www.sigasi.com Analog design automation: http://www.mephisto-da.com World-class digital design: http://www.easics.comArticle: 140860
On May 27, 11:21=A0am, "PrAsHaNtH@IIT" <prashaena...@gmail.com> wrote:
> hi
>
> module test_readmemory(
> =A0 =A0 );
>
> reg [0:7] mem [1:30];
> initial
> $readmemb("memory.mem",mem);
>
> always @(mem)
> $display("mems=3D %b,%b,%h,%h", mem[1],mem[10],mem[15],mem[30]);
> endmodule
>
> The file memory.mem contains these data
> 209
> 210
> 211
> 211
> 212
> 212
> 212
> 211
> 211
> 212
> 213
> 213
> 213
> 213
> 213
> 212
> 213
> 213
> 213
> 213
> 212
> 213
> 212
> 212
> 212
> 213
> 212
> 211
> 211
> 211 =A0 =A0While simulating this design in xilinx ise, some times I am
> getting error "ERROR:Simulator - Failed to link the design. Check to
> see if any previous simulation executables are still running."
> =A0what is this error. how to eliminate it.
>
> and sometimes I am getting outputs 8'h09, 8'h12, 8'h13, 8'h11
> In the input file, mem[1] =3D 209 but output i am getting is 8'h09
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mem[10]=3D212 but output i=
am getting is 8'12
> similarly =A0 =A0 =A0 =A0 =A0mem[15] and mem[30].
>
> 8 binary numbers are sufficient to represent upto 256. But, why I am
> getting like this??
>
> Please let me know asap
>
> thanks
You need to look at the file format required by $readmemh and
$readmemb. As you might guess,
one reads hex values, the other reads binary values.
I can't help you with the Xilinx simulation error - I don't use that
simulator.
John Providenza
Article: 140861On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > <j...@jonathanleslie.com> wrote: > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > >shifting function, but it goes on and says the DCM has a wide > >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > >locked? > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > >to mimic that signal on an internal std_logic pin with the idea that > >if the 2MHz signal on the incoming pin is ever lost, the internal > >std_logic pin continues the original timing as if nothing has > >happened. > > >Any suggestions? > > Implement your own NCO. Basically run a high resolution counter with > high speed clock and detect at which count the 2MHz signal is toggling > (both edges if need be) and generate an internal signal at the same > count. Now even if the external signal disappears you have the count > (phase) already and you can keep generating the internal signal. You > can use this internal signal either as a clock source (ie a divided > clock) or as an enable to its downstream logic. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.com as I've been thinking about this today I also thought to forget the DCM and just do it with the regular system clock. The main system clock will be anywhere between 25-100MHZ, and for that matter, the 25MHz can be 4X with the DCM. so now the issue is on the rising edge of the inbound 2MHz clock have the internal 2mhz clock count off 50 ticks of the 100MHz clock to do my best "phase lock"Article: 140862
On May 27, 12:51 pm, Andy Peters <goo...@latke.net> wrote: > On May 26, 1:13 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > > > 23-architecture arch of fifo is > > > > 24- type reg_file_type is array (2**W-1 downto 0) of > > > > 25- std_logic_vector(B-1 downto 0); > > > > 26: signal array_reg: reg_file_type; > > > > 27- signal w_ptr_reg, w_ptr_next, w_ptr_succ: > > > > 28- std_logic_vector(W-1 downto 0); > > > > 29- signal r_ptr_reg, r_ptr_next, r_ptr_succ: > > > > -- > > > > 39- process(clk,reset) > > > > 40- begin > > > > 41- if (reset='1') then > > > > 42: array_reg <= (others=>(others=>'0')); > > > > 43- elsif (clk'event and clk='1') then > > > > 44- if wr_en='1' then > > > > 45: array_reg(to_integer(unsigned(w_ptr_reg))) > > > > 46- <= w_data; > > > > 47- end if; > > > > 48- end if; > > > > 49- end process; > > > > 50- -- read port > > > > 51: r_data <= array_reg(to_integer(unsigned(r_ptr_reg))); > > > > 52- -- write enabled only when FIFO is not full > > > > 53- wr_en <= wr and (not full_reg); > > > > 54- > > > > > Ok, so here's all the code pertaining to array_reg, specifically lines > > > > 42, 45, and 51. From what I can understand, it seems that the > > > > professionals here are concerned about line 42; the one resulting from > > > > the reset signal. What would be the correct way to implement this > > > > concept? > > > > Simply delete the asynchronous reset stuff in lines 41 and 42, and > > > change the "elsif" on line 43 to a simple "if." > > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_reg)) > > > > but we ain't in C world any more... > > > > Indeed -- think HARDWARE. > > > > Since you are describing a FIFO, there's no need to reset the memory. > > > Simply resetting the read and write pointers effectively clears the > > > memory. You will never read from an empty FIFO and a FIFO write > > > guarantees that you read valid data. > > > > -a > > > quite right, > > > the other process has: > > process(clk,reset) > > begin > > if (reset='1') then > > w_ptr_reg <= (others=>'0'); > > r_ptr_reg <= (others=>'0'); > > full_reg <= '0'; > > empty_reg <= '1'; > > > and as my pointers get reset who cares about the data. System > > resources went dramatically down as a result of the changes, > > I'm glad the suggestion worked for you! > > > > > however > > two warnings are now being generated that were never there before: > > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing > > resources. If you are trying to use local clocking techniques, > > evaluate the placement of the clock's source and loads to ensure it > > meets the guidelines for local clocking. Otherwise, consider placing > > this clock on a dedicated clock routing resource. For more information > > on clock routing resources, see the target architecture's user guide. > > > WARNING Route - CLK Net:clk_7812hz is being routed on general routing > > resources. If you are trying to use local clocking techniques, > > evaluate the placement of the clock's source and loads to ensure it > > meets the guidelines for local clocking. Otherwise, consider placing > > this clock on a dedicated clock routing resource. For more information > > on clock routing resources, see the target architecture's user guide. > > > I can't imagine why these are showing up as a result of "fixing" the > > other error. > > Sounds like the clock signals are coming into the FPGA on non-clock > pins. You probably didn't see this error before because the original > warnings/complaints were issued by XST (the synthesis tool) and you > went no further. Now that the source synthesizes, the place and route > tools take over, and the warning you get is issued by the router. > > Check your UCF and pin selection. > > -a H'mmm, I checked the place and route report before and after the change in code. the Warnings are definitely not there when the 256 flip-flop warning is in place. I'll have to take a look at the UCF and see what can be done with the pins I'm using. I'm a bit confused about that, I thought GPIO is GPIO, I'm sending in a signal, and that's it, but I know that there is a document out there from Xilinx (how they love their documents) that says something about the pins... lets me check and see what I can find.Article: 140863
Fixed the last things I could find. Version R. 79MHz 641 LEs. Can you see anymore errors? I am imagining error which are not there. cheers jacko p.s. could any spotted errors be forwarded to me asap.Article: 140864
On May 21, 5:53=A0pm, David Antliff <david.antl...@gmail.com> wrote: > Let me try and describe the issue fully. A quick followup for this. After consulting with someone at Xilinx, it's clear that the .ngd file is encrypted. Assuming it contains a timestamp, this explains why it is always very different. I have been told the correct thing to do is to compare the reported Checksum (in the .par file for Xilinx 10.1, and the .map file for Xilinx 11.1). I have confirmed that although the output from ngdbuild and everything after this is different, that reported Checksum is the same. I was advised to omit the .ise file entirely from an automated system, which was our original goal. Thanks to everyone for your replies. -- David.Article: 140865
Open source microprocessor. BSD. http://nibz.googlecode.com just in case you were wondering.Article: 140866
On May 27, 4:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > <j...@jonathanleslie.com> wrote: > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > >shifting function, but it goes on and says the DCM has a wide > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz signal pha= se > > >locked? > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > > >to mimic that signal on an internal std_logic pin with the idea that > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > >std_logic pin continues the original timing as if nothing has > > >happened. > > > >Any suggestions? > > > Implement your own NCO. Basically run a high resolution counter with > > high speed clock and detect at which count the 2MHz signal is toggling > > (both edges if need be) and generate an internal signal at the same > > count. Now even if the external signal disappears you have the count > > (phase) already and you can keep generating the internal signal. You > > can use this internal signal either as a clock source (ie a divided > > clock) or as an enable to its downstream logic. > > -- > > Muzaffer Kal > > > DSPIA INC. > > ASIC/FPGA Design Services > > >http://www.dspia.com > > as I've been thinking about this today I also thought to forget the > DCM and just do it with the regular system clock. =A0The main system > clock will be anywhere between 25-100MHZ, and for that matter, the > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising edge > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > ticks of the 100MHz clock to do my best "phase lock" Hi Jonathan, I am currently working on the same sort of design. I don't think an NCO is the entire job. What you need is a phase locked loop with a mode of holding the last setting when the input clock is lost. To do this you need an integrator between the phase detector and the NCO which will accumulate and hold a value to maintain the output frequency when the input clock is lost. The trick is this is not a stable circuit and needs other feedback to stabilize it. If you know anything about DSP, this is not a hard problem to analyze. The integrator puts a pole on the unit circle at 1,0 which by itself is not stable. You can add a proportional feedback element to add a zero which can be placed very close to the pole which will stabilize it for frequencies other than near DC. But we don't care about being DC bounded because the feedback loop will compensate for that. RickArticle: 140867
On May 28, 2:09=A0am, gert1999 <ggd...@gmail.com> wrote: > I solved the problem ! > All I had to do is adding the following timing constraints > > clock period 40 ns > offset before clock 10 ns > offset after clock 10 ns > > It just works and had nothing but absolutely nothing to do with the > code > I wonder why the manual did not mention anything about this ? Strange - CPLDs are usually the most timing agnostic. (and you'd expect the tools to take a first guess at any timing) You should be able to compare the two Fitter report files, to see just how the logic mapped, and play 'spot the difference' between the one that worked, and the one that failed. -jgArticle: 140868
On May 27, 4:14 pm, jleslie48 <j...@jonathanleslie.com> wrote: > On May 27, 12:51 pm, Andy Peters <goo...@latke.net> wrote: > > > > > On May 26, 1:13 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > > 23-architecture arch of fifo is > > > > > 24- type reg_file_type is array (2**W-1 downto 0) of > > > > > 25- std_logic_vector(B-1 downto 0); > > > > > 26: signal array_reg: reg_file_type; > > > > > 27- signal w_ptr_reg, w_ptr_next, w_ptr_succ: > > > > > 28- std_logic_vector(W-1 downto 0); > > > > > 29- signal r_ptr_reg, r_ptr_next, r_ptr_succ: > > > > > -- > > > > > 39- process(clk,reset) > > > > > 40- begin > > > > > 41- if (reset='1') then > > > > > 42: array_reg <= (others=>(others=>'0')); > > > > > 43- elsif (clk'event and clk='1') then > > > > > 44- if wr_en='1' then > > > > > 45: array_reg(to_integer(unsigned(w_ptr_reg))) > > > > > 46- <= w_data; > > > > > 47- end if; > > > > > 48- end if; > > > > > 49- end process; > > > > > 50- -- read port > > > > > 51: r_data <= array_reg(to_integer(unsigned(r_ptr_reg))); > > > > > 52- -- write enabled only when FIFO is not full > > > > > 53- wr_en <= wr and (not full_reg); > > > > > 54- > > > > > > Ok, so here's all the code pertaining to array_reg, specifically lines > > > > > 42, 45, and 51. From what I can understand, it seems that the > > > > > professionals here are concerned about line 42; the one resulting from > > > > > the reset signal. What would be the correct way to implement this > > > > > concept? > > > > > Simply delete the asynchronous reset stuff in lines 41 and 42, and > > > > change the "elsif" on line 43 to a simple "if." > > > > > > In C I would of just done a memset(array_reg, 0, sizeof(array_reg)) > > > > > but we ain't in C world any more... > > > > > Indeed -- think HARDWARE. > > > > > Since you are describing a FIFO, there's no need to reset the memory. > > > > Simply resetting the read and write pointers effectively clears the > > > > memory. You will never read from an empty FIFO and a FIFO write > > > > guarantees that you read valid data. > > > > > -a > > > > quite right, > > > > the other process has: > > > process(clk,reset) > > > begin > > > if (reset='1') then > > > w_ptr_reg <= (others=>'0'); > > > r_ptr_reg <= (others=>'0'); > > > full_reg <= '0'; > > > empty_reg <= '1'; > > > > and as my pointers get reset who cares about the data. System > > > resources went dramatically down as a result of the changes, > > > I'm glad the suggestion worked for you! > > > > however > > > two warnings are now being generated that were never there before: > > > > WARNING Route - CLK Net:clk_2mhz is being routed on general routing > > > resources. If you are trying to use local clocking techniques, > > > evaluate the placement of the clock's source and loads to ensure it > > > meets the guidelines for local clocking. Otherwise, consider placing > > > this clock on a dedicated clock routing resource. For more information > > > on clock routing resources, see the target architecture's user guide. > > > > WARNING Route - CLK Net:clk_7812hz is being routed on general routing > > > resources. If you are trying to use local clocking techniques, > > > evaluate the placement of the clock's source and loads to ensure it > > > meets the guidelines for local clocking. Otherwise, consider placing > > > this clock on a dedicated clock routing resource. For more information > > > on clock routing resources, see the target architecture's user guide. > > > > I can't imagine why these are showing up as a result of "fixing" the > > > other error. > > > Sounds like the clock signals are coming into the FPGA on non-clock > > pins. You probably didn't see this error before because the original > > warnings/complaints were issued by XST (the synthesis tool) and you > > went no further. Now that the source synthesizes, the place and route > > tools take over, and the warning you get is issued by the router. > > > Check your UCF and pin selection. > > > -a > > H'mmm, I checked the place and route report before and after the > change in code. the Warnings are definitely not there when the 256 > flip-flop warning is in place. > > I'll have to take a look at the UCF and see what can be done with the > pins I'm using. I'm a bit confused about that, I thought GPIO is > GPIO, I'm sending in a signal, and that's it, but I know that there is > a document out there from Xilinx (how they love their documents) that > says something about the pins... lets me check and see what I can > find. You can use a GPIO pin as a clock line. It will come in through the GPIO buffers, get routed onto logic routing resources and, if it drives a significant amount of logic. eventually be used to drive a global clock line. The part that *might* not be good is the GPIO and general logic routing since it adds a lot of delay. This is only a problem if you are using this clock to drive FFs that have inputs or outputs on I/O pins and you care about the I/O timing. If this clock is only used for logic that does not using inputs or outputs on I/O pins, then it is not an issue. RickArticle: 140869
Hi Folks, I'm a student and electronics hobbyist. I've been collecting various old Altera MAX 7000 related programmers, more as a hobby than anything. And I realize this is old school so no worries, I'm just into the vintage electronics. :) I've been searching the net for the Altera LP6 logic programming card, part of the ASAP2 MPU. Image link below: http://www.digital-circuitry.com/FILES/Altera/Altera%20LP6%20PCI%20card.jpg I've been beating my head against the wall for some time now in frustration as I can't seem to find anything on this card and so I was wondering if anyone here might have one to sell or knows where I could acquire one used or new? Any help would be appreciated. Kind Regards, Gerry O'BrienArticle: 140870
"Gerry_MAN" <gerryob@digital-circuitry.com> wrote in message news:paqdnSqFQanzTIDXnZ2dnUVZ_vidnZ2d@giganews.com... > Hi Folks, > > I'm a student and electronics hobbyist. I've been collecting various old > Altera MAX 7000 related programmers, more as a hobby than anything. > And I realize this is old school so no worries, I'm just into the vintage > electronics. :) > > I've been searching the net for the Altera LP6 logic programming card, > part of the ASAP2 MPU. Image link below: > > http://www.digital-circuitry.com/FILES/Altera/Altera%20LP6%20PCI%20card.jpg > > I've been beating my head against the wall for some time now in > frustration as I can't seem to find anything on this card and so I was > wondering if anyone here might have one to sell or knows where I could > acquire one used or new? > > > Any help would be appreciated. > This may be a silly question, but Why? I thought MAX7000 can be programmed with virtually any programmer?Article: 140871
The Reason is due to the fact that many of the chips I have are in a "JTAG Lockout" state and I need the MPU setup to re-enable the JTAG comm pins. I realize that I can use a third party Universal programmer like a DATA I/O UniSite or similar but, when it comes to Previously programmed chips where the JTAG comm lines have been programmed to I/O pins for extra interfacing lines the other JTAG programmers are useless. :) -Gerry > >"Gerry_MAN" <gerryob@digital-circuitry.com> wrote in message >news:paqdnSqFQanzTIDXnZ2dnUVZ_vidnZ2d@giganews.com... >> Hi Folks, >> >> I'm a student and electronics hobbyist. I've been collecting various old >> Altera MAX 7000 related programmers, more as a hobby than anything. >> And I realize this is old school so no worries, I'm just into the vintage >> electronics. :) >> >> I've been searching the net for the Altera LP6 logic programming card, >> part of the ASAP2 MPU. Image link below: >> >> http://www.digital-circuitry.com/FILES/Altera/Altera%20LP6%20PCI%20card.jpg >> >> I've been beating my head against the wall for some time now in >> frustration as I can't seem to find anything on this card and so I was >> wondering if anyone here might have one to sell or knows where I could >> acquire one used or new? >> >> >> Any help would be appreciated. >> > >This may be a silly question, but Why? > >I thought MAX7000 can be programmed with virtually any programmer? > > >Article: 140872
On May 27, 2:43=A0pm, rickman <gnu...@gmail.com> wrote: > On May 27, 4:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > > >shifting function, but it goes on and says the DCM has a wide > > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz signal p= hase > > > >locked? > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I wan= t > > > >to mimic that signal on an internal std_logic pin with the idea that > > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > > >std_logic pin continues the original timing as if nothing has > > > >happened. > > > > >Any suggestions? > > > > Implement your own NCO. Basically run a high resolution counter with > > > high speed clock and detect at which count the 2MHz signal is togglin= g > > > (both edges if need be) and generate an internal signal at the same > > > count. Now even if the external signal disappears you have the count > > > (phase) already and you can keep generating the internal signal. You > > > can use this internal signal either as a clock source (ie a divided > > > clock) or as an enable to its downstream logic. > > > -- > > > Muzaffer Kal > > > > DSPIA INC. > > > ASIC/FPGA Design Services > > > >http://www.dspia.com > > > as I've been thinking about this today I also thought to forget the > > DCM and just do it with the regular system clock. =A0The main system > > clock will be anywhere between 25-100MHZ, and for that matter, the > > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising edge > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > ticks of the 100MHz clock to do my best "phase lock" > > Hi Jonathan, > > I am currently working on the same sort of design. =A0I don't think an > NCO is the entire job. =A0What you need is a phase locked loop with a > mode of holding the last setting when the input clock is lost. =A0To do > this you need an integrator between the phase detector and the NCO > which will accumulate and hold a value to maintain the output > frequency when the input clock is lost. =A0The trick is this is not a > stable circuit and needs other feedback to stabilize it. =A0If you know > anything about DSP, this is not a hard problem to analyze. =A0The > integrator puts a pole on the unit circle at 1,0 which by itself is > not stable. =A0You can add a proportional feedback element to add a zero > which can be placed very close to the pole which will stabilize it for > frequencies other than near DC. =A0But we don't care about being DC > bounded because the feedback loop will compensate for that. > > Rick Here is an all-digital solution: Assume we have a high clock frequency, e.g. 100 MHz. We use it to clock a DDS accumulator, whose parallel input is an up/ down counter. We also use the 100 MHz to differentiate the rising edge of the incoming 2 MHz frequency. We check whether this short 10 ns pulse occurs during the High or the Low time of the DDS output square wave. If during the Low level, we increment the up/down counter,(speeding up the DDS output) if during the High level, we decrement the counter. When there is no pulse, we leave the counter value stable, since it remembers the missing frequency. I have not checked whether this circuit will always start under all circumstances. Peter AlfkeArticle: 140873
It was actually very common that students who purchased second hand chips of the net like eBay and who where using a JTAG development board for the MAX 7000 series chips, assumed the chips were faulty when they couldn't program them. In actuality the JTAG pins were essentially just disabled and there was nothing wrong with the chip at all. Too Bad really if they had only known. :( I was however able to re-enable the JTAG comm pins on many of my Altera chips using a DATA I/O Labsite Programmer. But now I want to have my own setup and use the Altera (ASAP2) MPU setup to reset my chips, I still have about 40 EPM7128SLC84 chips with the JTAG pins disabled so, hopefully I can find the LP6 card somewhere. So anyone that knows where to get an Altera LP6 Logic Programming card please let me know. I'm willing to purchase it if the price is reasonable. Kind Regards, Gerry O'Brien >The Reason is due to the fact that many of the chips I have are in a >"JTAG Lockout" state and I need the MPU setup to re-enable the JTAG comm >pins. I realize that I can use a third party Universal programmer like a >DATA I/O UniSite or similar but, when it comes to Previously programmed >chips where the JTAG comm lines have been programmed to I/O pins for extra >interfacing lines the other JTAG programmers are useless. :) > >-Gerry > > >> >>"Gerry_MAN" <gerryob@digital-circuitry.com> wrote in message >>news:paqdnSqFQanzTIDXnZ2dnUVZ_vidnZ2d@giganews.com... >>> Hi Folks, >>> >>> I'm a student and electronics hobbyist. I've been collecting various >old >>> Altera MAX 7000 related programmers, more as a hobby than anything. >>> And I realize this is old school so no worries, I'm just into the >vintage >>> electronics. :) >>> >>> I've been searching the net for the Altera LP6 logic programming card, >>> part of the ASAP2 MPU. Image link below: >>> >>> >http://www.digital-circuitry.com/FILES/Altera/Altera%20LP6%20PCI%20card.jpg >>> >>> I've been beating my head against the wall for some time now in >>> frustration as I can't seem to find anything on this card and so I was >>> wondering if anyone here might have one to sell or knows where I could >>> acquire one used or new? >>> >>> >>> Any help would be appreciated. >>> >> >>This may be a silly question, but Why? >> >>I thought MAX7000 can be programmed with virtually any programmer? >> >> >> >Article: 140874
I've been using Xilinx for a few years now, but my new job is strictly Altera. Mostly Cyclones, with a few Max parts thrown in here and there. I figured it wouldn't hurt to compare the latest "cheap" offerings from Xilinx and Altera - and retrain myself on Quartus at home. I can sort of figure out, based on the definition of an LE vs a CLB approximately which parts are equivalent, but without actually compiling designs for both, I'm not sure how the Cyclone III stacks up against its equivalent Spartan 3 (or in my case 3E) part? However, I'd like a sanity check. I'm thinking of using a EP3C16E144 for my next design. I'd like to steer clear of BGA's, and the 144 pin QFP has more than enough I/O for the task. What would the equivalent Spartan 3 series part? It looks like something between a 3E500 and 3E1200, which if true, would be just about perfect for what I'm trying to do.
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