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Thomas Stanka <usenet_nospam_valid@stanka-web.de> wrote: > Am Montag, 4. November 2013 15:48:28 UTC+1 schrieb Kristo Godari: >> I need a Verilog behavioral model (verilog behavioral code) for: >> - unsigned 8-bit division > behavioral model means not necessary synthesisable. This is true, and I prefer structural verilog, but enough is synthesizable that many do write behavioral model for synthesis. > Easiest is a = b/c. > Your teacher don't like you to use this easiest sollution, > so he requestst you to learn about additional algorithms and > write them down. Since there is no clock, it has to be all combinatorial logic. I find continuous assignment more readable for combinatorial logic than behavioral assignment. On the other hand, I like to read state machines in behavioral form, where there is a latch on every state transition. -- glenArticle: 156001
Hi all, what we have here is both a lazy teacher giving an understated assignment, = and the typical student of this decade, looking the easy way through. As mo= st of 20ers are these days, he needs time for WoW, tablet time, txting, net= news or whatever. I would start with an untimed version in C, then devise the FSM/FSMD and do= the work. Shouldn't be more than an afternoon for each subtask for a stude= nt. Of course, this requires to wake up the teacher and ask him whether he = really requests a combinational implementation or would allow for a clock. Best regards Nikolaos KavvadiasArticle: 156002
Nikolaos Kavvadias <nikolaos.kavvadias@gmail.com> wrote: > what we have here is both a lazy teacher giving an understated > assignment, and the typical student of this decade, looking the > easy way through. As most of 20ers are these days, he needs time > for WoW, tablet time, txting, net news or whatever. Well, it is presumable in the context of what was taught in class, which we don't know. > I would start with an untimed version in C, then devise > the FSM/FSMD and do the work. Shouldn't be more than an > afternoon for each subtask for a student. Of course, > this requires to wake up the teacher and ask him whether > he really requests a combinational implementation or would > allow for a clock. What is wrong with the combinatorial one? They tend to take more hardware, as you can't time-share (reuse) parts of the logic, but there is nothing wrong with that. Seems to me that one should learn the combinatorial one first. Also, that is what verilog would generate if it synthesized the / operator. (I presume some do now, especially for only eight bits.) Now, often in actual practice one wants either the pipelined or iterative algorithm, but one should be able to understand any and all of them. -- glenArticle: 156003
Hi Glen, > What is wrong with the combinatorial one? There is nothing wrong with the combinational divider in principle. Eventually, for use in an IP-based scheme, inputs and outputs would be registered. For standalone use/experimentation it is OK. One would cascade maybe 1 or 2 iterations of either NR or Goldschmidt and this would be fine especially for such small datapath size. I guess a LUT-based scheme would also do. > Also, that is what verilog would generate if it synthesized > the / operator. (I presume some do now, especially for only > eight bits.) I am very interested to know which of the current RTL tools has a module generator for division. It would be a strong asset. For instance, tools don't have a module generator for integer modulo (apart from trivial cases). I have an implementation of a very good algorithm (published in 2011) for variable and constant modulo: http://nkavvadias.com/eshop/index.php?id_product=9&controller=product https://groups.google.com/forum/#!msg/comp.lang.verilog/7ei2AKq6_Es/7vLHSCkTg3UJ It is a pay IP alright, but the product brief and documentation are free for downloading. Any of the A, X, L, M, or S companies should provide such module generators in their backend tools. Best regards Nikolaos KavvadiasArticle: 156004
Hi everyone again... some update on this issue from my side. Read below if you are interested. On 29/10/2013 13:46, alb wrote: [] > this might be a stupid question to ask here but I really do not know > where else I can post it. I filed 4 technical support requests on the > Microsemi website last Friday and, as of today, never had an answer back > (not even a confirmation email of the request! [1]). [] if you ever want to contact Microsemi for technical support go through this link: http://www.actel.com/mycases If you are registered you can log in and open/close/modify all cases which are quickly updated by an FAE assigned to each of them. Avoid to use the technical support link (http://www.microsemi.com/design-support/technical-support) instead, since I've never received any update on my questions and had to input them again in their systems through the link previously mentioned. Hope that will help some other user. Cheers, AlArticle: 156005
Hi all, here is a feedback from the FAEs at Microsemi concerning the power up reset, please see my comments inline if you are interested. On 16/10/2013 10:02, alb wrote: [] > On 15/10/2013 03:59, rickman wrote: [] >> If there is no reset, what can you know about the state of the FFs on >> powerup? If they are random, I don't think you can make this work >> without a power up reset. > > In the AN I posted there's a solution the vendor proposes to implement a > POR. They suggest to rely on an external weak pull-up and profit of the > different time for input/output configuration during a power-up > sequence. I do not have an external pull-up, but I/Os can be opted with > a weak pull-up and maybe the result is the same. > According to the FAE it is possible to configure the internal weak pull-up resistor on the PIN configuration and profit of the same mechanism described in the AN I was referring to (http://www.actel.com/documents/LPF_AC380_AN.pdf), therefore *without* the need of an additional external pull up resistor. AlArticle: 156006
Am Mittwoch, 6. November 2013 08:52:16 UTC+1 schrieb Nikolaos Kavvadias: > I am very interested to know which of the current RTL tools has a module generator for division. It would be a strong asset. Check out designware for Synopsys design compiler. regards ThomasArticle: 156007
alb wrote: > Hi everyone again... some update on this issue from my side. Read below > if you are interested. > > On 29/10/2013 13:46, alb wrote: > [] >> this might be a stupid question to ask here but I really do not know >> where else I can post it. I filed 4 technical support requests on the >> Microsemi website last Friday and, as of today, never had an answer back >> (not even a confirmation email of the request! [1]). > [] > > if you ever want to contact Microsemi for technical support go through > this link: http://www.actel.com/mycases I second this. > > If you are registered you can log in and open/close/modify all cases > which are quickly updated by an FAE assigned to each of them. The email support has its limits due to time zone differences. We have committed to buy SF2 from them and get excellent support from Microsemi European FAE. -- SvennArticle: 156008
On Mon, 04 Nov 2013 12:51:45 -0800, Kristo Godari wrote: > I forgot to say that i can't use '/' or '%'.And i can't change the > module structure the module must have 2 inputs and 2 outputs: > > module divider( > output reg[7:0] q, > output reg[7:0] r, > input [7:0] a,b); > > /* > Code goes here > */ > > endmodule So, this is homework? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 156009
> So, this is homework? > > Tim Wescott > Wescott Design Services Seems so. This guy was also in freelancer (which implies that I was there, too). Most freelancers offered around 30 USD per divider topology, which is about the cost of a casual (low-cost) dinner for two in Greece. But this is week's payment in a number of countries around the globe.Article: 156010
hi guys,
i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting
Article: 156011Am Freitag, 8. November 2013 12:25:23 UTC+1 schrieb shrinivas gotur: > i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting The only fpga with included ADC is microsemi fusion fpga. Guess it sells in too small numbers to see more devices of that kind in near future on market available.Article: 156012
Thomas Stanka wrote: > Am Freitag, 8. November 2013 12:25:23 UTC+1 schrieb shrinivas gotur: >> i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting > > The only fpga with included ADC is microsemi fusion fpga. Guess it sells in too small numbers to see more devices of that kind in near future on market available. Newer Xilinx devices (7-series) have built-in ADC's. You'd need to use some external parts to handle your 5V input range. These parts are not cheap, however. You'd probably do better with a cheap plain FPGA and a separate ADC chip. Look at Artix-7 for the least expensive of the lot. -- GaborArticle: 156013
On 11/6/2013 11:07 AM, alb wrote: > Hi all, here is a feedback from the FAEs at Microsemi concerning the > power up reset, please see my comments inline if you are interested. > > On 16/10/2013 10:02, alb wrote: > [] >> On 15/10/2013 03:59, rickman wrote: > [] >>> If there is no reset, what can you know about the state of the FFs on >>> powerup? If they are random, I don't think you can make this work >>> without a power up reset. >> >> In the AN I posted there's a solution the vendor proposes to implement a >> POR. They suggest to rely on an external weak pull-up and profit of the >> different time for input/output configuration during a power-up >> sequence. I do not have an external pull-up, but I/Os can be opted with >> a weak pull-up and maybe the result is the same. >> > > According to the FAE it is possible to configure the internal weak > pull-up resistor on the PIN configuration and profit of the same > mechanism described in the AN I was referring to > (http://www.actel.com/documents/LPF_AC380_AN.pdf), therefore *without* > the need of an additional external pull up resistor. The app note goes into great detail about the timing of VCC and VCCI. In this discussion I believe they are talking about the input from the IBUF (RST_p) when they say, "The I/Os are tristated and the core logic detects '1' on the inputs from the boundary scan register (BSR)." It is not clear what sets the value in the BSR. It is also not clear how this determines the value of the RST_p signal. Do you understand this portion of the reset design? This entire circuit seems to depend on VCC reaching "its functional voltage level" before VCCI. Do you know that this is true for your board? It would be good to have a dialog with the person who wrote the app note, but they don't say who this is. Much of the language usage would indicate it is someone for whom English is a second language and so might not be easy to converse with. -- RickArticle: 156014
On 11/6/2013 9:57 AM, alb wrote: > Hi everyone again... some update on this issue from my side. Read below > if you are interested. > > On 29/10/2013 13:46, alb wrote: > [] >> this might be a stupid question to ask here but I really do not know >> where else I can post it. I filed 4 technical support requests on the >> Microsemi website last Friday and, as of today, never had an answer back >> (not even a confirmation email of the request! [1]). > [] > > if you ever want to contact Microsemi for technical support go through > this link: http://www.actel.com/mycases > > If you are registered you can log in and open/close/modify all cases > which are quickly updated by an FAE assigned to each of them. > > Avoid to use the technical support link > (http://www.microsemi.com/design-support/technical-support) instead, > since I've never received any update on my questions and had to input > them again in their systems through the link previously mentioned. > > Hope that will help some other user. > Cheers, > > Al That is *very* bizarre! Two different technical support methods, one functional and one dysfunctional. Although I can't say this is unique in the industry, I can say it is very unusual and very... well, dysfunctional. Is there any links to the functional support page from the rest of the web site or do you just have to know about it? -- RickArticle: 156015
On Fri, 8 Nov 2013 03:25:23 -0800 (PST) shrinivas gotur <shri.gotur@gmail.com> wrote: > hi guys, > i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting To what end? An external ADC allows you to trade off speed/resolution/cost as necessary, and doesn't mean that your ADC is trying to share a substrate with tiny CMOS gates switching at hundreds of MHz. And for any moderate rate of throughput you can talk to it SPI for a cost of a whopping 4 pins. -- Rob Gaddi, Highland Technology -- www.highlandtechnology.com Email address domain is currently out of order. See above to fix.Article: 156016
Dear all, just to keep you updated with the latest on HercuLeS high-level synthesis: http://www.nkavvadias.com/temp/index.php http://www.ajaxcompilers.com New versions for Windows 7 (64-bit) and Linux (64-bit) have recently been uploaded. Here is the update summary: 2013-11-06: HercuLeS GUI integration simplifications (Windows 7 only). 2013-10-30: Linux 64-bit version added! (experimental) 2013-10-29: Windows and Linux 32-bit version fix: Garbage collection library was missing. 2013-10-25: Linux 32-bit version added! For anyone interested, there is also an installer for the Windows 7 version. Let me know if you are interested to directly get the installer (I will then supply you with a direct link). Best regards Nikolaos Kavvadias CEO Ajax Compilers Kornarou 12 Rd, Nea Ampliani, 35100 Lamia GreeceArticle: 156017
On 11/8/2013 6:25 AM, shrinivas gotur wrote: > hi guys, > i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting You can build an ADC in an FPGA with decent performance. Look up DeltaSigma converters. Many FPGAs have differential inputs which can be used as an analog comparator. The rest is digital. -- RickArticle: 156018
Hi, I am unable to understand that how a PC communicate with FPGA. I have used = Xilinx software to implement codes and then connected a USB cable to Xilinx= test kit that did all jobs for me. Of course I assigned the chip pins with= the signal names through Xilinx software itself. I am unaware what happens= after I connect the USB cable to the kit. Please tell me what devices are = in between the PC and the chip in the kit and how does the PC communicate w= ith the chip or loads the design into the chip? thanks KoyelArticle: 156019
Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks of 15= 0MHz, 112.5MHz and 14.063MHz. I can't produce them with one pll core since = it does not generate the exact clock. If i concatenate two cores, the seco= nd core does not produce clock. ( i set one core with input clock as extern= al and other as hardwired). I need help to produce these 3 clocks.Article: 156020
On 11/10/2013 3:04 AM, koyel.aphy@gmail.com wrote: > Hi, > > I am unable to understand that how a PC communicate with FPGA. I have used Xilinx software to implement codes and then connected a USB cable to Xilinx test kit that did all jobs for me. Of course I assigned the chip pins with the signal names through Xilinx software itself. I am unaware what happens after I connect the USB cable to the kit. Please tell me what devices are in between the PC and the chip in the kit and how does the PC communicate with the chip or loads the design into the chip? > > thanks Koyel > Most Xilinx kits use some sort of FTDI USB chip. You should be able to find the schematic for your kit on the Xilinx site. -- GaborArticle: 156021
On Sun, 20 Oct 2013 08:47:57 +0100, Tom Gardner <spamjunk@blueyonder.co.uk> wrote: >On 20/10/13 03:02, Paul Rubin wrote: >> Tom Gardner <spamjunk@blueyonder.co.uk> writes: >>> I'd like to pick people's brains about aspects of >>> different *suppliers* of Zynq boards. >> >> Do you know anything about the microzed? I just heard of it, and it >> looks interesting: >> >> http://microzed.org >> http://linuxgizmos.com/tiny-sbc-runs-linux-on-xilinx-zynq-arm-fpga/ >> >> Also the Zybo: >> >> http://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO > >They do indeed look interesting for my purposes, but I only >know what I can read on the web. > >So, we would /both/ like some info about the suppliers :) > > We're just starting on a uZed signal-processing project. It will be a uZed plugged into a motherboard that has power, clock, signal input and output networks, ADC, DAC, connectors, and miscellaneous stuff. We bought two uZed boards from Avnet and they power up running Linux. My programmer and FPGA guys are just now learning how to write a C app that interacts with the FPGA, but the documentation seems good and they are making good progress. I'll be doing the architecture and designing the hardware. I took some pictures. The ones in the ZED documentation are mediocre. https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Top.JPG https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Bottom.JPG https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_End.JPG -- John Larkin Highland Technology Inc www.highlandtechnology.com jlarkin at highlandtechnology dot com Precision electronic instrumentation Picosecond-resolution Digital Delay and Pulse generators Custom timing and laser controllers Photonics and fiberoptic TTL data links VME analog, thermocouple, LVDT, synchro, tachometer Multichannel arbitrary waveform generatorsArticle: 156022
On Friday, 8 November 2013 16:55:23 UTC+5:30, shrinivas gotur wrote: > hi guys, > > i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input range will be available in market. please revert back soon if u know any.i am waiting thanks guys for your time.actually i wanted to interface A real time lvdt with fpga so i was thiking of built in adc.Article: 156023
On 11/11/13 03:08, John Larkin wrote: > On Sun, 20 Oct 2013 08:47:57 +0100, Tom Gardner <spamjunk@blueyonder.co.uk> > wrote: > >> On 20/10/13 03:02, Paul Rubin wrote: >>> Tom Gardner <spamjunk@blueyonder.co.uk> writes: >>>> I'd like to pick people's brains about aspects of >>>> different *suppliers* of Zynq boards. >>> >>> Do you know anything about the microzed? I just heard of it, and it >>> looks interesting: >>> >>> http://microzed.org >>> http://linuxgizmos.com/tiny-sbc-runs-linux-on-xilinx-zynq-arm-fpga/ >>> >>> Also the Zybo: >>> >>> http://www.digilentinc.com/Products/Detail.cfm?Prod=ZYBO >> >> They do indeed look interesting for my purposes, but I only >> know what I can read on the web. >> >> So, we would /both/ like some info about the suppliers :) >> >> > > We're just starting on a uZed signal-processing project. It will be a uZed > plugged into a motherboard that has power, clock, signal input and output > networks, ADC, DAC, connectors, and miscellaneous stuff. We bought two uZed > boards from Avnet and they power up running Linux. My programmer and FPGA guys > are just now learning how to write a C app that interacts with the FPGA, but the > documentation seems good and they are making good progress. I'll be doing the > architecture and designing the hardware. > > I took some pictures. The ones in the ZED documentation are mediocre. > > https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Top.JPG > > https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_Bottom.JPG > > https://dl.dropboxusercontent.com/u/53724080/PCBs/Micro_Zed_End.JPG Thanks, that's useful, and I will be *most* interested to hear how it goes. Out of curiosity, how long ago did you buy them and how long did they take to materialise? Currently Avnet are showing no stock and 5 weeks lead time. Worryingly, it has been "5 weeks" for the past 3 weeks - so I'm concerned that Avnet have "lost interest" in the board. Any info about Avnet's support practices would be useful.Article: 156024
Nikolaos Kavvadias wrote: > Seems so. This guy was also in freelancer (which implies that I was there, too). > > Most freelancers offered around 30 USD per divider topology, which is about the cost > of a casual (low-cost) dinner for two in Greece. But this is week's > payment in a number of countries around the globe. > Shit, I need a native USB 2.0 host in VHDL. Any poor sucker who would do a 4 week job at USD30/week? Cash on Delivery!!!! (though paypal) Is this how we want globalization to work? -- Svenn
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Compare FPGA features and resources
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