Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
David Brown wrote: > On 10/12/2012 02:04, no one wrote: >> I assume the bay area is number one for embedded software engineers, >> but where else are the big markets, as companies run from califoria >> taxes. >> >> Denver, CO - Does big population mean high tech? >> Phoenix, AZ - Sun birds. >> Albuquerque, NM - Sun birds, ballon festival. >> Salt Lake City, UT - Mormons, big population. >> Portland, OR - Big population. >> Seattle, WA - All those ex-Microsofties starting companies. >> >> Which of these are go, or no-go? >> >> And if the bay area is it, where in the bay area? >> > > This is an international group, not an American group - "the bay area" > is meaningless outside your country. > It's meaningless in most of the USA also. I used to live in the "bay area" on the "west coast" - Tampa, FL... > And since the world extends a long way outside the USA, have you > considered moving abroad? Certainly Norway has a great shortage of > engineers. > Have you considered looking for a job first, and then deciding where to move? In this economy, that would seem a sounder approach. -- GaborArticle: 154651
In article <ka3e4a$vab$1@dont-email.me>, hamilton <hamilton@nothere.com> wrote: > On 12/9/2012 6:04 PM, no one wrote: > > I assume the bay area is number one for embedded software engineers, > > but where else are the big markets, as companies run from califoria taxes. > > > > Denver, CO - Does big population mean high tech? > > Phoenix, AZ - Sun birds. > > Albuquerque, NM - Sun birds, ballon festival. > > Salt Lake City, UT - Mormons, big population. > > Portland, OR - Big population. > > Seattle, WA - All those ex-Microsofties starting companies. > > > > Which of these are go, or no-go? > > > > And if the bay area is it, where in the bay area? I find I must specify the California bay area, picky, picky, picky. ;) > I see by your list, you are not going East of the Miss. Correct. ;) > Embedded Software Engineers is no longer a term of embedded processor > engineers. > > Everyone uses it anymore, so you really need to be specific about _your_ > definition of embedded engineer. > > As this is an FPGA newsgroup, do you mean Embedded FPGA engineer ? No, I just happen to lurk here as the posts are interesting. > Do you mean assembly language / C language Embedded Engineer ? Correct, and this group seemed to cover software as well as hardware, though a few think not. If anyone would nominate a non-dead more software embedded newsgroup I will gladly go take a look. With the exception of C++ groups, fringe freaks debating broken ideas do not excite me. > PS: Don't Come to Denver, we have too many UN-employed engineers already. I have scoped out Denver a little and each of the suburb cities seems to have a major high tech company. On the downside last time I drove through I found the traffic to be horrible. Denver is so big I would have to pick a sub-city as the commute is to long, same as California. All those places I listed (except the bay area) would allow me to engage my geology hobby on the weekends.Article: 154652
On 12/12/2012 05:52, no one wrote: > In article <ka3e4a$vab$1@dont-email.me>, >> As this is an FPGA newsgroup, do you mean Embedded FPGA engineer ? > > No, I just happen to lurk here as the posts are interesting. That's why I am here too. I have only done a little FPGA (or CPLD) development, but sometimes threads here can be very interesting. I've learned a lot about high-speed digital design from this group over the years, and it applies to processor-based boards just as well as to FPGA boards. > >> Do you mean assembly language / C language Embedded Engineer ? > > Correct, and this group seemed to cover software as well as hardware, > though a few think not. If anyone would nominate a non-dead more software > embedded newsgroup I will gladly go take a look. > That would be comp.arch.embedded. It is not software-only, but that is certainly a common topic. mvh., DavidArticle: 154653
And since the world extends a long way outside the USA, have you considered moving abroad? Certainly Norway has a great shortage of engineers. Really? Where can I search for job listings?Article: 154654
On Tue, 11 Dec 2012 22:52:17 -0600, no one wrote: > In article <ka3e4a$vab$1@dont-email.me>, > hamilton <hamilton@nothere.com> wrote: > >> On 12/9/2012 6:04 PM, no one wrote: >> > I assume the bay area is number one for embedded software engineers, >> > but where else are the big markets, as companies run from califoria >> > taxes. >> > >> > Denver, CO - Does big population mean high tech? Phoenix, AZ - Sun >> > birds. >> > Albuquerque, NM - Sun birds, ballon festival. Salt Lake City, UT - >> > Mormons, big population. Portland, OR - Big population. >> > Seattle, WA - All those ex-Microsofties starting companies. >> > >> > Which of these are go, or no-go? >> > >> > And if the bay area is it, where in the bay area? > > I find I must specify the California bay area, picky, picky, picky. ;) > >> I see by your list, you are not going East of the Miss. > > Correct. ;) > >> Embedded Software Engineers is no longer a term of embedded processor >> engineers. >> >> Everyone uses it anymore, so you really need to be specific about >> _your_ definition of embedded engineer. >> >> As this is an FPGA newsgroup, do you mean Embedded FPGA engineer ? > > No, I just happen to lurk here as the posts are interesting. > >> Do you mean assembly language / C language Embedded Engineer ? > > Correct, and this group seemed to cover software as well as hardware, > though a few think not. If anyone would nominate a non-dead more > software embedded newsgroup I will gladly go take a look. > > With the exception of C++ groups, fringe freaks debating broken ideas do > not excite me. > >> PS: Don't Come to Denver, we have too many UN-employed engineers >> already. > > I have scoped out Denver a little and each of the suburb cities seems to > have a major high tech company. On the downside last time I drove > through I found the traffic to be horrible. Denver is so big I would > have to pick a sub-city as the commute is to long, same as California. > > All those places I listed (except the bay area) would allow me to engage > my geology hobby on the weekends. comp.arch.embedded is active, on-topic, and usually has many interesting threads. Dallas and Austin both have a lot of high tech. LA and San Diego have some automotive and industrial, and lots of defense stuff. Embedded is everywhere. If you're really pretty agnostic about where you want to work, I'd suggest that you just move to the first job you find (and in this economy, don't settle down: consider renting and not buying much stuff that's hard to move 1000 miles). Pay close attention to cost of living: I had a friend from the Portland (OR) area who went to work at a company in Silicon Valley at a pay rate that astonished him, only to discover after he had moved that the cost of rent and food and damn near everything else is astonishing, too -- he soon found a gig in Seattle for way less pay and higher net return. This cuts both ways: a pay rate that sucks in Portland (and is in the sub- basements in San Jose) may get you ahead in the long run if the job is in Missoula. Even though you specifically mention not looking east of the Mississippi, you should take a second look at the east coast. Massachusetts has tons of high-tech along the 128 corridor, and even more work scattered up and down I-495. There's plenty of high-tech in New Hampshire, to boot. If you don't mind Military, there's tons of work to be had in the various Washington DC outer suburbs, and the southeast is coming on strong. I'm sure I'm leaving out something here, but you get the idea. If you like your geology flat, there's always the Midwest: anything automotive (and I mean _anything_: cars, tractors, railway, etc.) needs lots of embedded, and it's all concentrated around the great lakes. It's not a bad idea if you do settle down to try to scope out where the work is concentrated, and try to center yourself in the area (or if you want to live out of town a bit, go for "center-rural"). Settling right next to work is great until you have to change jobs. Settling in the middle of a 30-minute-drive-to-anywhere spot works well when things change, or when the spouse gets a job, too. -- My liberal friends think I'm a conservative kook. My conservative friends think I'm a liberal kook. Why am I not happy that they have found common ground? Tim Wescott, Communications, Control, Circuits & Software http://www.wescottdesign.comArticle: 154655
On 12/12/2012 11:32 AM, Tim Wescott wrote: > > comp.arch.embedded is active, on-topic, and usually has many interesting > threads. If you visit comp.arch.embedded, be aware of the (right/left) wing crackpot that live there. "interesting threads" is an understatement !!Article: 154656
Hello, I have to detect the Start of a Ethernet Frame. So I want to make use of a = FPGA. The FPGA will be connected to the MII pins of the PHY (TXD 0-3 and RX= D 0-3, the Clocks, TX_EN and RX_DV). What I know from the IEEE802.3 Datashe= ets is that the preamble will be send as 14 Nibbles and after that 2 Nibble= s the SFD.=20 In transmitting case it will be like that: TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.. So I thought that I can trigger the rising edge from TxD3 in the 16. Cylce = or from Tx_En. But if I only check one wire there could be errors right? Ho= w do I check for more than one Cylce? Do I need a State machine? Is this the correct path? I found the example of SFD detection from OpenCores.org of the EtherMac pro= ject, but i dont have any verilog or vhdl knowledge. Thatswhy i wanted to use the Xilinx ISE Schematic tool.=20 So can you help me by giving me some advice how to make use of some fast lo= gic.=20 Do i need some FIFOs oder Latches?=20 Thank you very much and greetingsArticle: 154657
Tim Wescott wrote: > On Tue, 11 Dec 2012 22:52:17 -0600, no one wrote: > >> In article <ka3e4a$vab$1@dont-email.me>, >> hamilton <hamilton@nothere.com> wrote: >> >>> On 12/9/2012 6:04 PM, no one wrote: >>>> I assume the bay area is number one for embedded software engineers, >>>> but where else are the big markets, as companies run from califoria >>>> taxes. >>>> >>>> Denver, CO - Does big population mean high tech? Phoenix, AZ - Sun >>>> birds. >>>> Albuquerque, NM - Sun birds, ballon festival. Salt Lake City, UT - >>>> Mormons, big population. Portland, OR - Big population. >>>> Seattle, WA - All those ex-Microsofties starting companies. >>>> >>>> Which of these are go, or no-go? >>>> >>>> And if the bay area is it, where in the bay area? >> >> I find I must specify the California bay area, picky, picky, picky. ;) >> >>> I see by your list, you are not going East of the Miss. >> >> Correct. ;) >> >>> Embedded Software Engineers is no longer a term of embedded processor >>> engineers. >>> >>> Everyone uses it anymore, so you really need to be specific about >>> _your_ definition of embedded engineer. >>> >>> As this is an FPGA newsgroup, do you mean Embedded FPGA engineer ? >> >> No, I just happen to lurk here as the posts are interesting. >> >>> Do you mean assembly language / C language Embedded Engineer ? >> >> Correct, and this group seemed to cover software as well as hardware, >> though a few think not. If anyone would nominate a non-dead more >> software embedded newsgroup I will gladly go take a look. >> >> With the exception of C++ groups, fringe freaks debating broken ideas do >> not excite me. >> >>> PS: Don't Come to Denver, we have too many UN-employed engineers >>> already. >> >> I have scoped out Denver a little and each of the suburb cities seems to >> have a major high tech company. On the downside last time I drove >> through I found the traffic to be horrible. Denver is so big I would >> have to pick a sub-city as the commute is to long, same as California. >> >> All those places I listed (except the bay area) would allow me to engage >> my geology hobby on the weekends. > > comp.arch.embedded is active, on-topic, and usually has many interesting > threads. > > Dallas and Austin both have a lot of high tech. Dallas has this endless supply of 3 month Java contracts, so it's at least something, but there's not a lot of embedded work. Something's gone horribly wrong in Dallas. Can't put my finger on it. > LA and San Diego have > some automotive and industrial, and lots of defense stuff. > > Embedded is everywhere. If you're really pretty agnostic about where you > want to work, I'd suggest that you just move to the first job you find > (and in this economy, don't settle down: consider renting and not buying > much stuff that's hard to move 1000 miles). > +1. You can move a lot of stuff surprisingly cheap these days. > Pay close attention to cost of living: I had a friend from the Portland > (OR) area who went to work at a company in Silicon Valley at a pay rate > that astonished him, only to discover after he had moved that the cost of > rent and food and damn near everything else is astonishing, too-- he > soon found a gig in Seattle for way less pay and higher net return. This > cuts both ways: a pay rate that sucks in Portland (and is in the sub- > basements in San Jose) may get you ahead in the long run if the job is in > Missoula. > > Even though you specifically mention not looking east of the Mississippi, > you should take a second look at the east coast. Massachusetts has tons > of high-tech along the 128 corridor, and even more work scattered up and > down I-495. There's plenty of high-tech in New Hampshire, to boot. If > you don't mind Military, there's tons of work to be had in the various > Washington DC outer suburbs, They very frequently expect an active clearance and military spend is in grave risk these days - has been since '08. If you point that way get and keep an active clearance. > and the southeast is coming on strong. I'm > sure I'm leaving out something here, but you get the idea. > > If you like your geology flat, there's always the Midwest: anything > automotive (and I mean _anything_: cars, tractors, railway, etc.) needs > lots of embedded, and it's all concentrated around the great lakes. > Yep. It also usually has a very low Mickey Mouse factor. > It's not a bad idea if you do settle down to try to scope out where the > work is concentrated, and try to center yourself in the area (or if you > want to live out of town a bit, go for "center-rural"). Settling right > next to work is great until you have to change jobs. Settling in the > middle of a 30-minute-drive-to-anywhere spot works well when things > change, or when the spouse gets a job, too. > -- Les CargillArticle: 154658
bln5320@googlemail.com wrote: > I have to detect the Start of a Ethernet Frame. So I want to > make use of a FPGA. The FPGA will be connected to the MII pins > of the PHY (TXD 0-3 and RXD 0-3, the Clocks, TX_EN and RX_DV). > What I know from the IEEE802.3 Datasheets is that the preamble > will be send as 14 Nibbles and after that 2 Nibbles the SFD. > In transmitting case it will be like that: > TxD0 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data > TxD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Data > TxD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data > TxD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Data > TxEn 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1.. You could crosspost to comp.dcom.lans.ethernet. Though there isn't so much traffic over there, it still seems like the right place. -- glenArticle: 154659
On 12/12/2012 22:26, hamilton wrote: > On 12/12/2012 11:32 AM, Tim Wescott wrote: > >> >> comp.arch.embedded is active, on-topic, and usually has many interesting >> threads. > > If you visit comp.arch.embedded, be aware of the (right/left) wing > crackpot that live there. > > "interesting threads" is an understatement !! > I use c.a.e. all the time, but I am not aware of any such crackpots - the newsgroup is mercifully free of such people. There are a few with strong or unusual opinions (people probably think of me that way at times), but none of the sort of characters who blame some politician for every bug in their software, or throw a tantrum when they are contradicted. Occasionally, we get visits from such people via cross-posts. sci.electronics.design is a group that is mostly dedicated to political discussions amongst retired Americans that view mainstream Republican politics as so left-wing they are practically communist, but it sometimes also has threads on the topic of electronics design. These can get cross-posted to c.a.e., and start off fine - but inevitably degenerate into politics. There is also the world-famous (in the Usenet world, anyway) character Rod Speed, whom I have seen once or twice in c.a.e. via cross-posts to Australian electronics newsgroups. But I haven't seen him at his full strength there. All in all, c.a.e. is at a similar level to c.a.f. regarding crackpots, off-topic threads, spam, etc.Article: 154660
On 10.12.2012 02:04, no one wrote: > I assume the bay area is number one for embedded software engineers, > but where else are the big markets, Southern Germany. Lots of companies seem to be hiring around here, inluding some bigger ones, such as Bosch and Sick, and a huge number of smaller ones with at most a few hundred employees. PhilippArticle: 154661
> You could crosspost to comp.dcom.lans.ethernet. > > > > Though there isn't so much traffic over there, it still seems like > > the right place. > > > > -- glen Thanks for the advice I will also try my luck there. So for the question with the Schematic in generell. How do I check for Signals that are High for more than one Cylce. Something like: If Tx_En is asserted begin to check: Signal ( TxD0 & TxD2) == 1 for 16 Cylces Signal ( TxD1 ) == 0 for 16 Cycles Signal ( TxD3 ) == 0 for 15 Cycles and after that its rising to 1 output SFD detected! If its not possible with logic from schematics I have to learn some verilog and vhdl :) Thanks and greetingsArticle: 154662
bln5320@googlemail.com wrote: >> You could crosspost to comp.dcom.lans.ethernet. >> >> >> >> Though there isn't so much traffic over there, it still seems like >> >> the right place. >> >> >> >> -- glen > > Thanks for the advice I will also try my luck there. > > So for the question with the Schematic in generell. How do I check for Signals that are High for more than one Cylce. > Something like: > If Tx_En is asserted > begin to check: > Signal ( TxD0 & TxD2) == 1 for 16 Cylces > Signal ( TxD1 ) == 0 for 16 Cycles > Signal ( TxD3 ) == 0 for 15 Cycles and after that its rising to 1 > output SFD detected! > > If its not possible with logic from schematics I have to learn some verilog and vhdl :) > > Thanks and greetings You'd use the same structures whether it's schematics or HDL. For each bit you need history of the most recent 16 cycles. This usually means you want a 16-bit serial-in parallel-out shift-register. Look for the desired bit patterns on the output of the S/R. This generally means a 16-bit AND gate with various inputs inverted. If this pattern could crop up unexpectedly during a data packet, you'd need some additional logic to filter it out. For that, a state machine may be better. There's nothing to say you can't have a schematic based design with state machines, but most people generally use HDL for that. When I was designing FPGA's with schematics, all of my state machines were HDL "macros" instantiated in the schematic. -- GaborArticle: 154663
Ouch; state machines in schematics... that brings back some painful memories. I usually used a ROM with feedback from Q to A. Some data bits were outputs. Some address bits were inputs. I also occasionally used a state register that fed the control lines to a mux, whose outputs fed the state register. The inputs to the mux defined next state and any outputs. HDL is SO much easier... AndyArticle: 154664
On 13/12/2012 23:14, jonesandy@comcast.net wrote: > Ouch; state machines in schematics... that brings back some painful memories. Interesting, I can't imagine designing state machines in anything else but schematics ;-) I use HDL Designer to quickly draw a bubble diagram and let the tool generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine, sync/async reset, encoding style, etc.). Hans www.ht-lab.com > I usually used a ROM with feedback from Q to A. Some data bits were outputs. Some address bits were inputs. > > I also occasionally used a state register that fed the control lines to a mux, whose outputs fed the state register. The inputs to the mux defined next state and any outputs. > > HDL is SO much easier... > > Andy >Article: 154665
"Philipp Klaus Krause" wrote in message news:kacoae$25e$1@solani.org... On 10.12.2012 02:04, no one wrote: > I assume the bay area is number one for embedded software engineers, > but where else are the big markets, Southern Germany. Lots of companies seem to be hiring around here, inluding some bigger ones, such as Bosch and Sick, and a huge number of smaller ones with at most a few hundred employees. Remember to tell that You will probably must speek German...Article: 154666
HT-Lab <hans64@htminuslab.com> wrote: > On 13/12/2012 23:14, jonesandy@comcast.net wrote: >> Ouch; state machines in schematics... that brings back some painful memories. > Interesting, I can't imagine designing state machines in anything else > but schematics ;-) There are state machine design tools, but the usual meaning of schematic is you move gates and registers around, then connect the inputs and outputs with lines. Be careful that the lines aren't on top of previous ones, where they might accidentally connect. (Some editors make such accidents easier than others.) Fortunately I never did that before learning verilog. I did some for other projects after using verilog, though. I find it much easier to hand convert to verilog than to work on something in the schematic editor. > I use HDL Designer to quickly draw a bubble diagram and let the tool > generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine, > sync/async reset, encoding style, etc.). -- glenArticle: 154667
On 12/14/2012 2:16 AM, scrts wrote: > "Philipp Klaus Krause" wrote in message news:kacoae$25e$1@solani.org... > On 10.12.2012 02:04, no one wrote: >> I assume the bay area is number one for embedded software engineers, >> but where else are the big markets, > > Southern Germany. Lots of companies seem to be hiring around here, > inluding some bigger ones, such as Bosch and Sick, and a huge number of > smaller ones with at most a few hundred employees. > > > > Remember to tell that You will probably must speek German... > Are the EU countries more welcoming to foreign workers then the USA ? What is the equivalent to the H1-B visa ? Does each EU country have a different visa requirement ? thanks for any info hamiltonArticle: 154668
hamilton wrote: > Are the EU countries more welcoming to foreign workers then the USA ? > > What is the equivalent to the H1-B visa ? > > Does each EU country have a different visa requirement ? > > thanks for any info I don't have information on other EU countries, but Germany at least is always trying to attract foreign talent. Instead of the US Green Card, they have the "Blue Card": http://www.bluecard-eu.de/ This is meant to simplify the process of well educated immigrants coming there to work. The language is usually not a problem either. Of course speaking German makes every-day life easier, but for work at tech companies English is usually sufficient, especially in the embedded sector. All the literature and such is in English anyway, so being proficient in English is mandatory for (software) engineers. German universities also offer a lot of engineering courses in English these days, so most young (software) engineers speak fluently. This is even less of a problem when you're working for one of the global players like Siemens, Bosch, Continental or the automotive industry (Mercedes-Benz, Porsche, BMW, Audi in southern Germany, Volkswagen up north), to bring up a few names that do a lot of work in embedded software. HTH, SeanArticle: 154669
HT-Lab wrote:
> On 13/12/2012 23:14, jonesandy@comcast.net wrote:
>> Ouch; state machines in schematics... that brings back some painful
>> memories.
>
> Interesting, I can't imagine designing state machines in anything else
> but schematics ;-)
Huh? Real electrical schematics? Are you sure?
> I use HDL Designer to quickly draw a bubble diagram and let the tool
> generate whatever HDL I want (VHDL/Verilog/1,2,3 process statemachine,
> sync/async reset, encoding style, etc.).
Oh, the state machine designer. Yes, that actually works, up to about
20 states. When you get up there, the page becomes VERY unwieldy,
and the self-documenting concept kind of falls apart. I tried it, ONCE,
and decided that:
if state = x1 then
if y=z then
state = x2
works a lot better.
Jon
Article: 154670We all know that a fifo should operate without getting empty or full. Does anybody have experience of what sort of output disorder can one expect when operating in the wrong state (underflow or overflow). I am asking that because naturally one thinks of some data samples getting lost when a fifo is in this wrong state but I am facing another output pattern at final system output and trying to find a cause. The pattern I get is an odd/even offset by some 8 samples in one case or every 8th sample duplicated in another case. For case1 if I realign that stream it gets correct so I am not actually losing samples. The system is too large and remotely tested and there is not much room to do any test at the time being. I have suspicion of a dc fifo in the path that may enter wrong state(underflow/overflow). It is altera dc fifo in stratix iv writing on ~368MHz clock and reading on ~245MHz, 32bits wide and 8 words deep. Any thoughts appreciated Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 154671
"kaz" <3619@embeddedrelated> wrote in message news:GLidnQK34ou08lHNnZ2dnUVZ_tGdnZ2d@giganews.com... > We all know that a fifo should operate without getting empty or full. Does > > anybody have experience of what sort of output disorder can one expect > when > operating in the wrong state (underflow or overflow). > > I am asking that because naturally one thinks of some data samples getting > lost > when a fifo is in this wrong state but I am facing another output pattern > at > final system output and trying to find a cause. The pattern I get is an > odd/even offset by some 8 samples in one case or every 8th sample > duplicated in > another case. For case1 if I realign that stream it gets correct so I am > not > actually losing samples. The system is too large and remotely tested and > there > is not much room to do any test at the time being. > > I have suspicion of a dc fifo in the path that may enter wrong > state(underflow/overflow). It is altera dc fifo in stratix iv writing on > ~368MHz clock and reading on ~245MHz, 32bits wide and 8 words deep. > > Any thoughts appreciated > > Kaz > I would never let a FIFO over or under flow. You should always stop writing to the FIFO if the full flag is set and discard the input data stream. If the empty flag is set you should not read from the FIFO - instead output known dummy data (invariably I output all zero's). Following this rule the behaviour of the FIFO is totally predictable. AndyArticle: 154672
> >I would never let a FIFO over or under flow. You should always stop writing >to the FIFO if the full flag is set and discard the input data stream. If >the empty flag is set you should not read from the FIFO - instead output >known dummy data (invariably I output all zero's). > >Following this rule the behaviour of the FIFO is totally predictable. > >Andy > Thanks Andy. No question that fifo is meant to be working away from underflow or overflow. What I am asking is there any known patterns that could emerge - after all - within this unpredictibility. Here I am asking about known symptoms of wrong behaviour really. Kaz --------------------------------------- Posted through http://www.FPGARelated.comArticle: 154673
"kaz" <3619@embeddedrelated> wrote in message news:AaydnUTdO7FfE1HNnZ2dnUVZ_iydnZ2d@giganews.com... > > >>I would never let a FIFO over or under flow. You should always stop > writing >>to the FIFO if the full flag is set and discard the input data stream. If > >>the empty flag is set you should not read from the FIFO - instead output >>known dummy data (invariably I output all zero's). >> >>Following this rule the behaviour of the FIFO is totally predictable. >> >>Andy >> > > Thanks Andy. No question that fifo is meant to be working away from > underflow > or overflow. What I am asking is there any known patterns that could > emerge > - after all - within this unpredictibility. Here I am asking about known > symptoms of wrong behaviour really. > > Kaz > Depends how the FIFO is constructed. If it is as a dual port RAM with an incrementable write pointer on the input port, and an incrementable read pointer on the output port then if you fill it to full - stop writing - then keep pulling data from the read port it will act as a circular buffer with data that will repeat over a number of cycles which will equal the FIFO length. You can work out other scenarios for this architecture yourself, for sure. AndyArticle: 154674
> >"kaz" <3619@embeddedrelated> wrote in message >news:AaydnUTdO7FfE1HNnZ2dnUVZ_iydnZ2d@giganews.com... >> > >>>I would never let a FIFO over or under flow. You should always stop >> writing >>>to the FIFO if the full flag is set and discard the input data stream. If >> >>>the empty flag is set you should not read from the FIFO - instead output >>>known dummy data (invariably I output all zero's). >>> >>>Following this rule the behaviour of the FIFO is totally predictable. >>> >>>Andy >>> >> >> Thanks Andy. No question that fifo is meant to be working away from >> underflow >> or overflow. What I am asking is there any known patterns that could >> emerge >> - after all - within this unpredictibility. Here I am asking about known >> symptoms of wrong behaviour really. >> >> Kaz >> > >Depends how the FIFO is constructed. > >If it is as a dual port RAM with an incrementable write pointer on the input >port, and an incrementable read pointer on the output port then if you fill >it to full - stop writing - then keep pulling data from the read port it >will act as a circular buffer with data that will repeat over a number of >cycles which will equal the FIFO length. > >You can work out other scenarios for this architecture yourself, for sure. > >Andy > > > My crucial point is: Is there anyway this altera fifo will break up the stream into another stream with even samples ahead of its odd half by 8 samples? Kaz --------------------------------------- Posted through http://www.FPGARelated.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z