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Messages from 154425

Article: 154425
Subject: Re: TMDS CML PCB
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 29 Oct 2012 01:28:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
inv___ <3827@embeddedrelated> wrote:
 
>    I have problem with understanding differential nature of DC coupled CML
> pair in TDMS (DVI, HDMI). In DC coupled LVDS current flows from source
> through one wire of transmission line then through termination resistor and
> goes back through second line to source. So currents are equal and they
> flow in opposite direction. Loop is formed by source, differential pair and
> termination resistor. 

> In CML pair current flows only in one line at the
> same time, second line is disconnected. 

In TDMS, a line either changes state or not. But there are many signals
in the cable, and it arranges the transitions such that over all the
wires, an almost equal number transition in each direction. 
Well, that is from reading

http://en.wikipedia.org/wiki/Transition-minimized_differential_signaling

I didn't try counting all the combinations myself. 

For LVDS, it takes 2N wires to send N signals, where the two of a pair
either change state or not.  A lot of redundancy there.

TDMS sends 8 signals in 10 wires, each of which is in a twisted pair.
The code is designed to minimize the number of the 10 transitioning,
and so that most are in opposite direction. If not all are opposite,
the next unequal transition will be in the opposite direction.

Enough current will flow through the ground wires to keep EM radiation
down. 

> If I have understood it good return
> current has to flow in ground plane. Loop is formed by source, one line
> from differential pair, termination resistor, VCC plane, decoupling
> capacitor, ground plane. Does it make ground connection between for example
> two PCBs extremely crucial? Does sending TMDS signal through twisted pair
> CAT cable depends highly on good shield connection between systems because
> this is conductor through which return currents flow ?

Even in that case, the decoupling capacitors would keep the signals
away from the ground lines, but there would still be too much radiation.

Since one idea behind TDMS is to minimize EM radiation, that doesn't
seem likely.

-- glen

Article: 154426
Subject: Re: Re: Altera delivery
From: krw@att.bizzz
Date: Sun, 28 Oct 2012 21:28:44 -0400
Links: << >>  << T >>  << A >>
On Sat, 27 Oct 2012 19:39:22 -0400, rickman <gnuarm@gmail.com> wrote:

>On 10/27/2012 3:28 PM, krw@att.bizzz wrote:
>> On Fri, 26 Oct 2012 08:24:14 -0700, John Larkin
>> <jjlarkin@highNOTlandTHIStechnologyPART.com>  wrote:
>>
>>>
>>>
>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>>> GX65 and 95. Numbers like 20 weeks and worse.
>>>
>>> Is this specific to Altera, or to Arria parts? I wonder if all the
>>> cell phones and tablets and stuff are overloading the fabs.
>>
>> I've been told that everyone is cutting back production starts,
>> expecting 2010 redux if Obama is reelected.
>
>Geeze, can't you leave politics out of a technical thread?  Oh, I 
>forgot, this is sci.electronics.design!  Politics is always on topic...

Idiot, it *is* the reason given.  You really are a loser, like you boy
Obama.

Article: 154427
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sun, 28 Oct 2012 21:40:48 -0400
Links: << >>  << T >>  << A >>
On 10/28/2012 9:28 PM, krw@att.bizzz wrote:
> On Sat, 27 Oct 2012 19:39:22 -0400, rickman<gnuarm@gmail.com>  wrote:
>
>> On 10/27/2012 3:28 PM, krw@att.bizzz wrote:
>>> On Fri, 26 Oct 2012 08:24:14 -0700, John Larkin
>>> <jjlarkin@highNOTlandTHIStechnologyPART.com>   wrote:
>>>
>>>>
>>>>
>>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>>>> GX65 and 95. Numbers like 20 weeks and worse.
>>>>
>>>> Is this specific to Altera, or to Arria parts? I wonder if all the
>>>> cell phones and tablets and stuff are overloading the fabs.
>>>
>>> I've been told that everyone is cutting back production starts,
>>> expecting 2010 redux if Obama is reelected.
>>
>> Geeze, can't you leave politics out of a technical thread?  Oh, I
>> forgot, this is sci.electronics.design!  Politics is always on topic...
>
> Idiot, it *is* the reason given.  You really are a loser, like you boy
> Obama.

Oh yeah, like everyone hates Obama and thinks the world will end if he 
is elected.

Reminds me of the movie "Chinatown", at the end someone says something 
like, "Forget about it Jack, its Chinatown".  I should forget about it, 
this is just s.e.d.

Rick

Article: 154428
Subject: Re: Re: Altera delivery
From: krw@att.bizzz
Date: Sun, 28 Oct 2012 23:19:37 -0400
Links: << >>  << T >>  << A >>
On Sun, 28 Oct 2012 21:40:48 -0400, rickman <gnuarm@gmail.com> wrote:

>On 10/28/2012 9:28 PM, krw@att.bizzz wrote:
>> On Sat, 27 Oct 2012 19:39:22 -0400, rickman<gnuarm@gmail.com>  wrote:
>>
>>> On 10/27/2012 3:28 PM, krw@att.bizzz wrote:
>>>> On Fri, 26 Oct 2012 08:24:14 -0700, John Larkin
>>>> <jjlarkin@highNOTlandTHIStechnologyPART.com>   wrote:
>>>>
>>>>>
>>>>>
>>>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>>>>> GX65 and 95. Numbers like 20 weeks and worse.
>>>>>
>>>>> Is this specific to Altera, or to Arria parts? I wonder if all the
>>>>> cell phones and tablets and stuff are overloading the fabs.
>>>>
>>>> I've been told that everyone is cutting back production starts,
>>>> expecting 2010 redux if Obama is reelected.
>>>
>>> Geeze, can't you leave politics out of a technical thread?  Oh, I
>>> forgot, this is sci.electronics.design!  Politics is always on topic...
>>
>> Idiot, it *is* the reason given.  You really are a loser, like you boy
>> Obama.
>
>Oh yeah, like everyone hates Obama and thinks the world will end if he 
>is elected.

You really are an idiot's idiot.

>Reminds me of the movie "Chinatown", at the end someone says something 
>like, "Forget about it Jack, its Chinatown".  I should forget about it, 
>this is just s.e.d.

Good God, you're as stupid as Slowman.

Article: 154429
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: jg <j.m.granville@gmail.com>
Date: Sun, 28 Oct 2012 22:14:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Monday, October 29, 2012 8:52:06 AM UTC+13, rickman wrote:
>  
> Will this cause the power consumption to increase compared to a single 
> ended input driven digitally?

You would need to measure a part. 
Sweep both ways, which shows any Schmitt action.

Digital Inputs can draw a LOT of current near the threshold, and I've seen some even oscillate, and disturb other Logic.

Some LVC parts show well over 1mA.
I measured an Atmel ATF1502BE, at ~56uA, schmitt, and that was the best I've seen.

LVDS current drain will not be so voltage dependent, but they do need a bias current to set-up the whole differential IP. - and as they chase speed, do not expect that to be low-uA values.

Some of the better LVDS stages will actually deliver Rail-Rail IP, and some are N-FET only. Expect some hysteresis on these.


Article: 154430
Subject: Re: TMDS CML PCB
From: "inv___" <3827@embeddedrelated>
Date: Mon, 29 Oct 2012 06:37:01 -0500
Links: << >>  << T >>  << A >>
line is disconnected. 
>
>In TDMS, a line either changes state or not. But there are many signals
>in the cable, and it arranges the transitions such that over all the
>wires, an almost equal number transition in each direction. 
>Well, that is from reading
>
>http://en.wikipedia.org/wiki/Transition-minimized_differential_signaling

In specyfication of DVI I did not find anything that says that coding data
in one channel depends on data in other channels. Could you point me where
can I find how is it done ?

>I didn't try counting all the combinations myself. 
>
>For LVDS, it takes 2N wires to send N signals, where the two of a pair
>either change state or not.  A lot of redundancy there.
>
>TDMS sends 8 signals in 10 wires, each of which is in a twisted pair.
>The code is designed to minimize the number of the 10 transitioning,
>and so that most are in opposite direction. If not all are opposite,
>the next unequal transition will be in the opposite direction.

As I understood DVI specyfication there is one pair for reference clock
(pixel clock) and three for data (cahnnels for color). 8b/10b is used thats
true, but to code each octet in channel (additional 2 bits are used for
marking type of xor operation, negation for DC balance or they are used for
control signal coding, HSync, VSync). 

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 154431
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: rickman <gnuarm@gmail.com>
Date: Mon, 29 Oct 2012 14:07:31 -0400
Links: << >>  << T >>  << A >>
On 10/29/2012 1:14 AM, jg wrote:
> On Monday, October 29, 2012 8:52:06 AM UTC+13, rickman wrote:
>>
>> Will this cause the power consumption to increase compared to a single
>> ended input driven digitally?
>
> You would need to measure a part.
> Sweep both ways, which shows any Schmitt action.

I was hoping someone who has tried this trick might know how these 
inputs are made.  I'm told by the FAE there is no Schmitt.


> Digital Inputs can draw a LOT of current near the threshold, and I've seen some even oscillate, and disturb other Logic.

You are talking about single ended inputs.  A LVDS input normally 
operates in a small range near Vcc/2.  I don't expect the same level of 
power consumption that a standard input would have.  But I don't know 
how they switch between these modes and I expect that will impact it 
significantly.


> Some LVC parts show well over 1mA.
> I measured an Atmel ATF1502BE, at ~56uA, schmitt, and that was the best I've seen.
>
> LVDS current drain will not be so voltage dependent, but they do need a bias current to set-up the whole differential IP. - and as they chase speed, do not expect that to be low-uA values.

Yes, that is a major concern.  That could preclude the use of the LVDS 
input.


> Some of the better LVDS stages will actually deliver Rail-Rail IP, and some are N-FET only. Expect some hysteresis on these.
>

I'm trying to talk the FAE out of an eval board on the iCE65 parts which 
are already EOL'd.  With their focus on the iCE40 parts they should be 
willing to part with one of these if they still have any.  Then I can 
take some measurements.

Rick

Article: 154432
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Mon, 29 Oct 2012 18:42:55 +0000 (UTC)
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> wrote:

(snip)

> I'm trying to talk the FAE out of an eval board on the iCE65 parts which 
> are already EOL'd.  With their focus on the iCE40 parts they should be 
> willing to part with one of these if they still have any.  Then I can 
> take some measurements.

Tell them you will test it out and report good results to this group.

Of course, they would rather you not post the bad results, so it
will depend on how likely they think it is to work.

-- glen

Article: 154433
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: jg <j.m.granville@gmail.com>
Date: Mon, 29 Oct 2012 13:45:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Tuesday, October 30, 2012 7:42:55 AM UTC+13, glen herrmannsfeldt wrote:
> Tell them you will test it out and report good results to this group.
> 
> Of course, they would rather you not post the bad results, so it
> will depend on how likely they think it is to work.
> > 
> -- glen


- but if the iCE65 is EOL, why bother.

This is the sort of detail that could vary wildly between designs, so it wodl be best to check the parts/process you will actually use ?

There is a low cost iCE40 board - not sure if it includes LVDS silicon ?

If low power matters, I'd try a dual-slope over Sigma delta, as that allows uA opamps to be used, and avoids poorly spec'd Digital operation.



-jg



Article: 154434
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: rickman <gnuarm@gmail.com>
Date: Mon, 29 Oct 2012 17:17:48 -0400
Links: << >>  << T >>  << A >>
On 10/29/2012 4:45 PM, jg wrote:
> On Tuesday, October 30, 2012 7:42:55 AM UTC+13, glen herrmannsfeldt wrote:
>> Tell them you will test it out and report good results to this group.
>>
>> Of course, they would rather you not post the bad results, so it
>> will depend on how likely they think it is to work.
>>>
>> -- glen
>
>
> - but if the iCE65 is EOL, why bother.

This is basically a one off as a demonstration.  The iCE65 has better 
power figures at the low end.  I might try the iCE 40.  We'll see what I 
can get from the FAE.


> This is the sort of detail that could vary wildly between designs, so it wodl be best to check the parts/process you will actually use ?
>
> There is a low cost iCE40 board - not sure if it includes LVDS silicon ?
>
> If low power matters, I'd try a dual-slope over Sigma delta, as that allows uA opamps to be used, and avoids poorly spec'd Digital operation.

Dual-slope doesn't give much resolution unless you use a pretty low 
sample rate relative to the clock rate.  Or do I not understand 
dual-slope that well?

I still need to look at a few things.  It may turn out that I only need 
a 1 bit ADC without the complexity of the delta-sigma converter... but 
I'll still need the LVDS input as a comparitor.

Rick

Article: 154435
Subject: Re: Using LVDS Input for Delta Sigma ADC
From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Date: Mon, 29 Oct 2012 16:47:30 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 28, 8:52=A0pm, rickman <gnu...@gmail.com> wrote:
> I found an app note on the Lattice site about using the LVDS input as
> the input comparator. =A0My design is very low power and I am concerned
> about the power consumption of this input. =A0Typically inputs are not
> supposed to operate in the linear region as this draws extra power in a
> "shoot through" mode. =A0The LVDS spends its entire time in this region.
>
> Will this cause the power consumption to increase compared to a single
> ended input driven digitally?
>
> The parts I'm considering are the iCE40 and iCE65 chips from Lattice,
> formerly Silicon Blue. =A0The iCE65 is obsolete, but this is a proof of
> concept so I don't much care if I can't use it in production. =A0It has
> better leakage current specs.
>
> Rick

I don't know how valid it really is but:
http://www.patentgenius.com/patent/8212700.html

-Lasse

Article: 154436
Subject: Re: production life of Spartan3A ?
From: Gabor <gabor@szakacs.invalid>
Date: Wed, 31 Oct 2012 11:02:05 -0400
Links: << >>  << T >>  << A >>
Jon Elson wrote:
> Hello,
> 
> Anybody have any idea how much longer the Spartan 3A will be
> in production?  I'm hoping a good while, yet, as it appears to
> be the cheapest modest-size FPGA from Xilinx right now, about
> $8 for the XC3S50A in the TQFP144 package.
> 
> Thanks much in advance,
> 
> Jon

Just to kick up the dust a bit, today Xilinx announced that
Spartan 3 and 3E are not recommended for new designs.  3A
is safe for the moment...

-- Gabor

Article: 154437
Subject: Re: production life of Spartan3A ?
From: rickman <gnuarm@gmail.com>
Date: Wed, 31 Oct 2012 20:33:07 -0400
Links: << >>  << T >>  << A >>
On 10/31/2012 11:02 AM, Gabor wrote:
> Jon Elson wrote:
>> Hello,
>>
>> Anybody have any idea how much longer the Spartan 3A will be
>> in production? I'm hoping a good while, yet, as it appears to
>> be the cheapest modest-size FPGA from Xilinx right now, about
>> $8 for the XC3S50A in the TQFP144 package.
>>
>> Thanks much in advance,
>>
>> Jon
>
> Just to kick up the dust a bit, today Xilinx announced that
> Spartan 3 and 3E are not recommended for new designs. 3A
> is safe for the moment...

Certainly I can't speak for Xilinx, but in the past they have kept parts 
in production for many, many years.  I would bet that listing them as NR 
for new designs simply means they won't be supporting the parts in the 
new versions of the tools.  That is the first step to obsolescence.  The 
prices of these chips will rise considerably.  It typically is many 
years after that when the chips are discontinued and even then they turn 
the mask sets over to companies that specialize in producing old chips. 
  You could still buy XC3000 parts the last time I remember this being 
discussed here a few years ago.

Rick

Article: 154438
Subject: Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)
From: Elder <ih8sp4m@yahoo.com>
Date: Thu, 1 Nov 2012 10:42:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi.

I want to verify if it is possible to use the CE10 to replace the CE15. Som=
e pins that are GND or VCCIO/VCCINT/VCCA on the CE15 are IOs on the CE10. T=
he GNDs are not a problem. But pins connected to VCCINT are as 1.2V are in =
the undefined input voltage range (VCCIOs are 3.15V in my design.) I will n=
ot define these pins in my project unless I have to.

Another concern is that a pin that was used as clock input (100MHz) is CLK1=
0 on the CE15 is a regular IO on the CE10. Could that be an issue?

Thanks for your inputs.



Article: 154439
Subject: Re: Altera FPGA: EP4CE10 as drop-in replacement for EP4CE15 (F17)
From: jonesandy@comcast.net
Date: Fri, 2 Nov 2012 07:54:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
You may be able to select an IO standard for the pin(s) that will be connec=
ted to VCCINT, such that 1.2V is safely within a valid input range. That wo=
uld likely require defining those pins in order to constrain them.

The clock should only be an issue if you have any intputs or outputs for wh=
ich timing relative to that clock input is critical (e.g. if the FPGA commu=
nicates with some other device that shares the same board-level clock signa=
l, or buffered versions thereof).

Andy

Article: 154440
Subject: Re: production life of Spartan3A ?
From: jg <j.m.granville@gmail.com>
Date: Fri, 2 Nov 2012 11:33:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Thursday, October 25, 2012 7:59:56 AM UTC+13, Jon Elson wrote:
> So, nobody has any ideas for about how long the Spartan 3A
> will be available?  I'm just redoing a board to move up from
> the Spartan 2E.  The Spartan 6 gives me no advantages at all,
> costs more, and needs a (much) bigger config ROM.

Ask Xilinx which packages are the most popular ?
Vendors can sometimes prune niche, low volume packages before they prune the die.
I see the 3A and 3E are in the Automotive line as well, which helps lifetime.

You could also check you can compile for variants, like the 3AN, and also one-size-up, as that gives you more 'alternate sources'.
Another effect to watch for, as devices hit the volume tail, is a large user vacuum effect, so some alternate part codes is a good idea.

-jg


Article: 154441
Subject: help
From: mehdi bousfiha <el.mehdi.bousfiha@gmail.com>
Date: Sat, 3 Nov 2012 18:14:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi everyone, i'm realy excited about starting my first project in VHDl prog=
ramming, by using FPGA card, my project is about monitoring cameras, and i =
didn't find any information about it, basiclly i'm realy confused about sta=
rting this project without any guides or information sources, it's my first=
 step trought materials and FPGA card, except some basic tranings on it, i =
hope someone will help me to get what i need.

Thank you in advance.

Article: 154442
Subject: Re: help
From: rickman <gnuarm@gmail.com>
Date: Sat, 03 Nov 2012 21:28:30 -0400
Links: << >>  << T >>  << A >>
On 11/3/2012 9:14 PM, mehdi bousfiha wrote:
> Hi everyone, i'm realy excited about starting my first project in VHDl programming, by using FPGA card, my project is about monitoring cameras, and i didn't find any information about it, basiclly i'm realy confused about starting this project without any guides or information sources, it's my first step trought materials and FPGA card, except some basic tranings on it, i hope someone will help me to get what i need.
>
> Thank you in advance.

That's not much info to go on to help you.  You should probably start 
with some simple projects to learn the nature of FPGAs and how to use 
the tools, then work you way up to more complex projects until you 
understand enough to tackle a project like image processing.

There are any number of starter pages on the web.  A common project is a 
traffic light controller.

What exactly do you want to do with the cameras?

Rick

Article: 154443
Subject: Re: help
From: mehdi bousfiha <el.mehdi.bousfiha@gmail.com>
Date: Sat, 3 Nov 2012 19:00:50 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
> Hi everyone, i'm realy excited about starting my first project in VHDl pr=
ogramming, by using FPGA card, my project is about monitoring cameras, and =
i didn't find any information about it, basiclly i'm realy confused about s=
tarting this project without any guides or information sources, it's my fir=
st step trought materials and FPGA card, except some basic tranings on it, =
i hope someone will help me to get what i need.
>=20
>=20
>=20
> Thank you in advance.

first of all thank you for your reply,=20
My project is about surveillance camera, it means a camera that can stock a=
 video, and only on a presence of mouvement, and after that we can display =
these sequence of videos on a LCD screen=20

Article: 154444
Subject: Lowest Power Design in an FPGA
From: rickman <gnuarm@gmail.com>
Date: Sat, 03 Nov 2012 23:40:12 -0400
Links: << >>  << T >>  << A >>
What is the lowest power design you have done in an FPGA or CPLD?  There 
have been some very low power devices on the market for a number of 
years now.  I assume there have been some designs that push the power 
consumption to new lows in various "zero power" parts.

What design did you do that was very power sensitive, what parts did you 
use and how low did you get your power consumption?

Did you use any special tricks to get the power lower than you thought 
possible?  Were you able to meet the goals you estimated before you did 
the design?  In other words, any surprises?

Did you learn any limitations of the parts in what you could do in low 
power modes?  Features you couldn't use or ways the parts didn't work as 
well as expected?

One thing that has occurred to me is that many RAM based parts have to 
be configured.  This often takes a fair amount of power that might be a 
lot more than zero.  Is there any way to stretch this out so the rate of 
configuration reduces the power level?

Rick

Article: 154445
Subject: Re: help
From: Robert Miles <robertmilesxyz@gmail.com>
Date: Sat, 3 Nov 2012 22:56:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote:
> On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
>=20
> > Hi everyone, i'm realy excited about starting my first project in VHDl =
programming, by using FPGA card, my project is about monitoring cameras, an=
d i didn't find any information about it, basiclly i'm realy confused about=
 starting this project without any guides or information sources, it's my f=
irst step trought materials and FPGA card, except some basic tranings on it=
, i hope someone will help me to get what i need.
>=20
> > Thank you in advance.
>=20
> first of all thank you for your reply,=20
>=20
> My project is about surveillance camera, it means a camera that can stock=
 a video, and only on a presence of mouvement, and after that we can displa=
y these sequence of videos on a LCD screen

Is the wind blowing enough to move lightweight objects enough that it shoul=
d be displayed?


Article: 154446
Subject: Re: help
From: mehdi bousfiha <el.mehdi.bousfiha@gmail.com>
Date: Sun, 4 Nov 2012 01:59:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote:
> On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote:
>=20
> > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
>=20
> >=20
>=20
> > > Hi everyone, i'm realy excited about starting my first project in VHD=
l programming, by using FPGA card, my project is about monitoring cameras, =
and i didn't find any information about it, basiclly i'm realy confused abo=
ut starting this project without any guides or information sources, it's my=
 first step trought materials and FPGA card, except some basic tranings on =
it, i hope someone will help me to get what i need.
>=20
> >=20
>=20
> > > Thank you in advance.
>=20
> >=20
>=20
> > first of all thank you for your reply,=20
>=20
> >=20
>=20
> > My project is about surveillance camera, it means a camera that can sto=
ck a video, and only on a presence of mouvement, and after that we can disp=
lay these sequence of videos on a LCD screen
>=20
>=20
>=20
> Is the wind blowing enough to move lightweight objects enough that it sho=
uld be displayed?

We suppose that the camera is inside a building, such details are far from =
what i want, i need the first steps 

Article: 154447
Subject: Re: help
From: "Andy Bartlett" <andyb@nospam.net>
Date: Sun, 4 Nov 2012 10:18:17 -0000
Links: << >>  << T >>  << A >>

"mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message 
news:edbf8b3f-72af-4f9c-b170-b88283a28cc6@googlegroups.com...
On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote:
> On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote:
>
> > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
>
> >
>
> > > Hi everyone, i'm realy excited about starting my first project in VHDl 
> > > programming, by using FPGA card, my project is about monitoring 
> > > cameras, and i didn't find any information about it, basiclly i'm 
> > > realy confused about starting this project without any guides or 
> > > information sources, it's my first step trought materials and FPGA 
> > > card, except some basic tranings on it, i hope someone will help me to 
> > > get what i need.
>
> >
>
> > > Thank you in advance.
>
> >
>
> > first of all thank you for your reply,
>
> >
>
> > My project is about surveillance camera, it means a camera that can 
> > stock a video, and only on a presence of mouvement, and after that we 
> > can display these sequence of videos on a LCD screen
>
>
>
> Is the wind blowing enough to move lightweight objects enough that it 
> should be displayed?

>We suppose that the camera is inside a building, such details are far from 
>what i want, i need the first steps

OK one step at a time.

What are the cameras you wish to use - are they analog or digital output?
 If they are analog then what format of video do they provide?
If baseband then probably either RS170 or CCIR. You need to read up and 
understand these video formats, then you will need to build an Analog to 
digital converter to allow you to interface to the FPGA - how many bits? - 
you need to understand sampling theory to get a handle on the conversion 
rate you will need to preserve the analog bandwidth, and understand what 
level of quantization you will need.

Having got the digitised input to the FPGA you will need to strip the sync 
pulses from it to allow you to form the images properly into some kind of 
frame store. You probably (almost certainly) will not have enough memory on 
the FPGA for a frame store, so you will need external memory.

This will probably be DRAM or SDRAM. You need to define the devices your 
need, speed and capacity, and understand how to drive the memory devices 
from your FPGA.

If the cameras are digital - what format - camera link? Ethernet? 
proprietary?

We have not even scratched the surface yet.

You need to do some background work and system design first before you even 
think about coding the FPGA.

Just a few thoughts ...




Article: 154448
Subject: Re: help
From: mehdi bousfiha <el.mehdi.bousfiha@gmail.com>
Date: Sun, 4 Nov 2012 05:31:15 -0800 (PST)
Links: << >>  << T >>  << A >>
On Sunday, November 4, 2012 10:18:14 AM UTC, Andy Bartlett wrote:
> "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message 
> 
> news:edbf8b3f-72af-4f9c-b170-b88283a28cc6@googlegroups.com...
> 
> On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote:
> 
> > On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote:
> 
> >
> 
> > > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
> 
> >
> 
> > >
> 
> >
> 
> > > > Hi everyone, i'm realy excited about starting my first project in VHDl 
> 
> > > > programming, by using FPGA card, my project is about monitoring 
> 
> > > > cameras, and i didn't find any information about it, basiclly i'm 
> 
> > > > realy confused about starting this project without any guides or 
> 
> > > > information sources, it's my first step trought materials and FPGA 
> 
> > > > card, except some basic tranings on it, i hope someone will help me to 
> 
> > > > get what i need.
> 
> >
> 
> > >
> 
> >
> 
> > > > Thank you in advance.
> 
> >
> 
> > >
> 
> >
> 
> > > first of all thank you for your reply,
> 
> >
> 
> > >
> 
> >
> 
> > > My project is about surveillance camera, it means a camera that can 
> 
> > > stock a video, and only on a presence of mouvement, and after that we 
> 
> > > can display these sequence of videos on a LCD screen
> 
> >
> 
> >
> 
> >
> 
> > Is the wind blowing enough to move lightweight objects enough that it 
> 
> > should be displayed?
> 
> 
> 
> >We suppose that the camera is inside a building, such details are far from 
> 
> >what i want, i need the first steps
> 
> 
> 
> OK one step at a time.
> 
> 
> 
> What are the cameras you wish to use - are they analog or digital output?
> 
>  If they are analog then what format of video do they provide?
> 
> If baseband then probably either RS170 or CCIR. You need to read up and 
> 
> understand these video formats, then you will need to build an Analog to 
> 
> digital converter to allow you to interface to the FPGA - how many bits? - 
> 
> you need to understand sampling theory to get a handle on the conversion 
> 
> rate you will need to preserve the analog bandwidth, and understand what 
> 
> level of quantization you will need.
> 
> 
> 
> Having got the digitised input to the FPGA you will need to strip the sync 
> 
> pulses from it to allow you to form the images properly into some kind of 
> 
> frame store. You probably (almost certainly) will not have enough memory on 
> 
> the FPGA for a frame store, so you will need external memory.
> 
> 
> 
> This will probably be DRAM or SDRAM. You need to define the devices your 
> 
> need, speed and capacity, and understand how to drive the memory devices 
> 
> from your FPGA.
> 
> 
> 
> If the cameras are digital - what format - camera link? Ethernet? 
> 
> proprietary?
> 
> 
> 
> We have not even scratched the surface yet.
> 
> 
> 
> You need to do some background work and system design first before you even 
> 
> think about coding the FPGA.
> 
> 
> 
> Just a few thoughts ...

OK i see, So what are you suggestions for a beginner like me, i'm realy excited about building my own project, and i'll work hard to realize that, i juste need support and a push from professional people like you.
any ideas for easy projects ?? 

Article: 154449
Subject: Re: help
From: "Andy Bartlett" <andyb@nospam.net>
Date: Sun, 4 Nov 2012 15:21:16 -0000
Links: << >>  << T >>  << A >>

"mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message 
news:fc33de64-691d-4193-ad81-dc7ed266e52f@googlegroups.com...
> On Sunday, November 4, 2012 10:18:14 AM UTC, Andy Bartlett wrote:
>> "mehdi bousfiha" <el.mehdi.bousfiha@gmail.com> wrote in message
>>
>> news:edbf8b3f-72af-4f9c-b170-b88283a28cc6@googlegroups.com...
>>
>> On Sunday, November 4, 2012 5:56:12 AM UTC, Robert Miles wrote:
>>
>> > On Saturday, November 3, 2012 9:00:50 PM UTC-5, mehdi bousfiha wrote:
>>
>> >
>>
>> > > On Sunday, November 4, 2012 1:14:23 AM UTC, mehdi bousfiha wrote:
>>
>> >
>>
>> > >
>>
>> >
>>
>> > > > Hi everyone, i'm realy excited about starting my first project in 
>> > > > VHDl
>>
>> > > > programming, by using FPGA card, my project is about monitoring
>>
>> > > > cameras, and i didn't find any information about it, basiclly i'm
>>
>> > > > realy confused about starting this project without any guides or
>>
>> > > > information sources, it's my first step trought materials and FPGA
>>
>> > > > card, except some basic tranings on it, i hope someone will help me 
>> > > > to
>>
>> > > > get what i need.
>>
>> >
>>
>> > >
>>
>> >
>>
>> > > > Thank you in advance.
>>
>> >
>>
>> > >
>>
>> >
>>
>> > > first of all thank you for your reply,
>>
>> >
>>
>> > >
>>
>> >
>>
>> > > My project is about surveillance camera, it means a camera that can
>>
>> > > stock a video, and only on a presence of mouvement, and after that we
>>
>> > > can display these sequence of videos on a LCD screen
>>
>> >
>>
>> >
>>
>> >
>>
>> > Is the wind blowing enough to move lightweight objects enough that it
>>
>> > should be displayed?
>>
>>
>>
>> >We suppose that the camera is inside a building, such details are far 
>> >from
>>
>> >what i want, i need the first steps
>>
>>
>>
>> OK one step at a time.
>>
>>
>>
>> What are the cameras you wish to use - are they analog or digital output?
>>
>>  If they are analog then what format of video do they provide?
>>
>> If baseband then probably either RS170 or CCIR. You need to read up and
>>
>> understand these video formats, then you will need to build an Analog to
>>
>> digital converter to allow you to interface to the FPGA - how many 
>> bits? -
>>
>> you need to understand sampling theory to get a handle on the conversion
>>
>> rate you will need to preserve the analog bandwidth, and understand what
>>
>> level of quantization you will need.
>>
>>
>>
>> Having got the digitised input to the FPGA you will need to strip the 
>> sync
>>
>> pulses from it to allow you to form the images properly into some kind of
>>
>> frame store. You probably (almost certainly) will not have enough memory 
>> on
>>
>> the FPGA for a frame store, so you will need external memory.
>>
>>
>>
>> This will probably be DRAM or SDRAM. You need to define the devices your
>>
>> need, speed and capacity, and understand how to drive the memory devices
>>
>> from your FPGA.
>>
>>
>>
>> If the cameras are digital - what format - camera link? Ethernet?
>>
>> proprietary?
>>
>>
>>
>> We have not even scratched the surface yet.
>>
>>
>>
>> You need to do some background work and system design first before you 
>> even
>>
>> think about coding the FPGA.
>>
>>
>>
>> Just a few thoughts ...
>
> OK i see, So what are you suggestions for a beginner like me, i'm realy 
> excited about building my own project, and i'll work hard to realize that, 
> i juste need support and a push from professional people like you.
> any ideas for easy projects ??

As rickman suggested earlier - perhaps a traffic light controller.

You need to walk before you run - understand the fundamentals.

Personally I would suggest:-

1) Flashing LED - say 1Hz, 500ms on, 500ms off based on your system clock.

2) A counter that drives a decoder/seven segment display, using your 1Hz 
output from 1)

3) A frequency counter - drives the seven segment decoder/display from 2) 
and measures the frequency from 1)

When you have got that all going come back for some more help.

Andy 





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