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Messages from 154400

Article: 154400
Subject: RE: Xilinx Xact software for XC2018 Logic Cell Array
From: mark2112 <mark@micro-nova.com>
Date: Thu, 25 Oct 2012 13:45:58 -0500
Links: << >>  << T >>  << A >>
My friend and I made an FPGA module that may fit your needs. It packs a Spartan-3A XC3S200A onto a breadboard-friendly 64-pin DIP package - super easy to integrate into your own project! No need to solder any small packages by hand!

It has all the necessary support circuitry for the FPGA; it has the 1.2V and 3.3V voltage rails, bypass capacitors, and Flash to hold your configuration, and is programmable via USB. It also has 5V-tolerant I/O and an onboard 8-channel analog-to-digital converter!

Check it out at: http://micro-nova.com/mercury

--http://compgroups.net/comp.arch.fpga/xilinx-xact-software-for-xc2018-logic-cell-arr/107329



Article: 154401
Subject: Re: production life of Spartan3A ?
From: Jon Elson <jmelson@wustl.edu>
Date: Thu, 25 Oct 2012 14:17:53 -0500
Links: << >>  << T >>  << A >>
Gabor wrote:


> The problem with "nearly forever" is that the end date isn't actually
> set by Xilinx, but by the end-of life for the fab process.  Xilinx at
> one point announced a general EOL for Spartan 2, then changed
> their mind.  Not that long ago, Spartan 2e was actually the lowest
> priced Xilinx part per IOB. For many small applications the IOB count
> limits the device selection.  So even after Spartan 3 came out with
> great fanfare as the lowest cost device (per LUT), Spartan 2e still
> had better per-IOB price.
> 
Thanks all (Rob, Rick and Gabor) for your guesses - yes, I know all
you can do is guess on this, but you might have better "ear to the ground"
sources of info than I do.

Yes, I am JUST moving some products from Spartan 2E to the 3A, as 2E cost
is going up and I don't want to get caught scrambling for trailing-edge
parts.

I figured out how to use SST serial-PROMs on the 2E with just a couple
SSI chips.  These are FAR cheaper than Xilinx's offerings.  The Spartan
3A supports these chips with no additional logic.

I have some legacy designs that compile on iSE 10.1, and I only needed
the slightest tweaks to get them to compile for the S3A, other than
completely remapping the UCF pin assignments.

Knowing the quirks of the design package and having a design that already
is acceptable on that package made the change pretty easy.  Moving to
a different vendor is a last resort.  Compatibility issues, learning
new software, learning the quirks of a new vendor's chips, etc.  Even
learning how to navigate through different data sheets would be some
amount of effort.

So, I'd need a fairly big push to move to another vendor right now,
but thanks for the info.  I really ought to look at Lattice again.

Jon

Article: 154402
Subject: Re: production life of Spartan3A ?
From: rickman <gnuarm@gmail.com>
Date: Thu, 25 Oct 2012 20:15:13 -0400
Links: << >>  << T >>  << A >>
On 10/25/2012 3:17 PM, Jon Elson wrote:
>
> So, I'd need a fairly big push to move to another vendor right now,
> but thanks for the info.  I really ought to look at Lattice again.
>
> Jon

That is one big reason why I don't make an effort to use vendor specific 
features.  If the tools automatically generate the bits to use SRLs or 
other vendor specific features then fine, go with it.  But if I have to 
jump through hoops, I leave them alone.  Even if you don't port a 
design, it is not uncommon to reuse existing code on new designs.

Rick

Article: 154403
Subject: Altera delivery
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 26 Oct 2012 08:24:14 -0700
Links: << >>  << T >>  << A >>


We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
GX65 and 95. Numbers like 20 weeks and worse.

Is this specific to Altera, or to Arria parts? I wonder if all the
cell phones and tablets and stuff are overloading the fabs.



-- 

John Larkin                  Highland Technology Inc
www.highlandtechnology.com   jlarkin at highlandtechnology dot com   

Precision electronic instrumentation
Picosecond-resolution Digital Delay and Pulse generators
Custom timing and laser controllers
Photonics and fiberoptic TTL data links
VME  analog, thermocouple, LVDT, synchro, tachometer
Multichannel arbitrary waveform generators

Article: 154404
Subject: Re: production life of Spartan3A ?
From: Jon Elson <jmelson@wustl.edu>
Date: Fri, 26 Oct 2012 14:16:22 -0500
Links: << >>  << T >>  << A >>
rickman wrote:


> That is one big reason why I don't make an effort to use vendor specific
> features.  If the tools automatically generate the bits to use SRLs or
> other vendor specific features then fine, go with it.  But if I have to
> jump through hoops, I leave them alone.  Even if you don't port a
> design, it is not uncommon to reuse existing code on new designs.

Other than pull-ups and the method of implementing a tri-state I/O pin,
I'm not doing anything that could be considered vendor specific.  No
location locking, specifying carry chains or anything.  But, I HATE
learning new software, after all the trouble of learning ALL the quirks
on one program.  I hate even changing versions, as there are all new
quirks to discover.

Some of the designs are descended from mostly schematic entry projects
that were done in 2001.  I have them all converted to a mix of behavioral
and architectural VHDL, and the architectural stuff is a horrible
nightmare.  I hated the old Aldec shematic editor in Xilinx Foundation,
and went and patched up Protel's libraries so I could create the schematics
in Protel 99SE's schematic editor and export as VHDL.  Well, looking back,
that was one of the worst ideas I ever had!  If you want to edit the
schematic, you have to then hand-edit the architectural VHDL to make it
compatible with Xilinx, so I just edited the VHDL files, which are a huge
jumble.  When they get bad enough, I finally break down and convert them
to behavioral VHDL, which I should have done from the beginning.

So, I have no idea how these architectural VHDL files would work on
anybody else's tools.  But, I wouldn't be surprised if there were
problems.

Jon

Article: 154405
Subject: Re: production life of Spartan3A ?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 26 Oct 2012 20:22:37 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jon Elson <jmelson@wustl.edu> wrote:
 
(snip)

> Some of the designs are descended from mostly schematic entry projects
> that were done in 2001.  I have them all converted to a mix of behavioral
> and architectural VHDL, and the architectural stuff is a horrible
> nightmare.  I hated the old Aldec shematic editor in Xilinx Foundation,
> and went and patched up Protel's libraries so I could create the schematics
> in Protel 99SE's schematic editor and export as VHDL.  Well, looking back,
> that was one of the worst ideas I ever had!  

Conversion from schematic entry is nice, but the results
aren't usually very human readable. 

> If you want to edit the
> schematic, you have to then hand-edit the architectural VHDL to make it
> compatible with Xilinx, so I just edited the VHDL files, which are a huge
> jumble.  When they get bad enough, I finally break down and convert them
> to behavioral VHDL, which I should have done from the beginning.

I don't know VHDL well enough to say, but except for registers
and state machines, I prefer strutural (mostly continuous assignment)
verilog to behavioral verilog. 
 
> So, I have no idea how these architectural VHDL files would work on
> anybody else's tools.  But, I wouldn't be surprised if there were
> problems.

I don't know either, but if they follow the standard, then
they should work on any implementation that follows the standard.

-- glen

Article: 154406
Subject: Re: production life of Spartan3A ?
From: Jon Elson <elson@pico-systems.com>
Date: Fri, 26 Oct 2012 22:00:04 -0500
Links: << >>  << T >>  << A >>
glen herrmannsfeldt wrote:

> Jon Elson <jmelson@wustl.edu> wrote:

>> in Protel 99SE's schematic editor and export as VHDL.  Well, looking
>> back, that was one of the worst ideas I ever had!
> 
> Conversion from schematic entry is nice, but the results
> aren't usually very human readable.
> 
Yeah, that is clear to me NOW!

>> So, I have no idea how these architectural VHDL files would work on
>> anybody else's tools.  But, I wouldn't be surprised if there were
>> problems.
> 
> I don't know either, but if they follow the standard, then
> they should work on any implementation that follows the standard.
Well, I think they WON'T, because they make extensive use of the
Xilinx library unisim.vcomponents, which has all sorts of components
made out of standard primitives, like 3-input and gates with one inverted
input, multi-channel D-flops with all possible combinations of
clock enable, async or sync clear, etc.  I'm sure other tools
have similar libraries, but I'll bet they are all different, either
a little or a lot.  You can also build a design out of all 74xx
components from this library, but I didn't do that.

Jon

Article: 154407
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Oct 2012 06:37:36 -0400
Links: << >>  << T >>  << A >>
On 10/26/2012 11:24 AM, John Larkin wrote:
>
>
> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
> GX65 and 95. Numbers like 20 weeks and worse.
>
> Is this specific to Altera, or to Arria parts? I wonder if all the
> cell phones and tablets and stuff are overloading the fabs.

Since when do they use FPGAs in high volume stuff like cell phones or 
tablets?

I see FPGA supply vary all the time as well as other devices.  Once I 
couldn't get an AKM CODEC in the 8 week window I tend to rely on and the 
disti got AKM in the loop.  They said they had a reliable 14 week 
factory delivery as if that was something to brag about!  I'm a small 
player so all I can do is grin and say "thank you".

Rick

Article: 154408
Subject: Re: Altera delivery
From: krw@att.bizzz
Date: Sat, 27 Oct 2012 15:28:08 -0400
Links: << >>  << T >>  << A >>
On Fri, 26 Oct 2012 08:24:14 -0700, John Larkin
<jjlarkin@highNOTlandTHIStechnologyPART.com> wrote:

>
>
>We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>GX65 and 95. Numbers like 20 weeks and worse.
>
>Is this specific to Altera, or to Arria parts? I wonder if all the
>cell phones and tablets and stuff are overloading the fabs.

I've been told that everyone is cutting back production starts,
expecting 2010 redux if Obama is reelected.

Article: 154409
Subject: Re: Altera delivery
From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Date: Sat, 27 Oct 2012 12:47:32 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 27 Okt., 12:37, rickman <gnu...@gmail.com> wrote:
> On 10/26/2012 11:24 AM, John Larkin wrote:
>
>
>
> > We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
> > GX65 and 95. Numbers like 20 weeks and worse.
>
> > Is this specific to Altera, or to Arria parts? I wonder if all the
> > cell phones and tablets and stuff are overloading the fabs.
>
> Since when do they use FPGAs in high volume stuff like cell phones or
> tablets?
>

they don't, but as far I know Altera use TSMC, Xilinx UMC so they
compete for time at the fabs with the cell phone stuff

-Lasse

Article: 154410
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Oct 2012 16:01:16 -0400
Links: << >>  << T >>  << A >>
On 10/27/2012 3:47 PM, langwadt@fonz.dk wrote:
> On 27 Okt., 12:37, rickman<gnu...@gmail.com>  wrote:
>> On 10/26/2012 11:24 AM, John Larkin wrote:
>>
>>
>>
>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>>> GX65 and 95. Numbers like 20 weeks and worse.
>>
>>> Is this specific to Altera, or to Arria parts? I wonder if all the
>>> cell phones and tablets and stuff are overloading the fabs.
>>
>> Since when do they use FPGAs in high volume stuff like cell phones or
>> tablets?
>>
>
> they don't, but as far I know Altera use TSMC, Xilinx UMC so they
> compete for time at the fabs with the cell phone stuff
>
> -Lasse

That may be, but the fabs schedule production runs way, way in advance. 
  I'm sure Xilinx and Altera are at the head of the list when it comes 
to getting more share as well.  If there was a shortage, it would more 
likely be higher FPGA demand than it would be X or A getting cut out of 
their fab time.

Rick

Article: 154411
Subject: Re: Altera delivery
From: Michael S <already5chosen@yahoo.com>
Date: Sat, 27 Oct 2012 14:16:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 27, 10:01=A0pm, rickman <gnu...@gmail.com> wrote:
> On 10/27/2012 3:47 PM, langw...@fonz.dk wrote:
>
>
>
>
>
>
>
>
>
> > On 27 Okt., 12:37, rickman<gnu...@gmail.com> =A0wrote:
> >> On 10/26/2012 11:24 AM, John Larkin wrote:
>
> >>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
> >>> GX65 and 95. Numbers like 20 weeks and worse.
>
> >>> Is this specific to Altera, or to Arria parts? I wonder if all the
> >>> cell phones and tablets and stuff are overloading the fabs.
>
> >> Since when do they use FPGAs in high volume stuff like cell phones or
> >> tablets?
>
> > they don't, but as far I know Altera use TSMC, Xilinx UMC so they
> > compete for time at the fabs with the cell phone stuff
>
> > -Lasse
>
> That may be, but the fabs schedule production runs way, way in advance.
> =A0 I'm sure Xilinx and Altera are at the head of the list when it comes
> to getting more share as well.

Quallcomm is way more important than ether X or A.
Even NVidea and AMD are, at very least, as important as X&A.
Also, does not TI use TSMC for OMAP5? If true, it wouldn't affect
Arria2, since it uses older fabs, but could affect priority of 5-
series Altera products.

> =A0If there was a shortage, it would more
> likely be higher FPGA demand than it would be X or A getting cut out of
> their fab time.
>
> Rick

It's the same thing seen from different angle.
You have higher demand than was originally expected and then want to
get more waffers than what's already scheduled, but can't because you
are not the most important of TSMC customers.



Article: 154412
Subject: Re: Altera delivery
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Sat, 27 Oct 2012 15:09:05 -0700
Links: << >>  << T >>  << A >>
On Sat, 27 Oct 2012 06:37:36 -0400, rickman <gnuarm@gmail.com> wrote:

>On 10/26/2012 11:24 AM, John Larkin wrote:
>>
>>
>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>> GX65 and 95. Numbers like 20 weeks and worse.
>>
>> Is this specific to Altera, or to Arria parts? I wonder if all the
>> cell phones and tablets and stuff are overloading the fabs.
>
>Since when do they use FPGAs in high volume stuff like cell phones or 
>tablets?

They use silicon and wafer steppers. Both Xilinx and Altera are
fabless, so they have to compete for fab slots.

You would think, for $200 to $15,000 per FPGA, that they could get
their wafers fabbed.



Article: 154413
Subject: Re: Altera delivery
From: Michael S <already5chosen@yahoo.com>
Date: Sat, 27 Oct 2012 15:30:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 28, 12:09=A0am, John Larkin
<jjlar...@highNOTlandTHIStechnologyPART.com> wrote:
> On Sat, 27 Oct 2012 06:37:36 -0400, rickman <gnu...@gmail.com> wrote:
> >On 10/26/2012 11:24 AM, John Larkin wrote:
>
> >> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
> >> GX65 and 95. Numbers like 20 weeks and worse.
>
> >> Is this specific to Altera, or to Arria parts? I wonder if all the
> >> cell phones and tablets and stuff are overloading the fabs.
>
> >Since when do they use FPGAs in high volume stuff like cell phones or
> >tablets?
>
> They use silicon and wafer steppers. Both Xilinx and Altera are
> fabless, so they have to compete for fab slots.
>
> You would think, for $200 to $15,000 per FPGA, that they could get
> their wafers fabbed.

Except that selling price of Arria II GX65 to big customers is much
less than $200. And by die area it's no small chip.

Few years ago I heard about one not particularly big, but important
Altera customers getting Startix3-50E for $100 apiece. Stratix, not
Arria. Arria2 is considered mid-range rather than high-end, so I
wouldn't be surprised if really big customers are paying $60-$70 for
A2-GX65.


Article: 154414
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Oct 2012 19:26:09 -0400
Links: << >>  << T >>  << A >>
On 10/27/2012 5:16 PM, Michael S wrote:
> On Oct 27, 10:01 pm, rickman<gnu...@gmail.com>  wrote:
>> On 10/27/2012 3:47 PM, langw...@fonz.dk wrote:
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>> On 27 Okt., 12:37, rickman<gnu...@gmail.com>    wrote:
>>>> On 10/26/2012 11:24 AM, John Larkin wrote:
>>
>>>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>>>>> GX65 and 95. Numbers like 20 weeks and worse.
>>
>>>>> Is this specific to Altera, or to Arria parts? I wonder if all the
>>>>> cell phones and tablets and stuff are overloading the fabs.
>>
>>>> Since when do they use FPGAs in high volume stuff like cell phones or
>>>> tablets?
>>
>>> they don't, but as far I know Altera use TSMC, Xilinx UMC so they
>>> compete for time at the fabs with the cell phone stuff
>>
>>> -Lasse
>>
>> That may be, but the fabs schedule production runs way, way in advance.
>>    I'm sure Xilinx and Altera are at the head of the list when it comes
>> to getting more share as well.
>
> Quallcomm is way more important than ether X or A.
> Even NVidea and AMD are, at very least, as important as X&A.
> Also, does not TI use TSMC for OMAP5? If true, it wouldn't affect
> Arria2, since it uses older fabs, but could affect priority of 5-
> series Altera products.
>
>>   If there was a shortage, it would more
>> likely be higher FPGA demand than it would be X or A getting cut out of
>> their fab time.
>>
>> Rick
>
> It's the same thing seen from different angle.
> You have higher demand than was originally expected and then want to
> get more waffers than what's already scheduled, but can't because you
> are not the most important of TSMC customers.

I don't think any customers are the 600 lb gorilla.  A small customer 
might get displaced, but none of the large customers expect to have 
their schedules disrupted and none expect to be able to disrupt the 
schedules of the other gorillas.

Rick

Article: 154415
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Oct 2012 19:39:22 -0400
Links: << >>  << T >>  << A >>
On 10/27/2012 3:28 PM, krw@att.bizzz wrote:
> On Fri, 26 Oct 2012 08:24:14 -0700, John Larkin
> <jjlarkin@highNOTlandTHIStechnologyPART.com>  wrote:
>
>>
>>
>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>> GX65 and 95. Numbers like 20 weeks and worse.
>>
>> Is this specific to Altera, or to Arria parts? I wonder if all the
>> cell phones and tablets and stuff are overloading the fabs.
>
> I've been told that everyone is cutting back production starts,
> expecting 2010 redux if Obama is reelected.

Geeze, can't you leave politics out of a technical thread?  Oh, I 
forgot, this is sci.electronics.design!  Politics is always on topic...

Rick

Article: 154416
Subject: Re: Altera delivery
From: Michael S <already5chosen@yahoo.com>
Date: Sat, 27 Oct 2012 16:55:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 28, 1:26=A0am, rickman <gnu...@gmail.com> wrote:
> On 10/27/2012 5:16 PM, Michael S wrote:
>
>
>
>
>
>
>
>
>
> > On Oct 27, 10:01 pm, rickman<gnu...@gmail.com> =A0wrote:
> >> On 10/27/2012 3:47 PM, langw...@fonz.dk wrote:
>
> >>> On 27 Okt., 12:37, rickman<gnu...@gmail.com> =A0 =A0wrote:
> >>>> On 10/26/2012 11:24 AM, John Larkin wrote:
>
> >>>>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
> >>>>> GX65 and 95. Numbers like 20 weeks and worse.
>
> >>>>> Is this specific to Altera, or to Arria parts? I wonder if all the
> >>>>> cell phones and tablets and stuff are overloading the fabs.
>
> >>>> Since when do they use FPGAs in high volume stuff like cell phones o=
r
> >>>> tablets?
>
> >>> they don't, but as far I know Altera use TSMC, Xilinx UMC so they
> >>> compete for time at the fabs with the cell phone stuff
>
> >>> -Lasse
>
> >> That may be, but the fabs schedule production runs way, way in advance=
.
> >> =A0 =A0I'm sure Xilinx and Altera are at the head of the list when it =
comes
> >> to getting more share as well.
>
> > Quallcomm is way more important than ether X or A.
> > Even NVidea and AMD are, at very least, as important as X&A.
> > Also, does not TI use TSMC for OMAP5? If true, it wouldn't affect
> > Arria2, since it uses older fabs, but could affect priority of 5-
> > series Altera products.
>
> >> =A0 If there was a shortage, it would more
> >> likely be higher FPGA demand than it would be X or A getting cut out o=
f
> >> their fab time.
>
> >> Rick
>
> > It's the same thing seen from different angle.
> > You have higher demand than was originally expected and then want to
> > get more waffers than what's already scheduled, but can't because you
> > are not the most important of TSMC customers.
>
> I don't think any customers are the 600 lb gorilla.

But Qualcomm and Apple *are* 600 lb gorillas of fabless semico. That's
a fact of life.
Apple is currently on Samsung, but relationships between the two are
bad. So the switch is likely. And if Apple switches to TSMC then any
other TSMC client with exception of Qualcomm, and, possibly, Bradcom
and TI will look as a Lilliput. And even in Lilliput category, Altera
and Xilinx are smaller than Nvidea and AMD.


>=A0A small customer might get displaced, but none of the large customers e=
xpect to have
> their schedules disrupted and none expect to be able to disrupt the
> schedules of the other gorillas.
>
> Rick

Schedules of big Lilliput wouldn't be disrupted, but he can't expect
to get the same flexibility of allocation of the wafers as 600 lb
gorillas


Article: 154417
Subject: RTL simulation of Dynamic Partial Reconfiguration and Dynamically
From: "George (Lingkan) Gong" <george.gong.47@gmail.com>
Date: Sat, 27 Oct 2012 17:58:07 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

Are you working on Dynamic Partial Reconfiguration (DPR)? Are you strugglin=
g to get your DPR design working? Are you frustrated with using ChipScope?

I am a PhD student from the University of New South Wales, Australia, and I=
 am very interested in the Partially Reconfiguration, particularly the func=
tional verification of Partially Reconfigurable designs.=20

Similar to traditional static FPGA designs, DPR designs are also created by=
 writing Verilog/VHDL code. However, the design source can not be simulated=
 because HDL simulators do not support RTL simulation of partial reconfigur=
ation. Traditional HDL languages assume that the design hierarchy is define=
d at compile-time and can not be changed in the middle of a simulation run.=
=20

I am currently working on an open source library, ReSim, for simulation-bas=
ed functional verification of DPR designs. By compiling the library and you=
r design HDL source, you can perform cycle-accurate RTL simulation of your =
DPR design, including the partial reconfiguration process, in HDL simulator=
s such as ModelSim. The designer can view in the waveform window all the si=
gnal transitions during the reconfiguration process, such as the transfer o=
f the partial bitstreams and the subsequent swapping of reconfigurable modu=
les.

You can find my latest ReSim library on Google Code:=20

http://code.google.com/p/resim-simulating-partial-reconfiguration/

You are welcome to use it and I would be happy to hear from you any feedbac=
k of using the tool.

Thanks and Kind Regards,

Article: 154418
Subject: Re: Altera delivery
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sun, 28 Oct 2012 01:06:26 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote:

(snip)
> Since when do they use FPGAs in high volume stuff like cell phones or 
> tablets?
 
> I see FPGA supply vary all the time as well as other devices.  Once I 
> couldn't get an AKM CODEC in the 8 week window I tend to rely on and the 
> disti got AKM in the loop.  They said they had a reliable 14 week 
> factory delivery as if that was something to brag about!  I'm a small 
> player so all I can do is grin and say "thank you".

Since ASIC mask costs went over $1e6 or so, and FPGA prices
fell enough to make it cost effective.

Besides, with an ASIC you are stuck with that design for
a long time, but with FPGA you can change to follow
what is popular.

-- glen

Article: 154419
Subject: Re: Altera delivery
From: rickman <gnuarm@gmail.com>
Date: Sat, 27 Oct 2012 21:25:04 -0400
Links: << >>  << T >>  << A >>
On 10/27/2012 9:06 PM, glen herrmannsfeldt wrote:
> In comp.arch.fpga rickman<gnuarm@gmail.com>  wrote:
>
> (snip)
>> Since when do they use FPGAs in high volume stuff like cell phones or
>> tablets?
>
>> I see FPGA supply vary all the time as well as other devices.  Once I
>> couldn't get an AKM CODEC in the 8 week window I tend to rely on and the
>> disti got AKM in the loop.  They said they had a reliable 14 week
>> factory delivery as if that was something to brag about!  I'm a small
>> player so all I can do is grin and say "thank you".
>
> Since ASIC mask costs went over $1e6 or so, and FPGA prices
> fell enough to make it cost effective.
>
> Besides, with an ASIC you are stuck with that design for
> a long time, but with FPGA you can change to follow
> what is popular.
>
> -- glen

Isn't a megabuck still in the noise for cell phones and tablets? 
Gartner and IDC say there were 1.5 *Billion* cell phones sold in the 
world in 2011!  I'll bet damn few of them contained any FPGAs.  That is 
what Silicon Blue (now part of Lattice) was trying to change, but I 
don't know how successful they are in that particular market selling 
$1-2 parts.

Have you seen any teardowns of tablets or cell phones with FPGAs in 
them?  I haven't.

Rick

Article: 154420
Subject: Re: Altera delivery
From: Jon Elson <elson@pico-systems.com>
Date: Sat, 27 Oct 2012 22:27:54 -0500
Links: << >>  << T >>  << A >>
John Larkin wrote:


> You would think, for $200 to $15,000 per FPGA, that they could get
> their wafers fabbed.
I see those $7K to 15K FPGAs in the distributor listings, and wonder
WHO the hell can afford a $7K or more chip?  I'm guessing some
simulation farms and NSA code crackers have good reason for such
chips, but that must be a fairly small niche market, no?  Obviously,
no such chip ever winds up in consumer gear.

Jon

Article: 154421
Subject: Re: Altera delivery
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Sun, 28 Oct 2012 04:22:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
In comp.arch.fpga rickman <gnuarm@gmail.com> wrote:

(snip)
>> Since ASIC mask costs went over $1e6 or so, and FPGA prices
>> fell enough to make it cost effective.

>> Besides, with an ASIC you are stuck with that design for
>> a long time, but with FPGA you can change to follow
>> what is popular.
 
> Isn't a megabuck still in the noise for cell phones and tablets? 
> Gartner and IDC say there were 1.5 *Billion* cell phones sold in the 
> world in 2011!  I'll bet damn few of them contained any FPGAs.  That is 
> what Silicon Blue (now part of Lattice) was trying to change, but I 
> don't know how successful they are in that particular market selling 
> $1-2 parts.

Maybe true, but FPGAs are going in many places that would have
been custom ASICs not so long ago. 
 
> Have you seen any teardowns of tablets or cell phones with FPGAs in 
> them?  I haven't.

I haven't followed the teardowns closely at all.

-- glen

Article: 154422
Subject: Re: Altera delivery
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 28 Oct 2012 16:40:50 +0000 (GMT)
Links: << >>  << T >>  << A >>
In article <k6hcb9$tc1$4@dont-email.me>, rickman  <gnuarm@gmail.com> wrote:
>On 10/26/2012 11:24 AM, John Larkin wrote:
>>
>>
>> We are seeing huge leadtimes on Altera FPGAs, specifically Arria II
>> GX65 and 95. Numbers like 20 weeks and worse.
>>
>> Is this specific to Altera, or to Arria parts? I wonder if all the
>> cell phones and tablets and stuff are overloading the fabs.
>
>Since when do they use FPGAs in high volume stuff like cell phones or 
>tablets?

It used to be that a fair number were used in LCD TVs: meant you could
get your panels from wherever panels were cheapest that day and
program the FPGA to drive that particular panel type.  I suspect that
there's been enough of a shakeout in the LCD TV factory world that
there are now very few panel types and not much of a spot market for
them.

Tom

Article: 154423
Subject: Using LVDS Input for Delta Sigma ADC
From: rickman <gnuarm@gmail.com>
Date: Sun, 28 Oct 2012 15:51:49 -0400
Links: << >>  << T >>  << A >>
I found an app note on the Lattice site about using the LVDS input as 
the input comparator.  My design is very low power and I am concerned 
about the power consumption of this input.  Typically inputs are not 
supposed to operate in the linear region as this draws extra power in a 
"shoot through" mode.  The LVDS spends its entire time in this region.

Will this cause the power consumption to increase compared to a single 
ended input driven digitally?

The parts I'm considering are the iCE40 and iCE65 chips from Lattice, 
formerly Silicon Blue.  The iCE65 is obsolete, but this is a proof of 
concept so I don't much care if I can't use it in production.  It has 
better leakage current specs.

Rick

Article: 154424
Subject: TMDS CML PCB
From: "inv___" <3827@embeddedrelated>
Date: Sun, 28 Oct 2012 19:26:10 -0500
Links: << >>  << T >>  << A >>
Hello,

    I have problem with understanding differential nature of DC coupled CML
pair in TDMS (DVI, HDMI). In DC coupled LVDS current flows from source
through one wire of transmission line then through termination resistor and
goes back through second line to source. So currents are equal and they
flow in opposite direction. Loop is formed by source, differential pair and
termination resistor. In CML pair current flows only in one line at the
same time, second line is disconnected. If I have understood it good return
current has to flow in ground plane. Loop is formed by source, one line
from differential pair, termination resistor, VCC plane, decoupling
capacitor, ground plane. Does it make ground connection between for example
two PCBs extremely crucial? Does sending TMDS signal through twisted pair
CAT cable depends highly on good shield connection between systems because
this is conductor through which return currents flow ?

Best Regards,
inv___

	   
					
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