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On Wed, 26 Jan 2011 13:41:21 -0800 (PST), "langwadt@fonz.dk" <langwadt@fonz.dk> wrote: >On 26 Jan., 21:05, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Tue, 25 Jan 2011 11:26:06 +0100, David Brown >> >> >> >> <da...@westcontrol.removethisbit.com> wrote: >> >On 24/01/2011 23:17, John Larkin wrote: >> >> On Mon, 24 Jan 2011 11:51:12 -0800 (PST), rickman<gnu...@gmail.com> >> >> wrote: >> ><snip> >> >>> But none of this has to do with nationality. >> >> >>> Rick >> >> >It is important to distinguish between nationality and a country's laws >> >and bureaucracy - the regulations in John's quotation are about a >> >country's regulations, not an issue with the people. >> >> >>http://www.eetimes.com/electronics-news/4212317/Xilinx--sales-fall-sh... >> >> >> "Xilinx recorded $4.3 million worth of restructuring charges during >> >> the recently concluded quarter. Olson said the charges were greater >> >> than expected because the company is closing its software development >> >> operation in France, where regulations make eliminating jobs >> >> difficult." >> >> >> John >> >> >Clearly we don't know /what/ regulations are at issue here, as there >> >could be many. >> >> >In general, you have to have good reason for firing people in Europe, >> >and normally you have to give significant notice (I don't know the >> >details for France, but 3 months is standard here in Norway. Of course, >> >this also means you can't quit your job without giving 3 months notice - >> >it works both ways). >> >> Does the law require that you remain productive during those three >> months? > >here in Denmark it is the same 3 month minimum notice for employer >after first 6 months, >and it goes up by one month for ever 3 years of emplyment. >It is only one month for employees. > >The law says you have to do you jobs as you normally would >but you have the right to spend some time for job interviews etc. >and an employer can't make you do jobs that you normally wouldn't. > > >> >> But cutting staff because you are downsizing /is/ > >heres special rule that if you fire more that ~10 there has to be >collective negotiations of how it is to be done and what the terms >will be > >> >> >a good reason, though you might have to pay some sort of severance pay >> >or other compensation. You can't just tell employees to clear their >> >desks on the day, but you certainly can eliminate jobs. >> >> Here in California, an employer can ask an employee to take their >> stuff and leave, this very day or this very instant. I did that last >> week. And an employee can quit without notice. I've had people walk >> into my office, say "I quit", and walk out. >> >> John > >well you can tell an employee to leave immediately you'll just have >to keep paying the him for the severance period. Here, severance is voluntary on the employer's part; one week per year is common but not mandatory. Employees usually don't het severance if they quit, and may not if they are fired for cause. We are required to pay an employee for any unused vacation time. JohnArticle: 150576
On Jan 26, 5:30=A0pm, Jay <jpt03...@engr.uconn.edu> wrote: > "langw...@fonz.dk" <langw...@fonz.dk> wrote: > > On 26 Jan., 18:41, Jay <jpt03...@engr.uconn.edu> wrote: > >> Gabor <ga...@alacron.com> wrote: > >>> On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: > >>>> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: > > >>>>> Hey all. > > >>>>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of X= ilinx's > >>>>> documentation, (www.xilinx.com/support/answers/19146.htm) it is sug= gested > >>>>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to = protect > >>>>> the port from reverse current damage. However, instill might face l= ogic > >>>>> high problems as read from the avr. What would you suggest for a (s= mall > >>>>> footprint if possible) logic level converter? > > >>>>> Thanks in advance. > > >>>> There are so many chips for level shifting that the best fit > >>>> will really depend on your particular design. =A0How many > >>>> signals do you connect between the FPGA and the 5V > >>>> micro? =A0How many are inputs to the FPGA, how many > >>>> outputs from the FPGA and how many are bidirectional? > >>>> Going from 3V to 5V, you probably want to look at 74ACT > >>>> series or something similar that can work with a 5V supply > >>>> but has "TTL" compatible Vih and Vil specs. =A0Going from > >>>> 5V to 3V you could use the resistor (unidirectional). =A0For > >>>> bidirectional signals there are some parts with dual power > >>>> supply that can provide active drive to both sides. =A0If the > >>>> signals are relatively slow, then you can use "Quickswitch" > >>>> style FET switches and pullup resistors to do level shifting > >>>> bidirectionally without any added control signals. > > >>>> Regards, > >>>> Gabor > > >>> One more point I forgot to add. =A0The resistor trick doesn't > >>> work with the newer Spartan 3A and 3AN series parts. > >>> Those FPGA's don't have clamp diodes to Vcco. > > >>> -- Gabor > > >> Yeah in saw that. I'm not using the 3a, but i do need bi directional I= O. > >> There will be a total of 13 pins to the uC that need this treatment. > > >> Thanks for your help. > > > you can't change the supply for the AVR to something lower within the > > specs of > > the FPGA? > > > -Lasse > > No, I'm supporting an existing system. I've looked onto the 74act's and s= o > far they look like what I was looking for. I was just seeing if someone h= ad > dealt with this before. I'm surprised that you can't meet the input requirements for the 5 volt MCU. I guess they are using CMOS levels rather than TTL levels? The only way to boost the output level of the FPGA to the 5 volt CMOS level is with an active part like the ACT devices. But I'm not sure how you can use that part to work in both directions and I am pretty sure it won't do bidirectional, at least not in the same chip. The problem is that a part with 3.3 volt power will not drive enough for a 5 volt CMOS input and a part with a 5 volt supply will over drive the FPGA. If you check the TI web site, they have all sorts of parts for level shifting with all sorts of capabilities. I've found some pretty good selection guides there. RickArticle: 150577
>hi,
>i am using spartan 3 xc3s4000 in my design and i have two gigabit
ethernet
>interfaces integrated to it. I connect one interface to one pc and the
>other one to 2nd pc , all works fine. Pings going, packets going.
>When i insert two cisco switches configured on VLAN in the scenario i.e.
>pc<-> switch <-> FPGA <-> switch <-> pc ;
>
>my packets start dropping. I don't know why as i am only performing store
>and forward. If it is working without switches, it should work with
>switches as well.
>
>Can anyone give me any pointers ?
>
>Thanks
>
First replace the FPGA in this chain with a Cat5 crossover cable
(i.e.
remove the FPGA from the circuit and replace it with the cable (between the
two switches) and see if the packet loss still occurs. If yes, you need to
talk to the switch maintainer(s) to fix their switch (possibly allocating
more buffer space to your ports) and/or check the network settings on the
PCs to make sure they match the settings on the switch (usually auto). If
the loss doesn't occur then you are sure your board is the problem. Next
thing to check is the PHY and switch port configurations. Likely the switch
ports are in auto which means your boards PHYs need to be set to auto. If
the switches are set auto and your board is (of instance) manual 100 full
duplex (i.e. autonegotiation is disabled) then this can happen as the
switches may choose half duplex (they usually get the speed right) which
will cause the packet loss you are seeing. Another good thing to try is ask
the switch owner to check what the ports to the FPGA have negotiated with
the FPGA board in place. That should match what the PHY on your FPGA is set
for or has negotiated (although unless the PHY has status lights it may be
difficult to determine what it has negotiated). In short I think this is
more likely a network configuration problem than an FPGA one.
One last thought, check the settings on the network cards of the two PCs as
well, since they could be set to manual instead of auto (especially if your
board is also set to manual) and work but break when the switches are
added.
Peter Van Epp
---------------------------------------
Posted through http://www.FPGARelated.com
Article: 150578On Jan 26, 10:16=A0am, Emanuele83 <emanuele83katam...@googlemail.com> wrote: > Yes it cause the packing error, but not always... > > WHAT??? 100 lines? What do you mean with maintainability? > > My process has more than 900 lines... Sorry, but how can I separate a pro= cess in so small packages and do not go crazy with latency, synchronization= and so on? > I wold implement the whole design in schematics, it will be much easier..= . I'm with Robert on this one. If your code is so large that you can't explain it to us, it will be much harder for you to analyze. The code snippet that you posted is too small to see if you are using the variables correctly. You test I and then assign it another value, but it isn't checked again. A variable should be assigned a value before it is used no matter how the code is executed, or it describes a register and adds the latency you are trying to avoid. I keep my entire modules to around 150 to 200 lines if I can. Processes are typically 10 to 50 lines. State machines can be much larger of course, but you can try to put as much as possible outside the big case statement process to minimize the complexity. Think of the state machine as the sequencer of a CPU. Then do all the logic for controls separately. This can help eliminate latency too as the control decode can be done with combinatorial logic eliminating the registers that cause latency. Like Robert suggests, I always start with some sort of diagram showing where the registers go and then describe that in my HDL. Then I flesh it out with the various control logic. RickArticle: 150579
On 26/01/2011 21:05, John Larkin wrote: > On Tue, 25 Jan 2011 11:26:06 +0100, David Brown > <david@westcontrol.removethisbit.com> wrote: > >> On 24/01/2011 23:17, John Larkin wrote: >>> On Mon, 24 Jan 2011 11:51:12 -0800 (PST), rickman<gnuarm@gmail.com> >>> wrote: >> <snip> >>>> But none of this has to do with nationality. >>>> >>>> Rick >>> >>> >> >> It is important to distinguish between nationality and a country's laws >> and bureaucracy - the regulations in John's quotation are about a >> country's regulations, not an issue with the people. >> >>> http://www.eetimes.com/electronics-news/4212317/Xilinx--sales-fall-short-of-estimates >>> >>> "Xilinx recorded $4.3 million worth of restructuring charges during >>> the recently concluded quarter. Olson said the charges were greater >>> than expected because the company is closing its software development >>> operation in France, where regulations make eliminating jobs >>> difficult." >>> >>> John >>> >> >> Clearly we don't know /what/ regulations are at issue here, as there >> could be many. >> >> In general, you have to have good reason for firing people in Europe, >> and normally you have to give significant notice (I don't know the >> details for France, but 3 months is standard here in Norway. Of course, >> this also means you can't quit your job without giving 3 months notice - >> it works both ways). > > Does the law require that you remain productive during those three > months? > Note - I might not be entirely accurate here, since I am not involved in HR (other than helping with some technical interviews), and I've had the same job for the last sixteen years. Yes, you are bound by your contract (which employers must have with each employee, except for very short-term temporaries). Of course, it would get very messy if the employer had to sue the employee in court for breach of contract - generally if the employee is not going to do useful work for those 3 months, the employer and employee will reach an agreement. For example, if the employee is going to work for a competitor, the employer will probably effectively give him 3 months paid leave. It is also possible to make different arrangements, such as cutting out the 3 months so that the employee can start a new job immediately. The point of all this is to give both the employer and the employee a degree of stability. When you have a permanent job, you know you have a predictable income for the next three months at least. And when you have employed someone, you know they are not going to drop everything and disappear without notice. It makes it harder to fire a worker who doesn't do a good job (though you can still be fired on very short notice if you are doing something criminal, or dangerous, or grossly disloyal to your employer). > > But cutting staff because you are downsizing /is/ >> a good reason, though you might have to pay some sort of severance pay >> or other compensation. You can't just tell employees to clear their >> desks on the day, but you certainly can eliminate jobs. > > Here in California, an employer can ask an employee to take their > stuff and leave, this very day or this very instant. I did that last > week. And an employee can quit without notice. I've had people walk > into my office, say "I quit", and walk out. > Perhaps the Norwegian way takes some of the fun and excitement out of the employer-employee relationship...Article: 150580
from the Wikipedia's definition of Maintainability in Engineering: In engineering, maintainability is the ease with which a product can be mai= ntained in order to: _correct defects _meet new requirements _make future maintenance easier, or _cope with a changed environment I think that in my case the "cope with" sentence is important:=20 _the code works in post synthesis simulation _suppose that the requirements are fixed: I do not want to optimize it but = only to let it work in REAL logic _suppose that I do not care for the future _In this case if the environment means a different board, a different FPGA,= a different temperature, I do apologise, but the damned programming, compi= ling tool, must be able to synthetise, compile, translate, MAP and PAR my d= esign in the worst case. So if the design timing constraints are met, if th= ere are no errors I suppose that the LOGIC must implement my FW. I do agree= that there are better or worse HDL techniques, but since the user interfac= e does not show a red ERROR, I expect that if I compile the same FW with AR= EA or SPEED optimization (seeing the same, reasonable, constraints are met)= , I expect that the real FPGA board work. If I have a report that I cannot trust, why create the report itself? Why g= ive a synthesis tool which do not work as expected if the information which= gives (the reports, the warnings, the error, the programming bitstream) ar= e not real, or do not work as expected? If I am wrong, please explain me the way to understand how the FPGA designi= ng works. EmanueleArticle: 150581
On Wed, 26 Jan 2011 12:40:54 -0800 (PST), Lou <lciotti1@gmail.com> wrote: >OK. I finally got the display working. WOOO HOOO... > >Now my understanding is that to get characters on the display I have >to create a character rom, and a frame buffer. The character rom I >understand. I plan on making a rom that bisically contains 1's where >ever a pixel is on for each character. I plan on a 8x8 font. This >should give me 34 lines with 60 characters. > >I am a little confused on the frame buffer portion. Any pointers on >where to look for information on this? Your frame buffer holds the character for each display position. Typically using dual port BlockRAM - a read port feeding data to the display and a write port to update the display contents. Use initialisation data to put something in it to start with so you can get the display part working before worrying about the writing to it. The buffer read address is derived from your X/Y character position counts, and the output goes to the address input of your character ROM to select the character displayed at each position. The lower-order addresses of X/Y determine the address within each character definition. .Article: 150582
have you read this document from xilinx? it is used to interface a 3.3v FPGA to a 5V PCI bus http://www.xilinx.com/support/documentation/application_notes/xapp646.pdf this quickswitches will be maybe useful for you :)Article: 150583
Petter Gustad <newsmailcomp6@gustad.com> writes: > Martin Thompson <martin.j.thompson@trw.com> writes: > >> Your script can then write that image out to a file as a VHDL constant >> - you can use an array of integers to store the data. > > Or generate a MIF file or other ROM format supported by your FPGA > vendor. This is usually faster (but not as portable as the above > suggestion) to run through the tool-chain and most FPGA vendors have a > tool which will quickly merge a new version of a ROM file while > everything else being constant. Good point - I tend to lean very heavily towards portable, and forget about other options! What you suggest is an especially good plan if the project is likely to need to change the ROM contents frequently. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.co.uk/capabilities/39-electronic-hardwareArticle: 150584
Emanuele83 <emanuele83katamail@googlemail.com> wrote: >from the Wikipedia's definition of Maintainability in Engineering: > >In engineering, maintainability is the ease with which a product can be mai= >ntained in order to: >_correct defects >_meet new requirements >_make future maintenance easier, or >_cope with a changed environment > >I think that in my case the "cope with" sentence is important:=20 > >_the code works in post synthesis simulation >_suppose that the requirements are fixed: I do not want to optimize it but = >only to let it work in REAL logic >_suppose that I do not care for the future >_In this case if the environment means a different board, a different FPGA,= > a different temperature, I do apologise, but the damned programming, compi= >ling tool, must be able to synthetise, compile, translate, MAP and PAR my d= >esign in the worst case. So if the design timing constraints are met, if th= >ere are no errors I suppose that the LOGIC must implement my FW. I do agree= > that there are better or worse HDL techniques, but since the user interfac= >e does not show a red ERROR, I expect that if I compile the same FW with AR= >EA or SPEED optimization (seeing the same, reasonable, constraints are met)= >, I expect that the real FPGA board work. >If I have a report that I cannot trust, why create the report itself? Why g= >ive a synthesis tool which do not work as expected if the information which= > gives (the reports, the warnings, the error, the programming bitstream) ar= >e not real, or do not work as expected? > >If I am wrong, please explain me the way to understand how the FPGA designi= >ng works. In general computers do what they are told not what you expect them to do. In your original post you mention that communication between FPGAs is not working. This raises my suspision that the delays between input to FF and FF to output are not constrained. Check that first. http://www.xilinx.com/itp/xilinx10/isehelp/dec_c_unconst_path.htm Designing with FPGAs is not only a matter of writing correct HDL code. Depending on how much you are pushing the speed limits there may be a substantial amount of work in creating the constraints. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150585
all the I/Os are constrained. the point is: same VHDL code+same constrains --> changing synthesis/mapping/PAR options --> CONSTRAINTS ALWAYS MET @40MHz --> the behaviour changes. > >In general computers do what they are told not what you expect them to do. > Exactly what I do with my code that has been simulated and the algorithm results correct.Article: 150586
i am using DS33Z44 for IP to E1/E3 project and for Ethernet interface i am using 2 Phys(DP83849IF) each contains two internal PHY's(both internal PHYs have unique LSB of PHY address).now the thing i don't understand is each Phy has to configured with unique PHY address normally. but for the case of DS33Z44 which says that MDIO/MDC is only accessible by first MAC block of DS33Z44,and application note says MDIO lines of all phys and DS33Z44 need to be short and external address should be same too . in that case i can only configure one Phy-Address for all PHYs.so how can DS33Z44 identify which PHY is one,two three and four. can someone help me understand that architecture. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 150587
On Jan 27, 5:07=A0am, Emanuele83 <emanuele83katam...@googlemail.com> wrote: > have you read this document from xilinx? > > it is used to interface a 3.3v FPGA to a 5V PCI bus > > http://www.xilinx.com/support/documentation/application_notes/xapp646... > > this quickswitches will be maybe useful for you =A0:) Quick switches are good for limiting the voltage from a higher voltage device to a lower voltage device. But they don't boost the output voltage from the lower voltage device. CMOS levels between 5 volt and 3.3 volt logic are not compatible like TTL levels are. It sounds like the OP has 5 volt CMOS level inputs which won't work with quickswitches. That is why I recommended active devices like the ACT or HCT. These days this is a common problem and there are many specialized devices tailored to specific requirements. RickArticle: 150588
On Jan 27, 8:53=A0am, rickman <gnu...@gmail.com> wrote: > On Jan 27, 5:07=A0am, Emanuele83 <emanuele83katam...@googlemail.com> > wrote: > > > have you read this document from xilinx? > > > it is used to interface a 3.3v FPGA to a 5V PCI bus > > >http://www.xilinx.com/support/documentation/application_notes/xapp646... > > > this quickswitches will be maybe useful for you =A0:) > > Quick switches are good for limiting the voltage from a higher voltage > device to a lower voltage device. =A0But they don't boost the output > voltage from the lower voltage device. =A0CMOS levels between 5 volt and > 3.3 volt logic are not compatible like TTL levels are. =A0It sounds like > the OP has 5 volt CMOS level inputs which won't work with > quickswitches. =A0That is why I recommended active devices like the ACT > or HCT. =A0These days this is a common problem and there are many > specialized devices tailored to specific requirements. > > Rick Well, the quickswitches don't boost the voltage, but the pullup to 5V on the high voltage side will (eventually) boost the voltage. You should think of quickswitches as open-drain for 3V to 5V CMOS apps. It's really a little better than that because the channel conducts until about 1V below the power supply, but if you need to meet the CMOS levels the remainder of the rising waveform is only supplied by the pullup. Whether this is acceptable really depends on the speed of the interface and the drive capability of the 5V side (for reducing the pullup value). You need to be careful to choose a supply voltage that is low enough not to cause overdrive on the 3V side, and also be aware that some low supply voltage switches from TI actually have charge pumps in them that would defeat the whole purpose as a level shifter. -- GaborArticle: 150589
On Jan 27, 7:42=A0am, Emanuele83 <emanuele83katam...@googlemail.com> wrote: > all the I/Os are constrained. > > the point is: > same VHDL code+same constrains --> changing synthesis/mapping/PAR options= --> CONSTRAINTS ALWAYS MET @40MHz --> the behaviour changes. > > > > > > >In general computers do what they are told not what you expect them to > do. > > Exactly what I do with my code that has been simulated and the algorithm = results correct. There is a big difference between working simulation and working synthesis designs. My recommendation is to narrow your focus and problem range. You can focus on one of your problems and figure out what is wrong which may solve all the problems. Or perhaps cut out specific sections of your design and test that separately. Maybe design some specific logic to test your hardware since you can't say that is definitely working. This is the stuff that separates the men from the boys... Instead of complaining about the process, you need to learn the process and work with it. No, it is far from perfect and never really easy. But if it were easy, anyone could do it and they would hire out of work interior decorators instead of engineers! RickArticle: 150590
Emanuele83 <emanuele83katamail@googlemail.com> wrote: >all the I/Os are constrained. > >the point is: >same VHDL code+same constrains --> changing synthesis/mapping/PAR options --> CONSTRAINTS ALWAYS MET @40MHz --> the behaviour changes. Read what I'm typing: clock constraints are not enough for designs at 40MHz you must constrain the input to FF and FF to output paths as well! -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 150591
This is the first project I've done in Verilog in many years. With a long history in VHDL I have a new perspective and am seeing Verilog in a different way. I am finding some of the differences to be pretty interesting actually. I've already commented on the lack of the wildcard sensitivity only to find that VHDL has recently added this. Now I am learning how Verilog allows hierarchical path references to signals for test benches. This is awesome!!! I would love to have had this in Verilog. It is such a PITA to have to bring every generic or debug signal to the top of a design just to support a test bench. ... or did I miss something again? RickArticle: 150592
On Jan 27, 9:00=A0am, Gabor <ga...@alacron.com> wrote: > On Jan 27, 8:53=A0am, rickman <gnu...@gmail.com> wrote: > > > > > On Jan 27, 5:07=A0am, Emanuele83 <emanuele83katam...@googlemail.com> > > wrote: > > > > have you read this document from xilinx? > > > > it is used to interface a 3.3v FPGA to a 5V PCI bus > > > >http://www.xilinx.com/support/documentation/application_notes/xapp646.= .. > > > > this quickswitches will be maybe useful for you =A0:) > > > Quick switches are good for limiting the voltage from a higher voltage > > device to a lower voltage device. =A0But they don't boost the output > > voltage from the lower voltage device. =A0CMOS levels between 5 volt an= d > > 3.3 volt logic are not compatible like TTL levels are. =A0It sounds lik= e > > the OP has 5 volt CMOS level inputs which won't work with > > quickswitches. =A0That is why I recommended active devices like the ACT > > or HCT. =A0These days this is a common problem and there are many > > specialized devices tailored to specific requirements. > > > Rick > > Well, the quickswitches don't boost the voltage, but the pullup to 5V > on > the high voltage side will (eventually) boost the voltage. =A0You should > think of quickswitches as open-drain for 3V to 5V CMOS apps. > It's really a little better than that because the channel conducts > until about 1V below the power supply, but if you need to meet > the CMOS levels the remainder of the rising waveform is only > supplied by the pullup. =A0Whether this is acceptable really depends on > the speed of the interface and the drive capability of the 5V > side (for reducing the pullup value). =A0You need to be > careful to choose a supply voltage that is low enough not > to cause overdrive on the 3V side, and also be aware that > some low supply voltage switches from TI actually have > charge pumps in them that would defeat the whole purpose > as a level shifter. > > -- Gabor One volt below the 5 volt power rail blows out the Spartan inputs. The quick switch products for level shifting add a diode in the Vcc path so that the high level is limited to about 3.3 volts, below the high level threshold on the 5 volt side. Yes, a pullup can help, but as I found out on a design using a series limiting resistor, this can affect performance. I'm not saying this won't work, but it is not ideal for a 5 volt CMOS input. The devil is in the details which we don't have. RickArticle: 150593
Gabor <gabor@alacron.com> wrote: > On Jan 27, 8:53 am, rickman <gnu...@gmail.com> wrote: >> On Jan 27, 5:07 am, Emanuele83 <emanuele83katam...@googlemail.com> >> wrote: >> >>> have you read this document from xilinx? >> >>> it is used to interface a 3.3v FPGA to a 5V PCI bus >> >>> http://www.xilinx.com/support/documentation/application_notes/xapp646... >> >>> this quickswitches will be maybe useful for you :) >> >> Quick switches are good for limiting the voltage from a higher voltage >> device to a lower voltage device. But they don't boost the output >> voltage from the lower voltage device. CMOS levels between 5 volt and >> 3.3 volt logic are not compatible like TTL levels are. It sounds like >> the OP has 5 volt CMOS level inputs which won't work with >> quickswitches. That is why I recommended active devices like the ACT >> or HCT. These days this is a common problem and there are many >> specialized devices tailored to specific requirements. >> >> Rick > > > Well, the quickswitches don't boost the voltage, but the pullup to 5V > on > the high voltage side will (eventually) boost the voltage. You should > think of quickswitches as open-drain for 3V to 5V CMOS apps. > It's really a little better than that because the channel conducts > until about 1V below the power supply, but if you need to meet > the CMOS levels the remainder of the rising waveform is only > supplied by the pullup. Whether this is acceptable really depends on > the speed of the interface and the drive capability of the 5V > side (for reducing the pullup value). You need to be > careful to choose a supply voltage that is low enough not > to cause overdrive on the 3V side, and also be aware that > some low supply voltage switches from TI actually have > charge pumps in them that would defeat the whole purpose > as a level shifter. > > -- Gabor Well, interestingly, it looks like i can update the uC. The atmega 48/88/168/328 have minimum VIH of .6Vcc. Since this uC runs on 5v, that puts me at a minimum VIH of 3v. The FPGA should be able to drive the uC high. I just have to worry about the reverse current.Article: 150594
rickman wrote: > This is the first project I've done in Verilog in many years. With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. Now I am learning how Verilog > allows hierarchical path references to signals for test benches. This > is awesome!!! I would love to have had this in Verilog. It is such a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. > > ... or did I miss something again? Yep; VHDL 2008 added External Names (P1076-2008, section 8.7), which I believe are the moral equivalent of Verilog hierarchical references. Google's first hit on them: http://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_ease/#hierarchicalnames -- Tim McBrayer MathWorksArticle: 150595
"rickman" wrote in message
news:f8d79600-a7d4-4c5b-b5d3-655122ad1124@k14g2000pre.googlegroups.com...
..
I've already commented on the lack of the wildcard sensitivity only to
find that VHDL has recently added this. Now I am learning how Verilog
allows hierarchical path references to signals for test benches. This
is awesome!!! I would love to have had this in Verilog. It is such a
PITA to have to bring every generic or debug signal to the top of a
design just to support a test bench.
... or did I miss something again?
Yes, VHDL2008 supports hierarchical references (works fine in Modelsim
10.0), before that you had SignalSpy and many other custom solutions to this
issue.
<<signal .test2008_tb.u1.muxout : std_logic_vector(2 downto 0) >> <= force
"011"; -- inject error
Hans.
www.ht-lab.com
From puiterl@notaimvalley.nl Thu Jan 27 07:29:49 2011
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From: Paul Uiterlinden <puiterl@notaimvalley.nl>
Subject: Re: Wow! No TestbenchWow!
Newsgroups: comp.arch.fpga,comp.lang.vhdl,comp.lang.verilog
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Date: Thu, 27 Jan 2011 16:29:49 +0100
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rickman wrote:
> This is the first project I've done in Verilog in many years. With a
> long history in VHDL I have a new perspective and am seeing Verilog in
> a different way. I am finding some of the differences to be pretty
> interesting actually.
>
> I've already commented on the lack of the wildcard sensitivity only to
> find that VHDL has recently added this. Now I am learning how Verilog
> allows hierarchical path references to signals for test benches. This
> is awesome!!! I would love to have had this in Verilog. It is such a
> PITA to have to bring every generic or debug signal to the top of a
> design just to support a test bench.
>
> ... or did I miss something again?
Yes! ;-)
Well, maybe....
For bringing up debug signals to the testbench you can use "global" signals
declared in a package. It is not synthesizable (but for debug signals that
would not be a problem). Also, the assignment to the global signal has to
take place at the location were the object to be observed is visible.
Example:
PACKAGE pkg IS
SIGNAL spy: std_logic_vector(7 DOWNTO 0);
END PACKAGE pkg;
In the architecture where you want to observe a signal:
USE work.pkg.ALL;
ARCHITECTURE arch OF design_block IS
BEGIN
...
spy <= observed_signal;
...
END ARCHITECTURE arch;
In your testbench:
USE work.pkg.ALL;
ARCHITECTURE arch OF tb IS
BEGIN
...
-- spy is visible here, due to the USE statement
IF spy = ... -- whatever
...
END ARCHITECTURE arch;
Another way to do all this is using the new VHDL-2008 feature
called "external names". Then you can peek into the DUV every which way you
want, without the need of changing DUV code.
Example (from the Ashenden/Lewis book: VHDL-2008 just the new stuff):
ASSERT <<SIGNAL .tb.duv.controller.state: std_logic_vector(0 TO 4)>>
/= "00000"
REPORT "Illegal controller state";
VHDL-2008 also includes FORCE and RELEASE assignments. This means that you
don't need simulator dependant commands anymore for forcing signals in the
DUT.
I have no idea if there already is a simulator that supports these
constructs.
--
Paul Uiterlinden
www.aimvalley.nl
e-mail addres: remove the not.
Article: 150596"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:e2k1k61umef17laprla8cmb0j7garppgdj@4ax.com... > Here, severance is voluntary on the employer's part; one week per year > is common but not mandatory. My (limited) experienced is that for "regular" employees, one week per year is common... but for "executives" often six months to one year is common, despite their tenure and despite how much they personally were responsible for fouling things up. :-) > Employees usually don't het severance if > they quit, and may not if they are fired for cause. Heck, some scummy employers tend to hold onto an employee's last paycheck if the employee leaves under bad terms; they know that most employees are gonig to be busy looking for another job and likely won't have the time and/or money to pursue getting it in court. > We are required to > pay an employee for any unused vacation time. Right, since it's "their" time. AIUI this is the reason many companies cap vacation time at, e.g., 4 weeks -- they don't want employees building up a little $100k "vacation cash" fund that tends to look bad on the books. ---JoelArticle: 150597
On Jan 27, 2:22=A0pm, rickman <gnu...@gmail.com> wrote: > This is the first project I've done in Verilog in many years. =A0With a > long history in VHDL I have a new perspective and am seeing Verilog in > a different way. =A0I am finding some of the differences to be pretty > interesting actually. > > I've already commented on the lack of the wildcard sensitivity only to > find that VHDL has recently added this. =A0Now I am learning how Verilog > allows hierarchical path references to signals for test benches. =A0This > is awesome!!! =A0I would love to have had this in Verilog. =A0It is such = a > PITA to have to bring every generic or debug signal to the top of a > design just to support a test bench. > > ... or did I miss something again? > > Rick I've always thought that it would be nice if FPGA synthesis tools supported the hierarchical path names too. i.e. if you wanted to debug a core with chipscope, you could do assign trig0[0] =3D my_core.some_internal_block.troublesome_node;Article: 150598
rickman <gnuarm@gmail.com> wrote: > On Jan 27, 5:07 am, Emanuele83 <emanuele83katam...@googlemail.com> > wrote: > > have you read this document from xilinx? > > > > it is used to interface a 3.3v FPGA to a 5V PCI bus > > > > http://www.xilinx.com/support/documentation/application_notes/xapp646... > > > > this quickswitches will be maybe useful for you :) > Quick switches are good for limiting the voltage from a higher voltage > device to a lower voltage device. But they don't boost the output > voltage from the lower voltage device. CMOS levels between 5 volt and > 3.3 volt logic are not compatible like TTL levels are. It sounds like > the OP has 5 volt CMOS level inputs which won't work with > quickswitches. That is why I recommended active devices like the ACT > or HCT. These days this is a common problem and there are many > specialized devices tailored to specific requirements. BUSHOLD circuits, like in the AVR data bus, come to rescue here... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 150599
Jay <jpt03002@engr.uconn.edu> wrote: >Gabor <gabor@alacron.com> wrote: >> On Jan 26, 11:07 am, Gabor <ga...@alacron.com> wrote: >>> On Jan 26, 9:32 am, Jay <jpt03...@engr.uconn.edu> wrote: >>> >>>> Hey all. >>> >>>> I'm trying to interface a Spartan 3 with a 5 volt avr. In some of Xilinx's >>>> documentation, (www.xilinx.com/support/answers/19146.htm) it is suggested >>>> that to make the S3s IO 5v tolerant, a 300 ohm resistor be used to protect >>>> the port from reverse current damage. However, instill might face logic >>>> high problems as read from the avr. What would you suggest for a (small >>>> footprint if possible) logic level converter? >>> >>>> Thanks in advance. >>> >>> There are so many chips for level shifting that the best fit >>> will really depend on your particular design. How many >>> signals do you connect between the FPGA and the 5V >>> micro? How many are inputs to the FPGA, how many >>> outputs from the FPGA and how many are bidirectional? >>> Going from 3V to 5V, you probably want to look at 74ACT >>> series or something similar that can work with a 5V supply >>> but has "TTL" compatible Vih and Vil specs. Going from >>> 5V to 3V you could use the resistor (unidirectional). For >>> bidirectional signals there are some parts with dual power >>> supply that can provide active drive to both sides. If the >>> signals are relatively slow, then you can use "Quickswitch" >>> style FET switches and pullup resistors to do level shifting >>> bidirectionally without any added control signals. >>> >>> Regards, >>> Gabor >> >> One more point I forgot to add. The resistor trick doesn't >> work with the newer Spartan 3A and 3AN series parts. >> Those FPGA's don't have clamp diodes to Vcco. >> >> -- Gabor >Yeah in saw that. I'm not using the 3a, but i do need bi directional IO. >There will be a total of 13 pins to the uC that need this treatment. Use resistors and 3.3V zeners. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------
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