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Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10551
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -DamonArticle: 10552
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -DamonArticle: 10553
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10554
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10555
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10556
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10557
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10558
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10559
Hi all, Anyone knows why the Xact Step software from Xilinx doesn't allow me to assign an external clock to PGCK pin on XC4000A? However, I was able to assign an external clock to the SGCK. Thank you for your help, -PeterArticle: 10560
Hi, Does anyone know XGA timing standards (1024*768 at 60 Hz.)? I coludn't find it anywhere on the web. Mustafa Dagtekin http://www4.ncsu.edu/~mdagtekArticle: 10561
1998 IEEE International Workshop on MEMORY Technology, Design, and Testing August 24-25, 1998 Fairmont Hotel San Jose, California Web Page: www.cs.tamu.edu/faculty/fmeyer/mtdt98.html For general information contact: Fabrizio Lombardi, MTDT General Chair Computer Science MS 3112 Texas A&M University College Station TX 77843 +1-409-845-5464 fax +1-409-847-8578 lombardi@cs.tamu.edu Hotel reservation by: August 3, 1998 Advance registration by: August 10, 1998 Session Topics Embedded DRAM Embedded Memory Design Aids Memory Repair Content Addressable Memories Algorithms and Testing Techniques Unique Fault Models Special Tutorial Sessions DRAM Fault Modeling SRAM Acceptance TestingArticle: 10562
For HLL stuff, you could check out http://www.comlab.ox.ac.uk/oucl/hwcomp.html (look for Handel-C) http://www.optimagic.com/ has a list of FPGA board vendors and much other good stuff. regards, tom Guy Laden wrote: > > For fun, I'd like to purchase an FPGA and experiment with compiling > from my own HLL directly to the FPGA. I know a bit about compilers but > am totally new to reconfigurable computing and am seeking advice regarding > what I need to purchase. Can anybody recommend a cheap PC card with an > FPGA that I could use for this? Are there any software tools I need > that don't usually come with the card? Do these cards usually ship > with all the documentation one would need to accomplish what I want? > Finally, any pointers to similar work would be appreciated. > Thanks for any advice. > Regards, > Guy -- ----------- Tom Burgess National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 10563
Nothin new here. PPR does a better job than M1 with 4KE designs too (at least for the dense ones), especially if you've placed the design by hand. With no floorplanner in the current release of M1, the old xact6 stuff is the way to go if you need density and/or performance. There is a beta floorplanner for M1 available from xilinx if you pester them. It may help to place the design using the old placement. Too bad PPR doesn't handle the newer chips! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10564
Please find enclosed the call for participants for ICCD '98: International Conference on Computer Design 1998. Kindly forward this Announcement to your colleagues. Best regards. Chin-Long Wey, Publication Chair, ICCD '98 **************************************************************************** C A L L F O R P A T I C I P A N T S **************************************************************************** INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD '98 October 5 - 7, 1998 Marriott Hotel at the Capitol, Austin, Texas Sponsored by: IEEE Circuits and Systems Society and The IEEE Computer Society; In Cooperation with: IEEE Electron Devices Society The International Conference on Computer Design encompasses a wide range of topics in the design and implementation of computer systems and their components. ICCD's multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering system and computer architecture, verification and test, design and technology, and tools and methodologies. This year's program includes three invited sessions on the latest processor developments, two embedded tutorials, two panel discussions, two advance technology forums, and 21 technical sessions with 69 scheduled paper presentations. During the poster session on Monday night wine and cheese will be served. IBM and Motorola will sponsor the lunches on Monday and Tuesday, respectively. Murray Campbell, IBM Thomas J. Watson Research Center will give the Keynote Speech. Three plenary sessions provide leaders in the field the opportunity to present the latest developments and visions of future progress in key ICCD subject areas. Up-to-date information on ICCD '98 is available on the World Wide Web--- http://domino.watson.ibm.com/iccd98/iccd98.nsf/Program.html ************************************************************************** ICCD '98 General Chair: Bing Sheu, University of Southern California, USA Technical Program Chair: Andreas Kuehlmann, IBM T.J. Watson Research Center, USA Publications Chair: Chin-Long Wey, Michigan State University, USA Treasurer: Tim Brodnax, IBM Corporation, USA Industry Liaison: Nasr Ullah, Motorola Inc., USA Local Arrangements: Dan Elgin, University of Texas at Austin, USA Architecture and Algorithms Track Co-Chair: Craig Chase, University of Texas at Austin, USA Co-Chair: David Witt, Advanced Micro Devices, USA Integrated Systems Track Co-Chair: Rajesh K. Gupta, University of California, USA Co-Chair: John Trotter, Lucent Bell Laboratories, USA Verification and Test Track Co-Chair: Warren A. Hunt, Jr, IBM Corporation, USA Co-Chair: Wolfgang Kunz, University of Frankfurt, Germany Design and Technology Track Co-Chair: Sandip Kundu, Austin Research Lab, USA Co-Chair: Sarma Vrudhula, University of Arizona, USA Tools and Methodology Track Co-Chair: Joel Grodstein, Digital Equipment Corporation, USA Co-Chair: Kenneth L. Shepard, Columbia University, USA ===========****============****===========****================== Dr. Chin-long Wey, Professor Department of Electrical Engineering Michigan State University, East Lansing, MI 48824-1226 Phone: 517-353-0665; Fax: 517-353-1980; E-mail: wey@egr.msu.edu URL: http://www.egr.msu.edu/~weyArticle: 10565
http://users.cybermax.net/~cristy22/ =======ALL FOR FREE======= YOU HAVE TO SEE THIS TO BELIEVE IT. 4 HOT COLLEGE GIRLS LIVING IN A HOUSE WITH CANS IN EVERY ROOM INCLUDING THE SHOWER. THE CAMS ARE ON 24 HOURS AND THERE IS ALSO A CHAT ROOM SO YOU CAN TALK TO THEM TOO... http://users.cybermax.net/~cristy22/ http://users.cybermax.net/~cristy22/ BJaArticle: 10566
Damon: 1Q: Do you mean assign a pin number to a pad driving the PGCK? 1A: If so, there is a pre-defined pad/pin(based on pkg) that drives each PGCK (BUFGP) 2Q: Are you driving from an IPAD through an IBUF to the input of the BUFGP? 2A: If so, remove the IBUF - not appropriate when using BUFGP. The subtle difference between the two are discussed in the databook. From a source standpoint, the BUFGS can be driven by a dedicated package pin OR an internal signal. The BUFGP can only be driven from the package pin. There is a trick to drive it from an internal source. I'll pass it on if you think you need it. BTW, XC4000A? Whatcha using that for? -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 damon wrote: > > Hi all, > Anyone knows why the Xact Step software from Xilinx doesn't allow me > to assign an external clock to PGCK pin on XC4000A? However, I was able > to assign an external clock to the SGCK. > > Thank you for your help, > > -DamonArticle: 10567
Hello, PCB's with JTAG capability are often equiped with a "standard" 10 pol. flatcable connector. In some designs this connector needs a relative large percentage of available space on the PCB. Are there some other (tiny) connectors that are often used as a connector on a PCB to connect JTAG? Greetings, H. LuijmesArticle: 10568
Terje Mathisen wrote: > Bruce Hoult wrote: > > While that's true, I'm sure your hardware solution isn't using a > > full width sum-of-products implementation either. Anywhere you use > > cascaded logic, a software implementation can use the exact same > > cascaded logic or cascaded table lookups. > > That is of course the way to implement it. Quite so, which is why an FPGA implementation can be fast; cascaded table lookups being the fundamental architecture of most SRAM FPGAs. I've just spent a couple of hours doing a faster implementation (with single bit state), that pushes the ram bandwidth a bit harder. The new implementation does around 270 million cell iterations per second. I'm processing 32 cells in parallel, but its bandwidth limited (must do the usual read/write and also get data for display). The display is running at 60fps, but I'm effectively doing in excess of 1000fps. I can tell you things move very quickly! We should be getting a new board soon with more banks of RAM which should be able to reach at least four times this performance, and we may also be able to push the clock rate up further. A couple of other details: the system features VGA display and a serial mouse interface for interacting with the automata, and uses around 90% of a Xilinx 4013XL (I've been a bit lazy, could probably make it quite a lot smaller). The fundamental life cell uses around 5 CLBs, so without all the interfacing you could theoretically do 115 cells per clock cycle on this chip; the biggest chip in Xilinx's range could do around 10 times that. Cheers, Matt -- Matt Aubury Oxford University Computing Laboratory, Hardware Compilation GroupArticle: 10569
Matt Aubury (mpa@comlab.ox.ac.uk) wrote: [snip the how-to of Life] : Quite so, which is why an FPGA implementation can be fast; cascaded : table lookups being the fundamental architecture of most SRAM FPGAs. I'm interested in implementing one relatively complex and one very simple cellular automata on SRAM FPGAs. I'd be interested to know how much storage there is per gate on the type of Xilinx FPGAs typically used for such things. : The fundamental life cell uses around 5 CLBs, so without all the : interfacing you could theoretically do 115 cells per clock cycle [snip] That sounds pretty good. I looked briefly at the Oxford Hardware Compilation Group's web site but didn't find any relevant details. Is there a diagram of the ~=5 gates anywhere? -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk tt@cryogen.comArticle: 10570
Hi This what I try to sad is If in downloading time< when congig/done signal is low, on one of four dedicated inputs was trunsaction, incoming signal change, downloading fails, To prevent this I used and logic on the input (4) signals with config/done outgoing signal Regards ----------- Lev Razamat ------------- PHASECOM Ltd. Jerusalem lrazamat@usa.net lev5@phasecom.co.il ICQ# 3347700 Tel: (972)-2-5889860 w. (972)-2-5355576 r. Fax: (972)-2-5889889 Mobile: (972)-50-420846 ------------------------------------------------- Changho Bae wrote in message <6klb1a$1id$1@news.kren.nm.kr>... >Hi >I don't understand what does that mean, >so could you explain it more detail, please. > >have a good day. > >Article: 10571
Without a little more information its difficult to be sure. However my suspicion is that the command file was originally developed to recall a specific checkpoint ( previously save state of the simulator ). If this command file is running on a different system or project, then that state will not be available. You should be able to resolve the problem by simply removing the appropriate reference in the command file. Will In article <01bd8a05$75e121c0$69c3af8b@john>, John Huang <hungi@tpts4.seed.net.tw> writes >Hi all > > I get a problem in ViewLogic's SpeedWave, the message >shown when I execute a command file, > >ex test.cmd >| Clearing all clocks. >| Fatal Error: Restart failed for VHDL, checkpoint directory doesn't exist. >| Reinitializing waveforms. >| Simulation time rolled back to 0.0ns. >| Open wave streams: Asic.vcd >| Simulation stopped at 40.0ns. > >What's the error meaning? > > Please tell me, Thanks! > > > John Huang -- William White < ------------------------ < < < ---------- Mailto: will@fpga.demon.co.uk | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | < < < Fax: +44 1280 700577 | --------------------------- < ------------------------------------------Article: 10572
The SPROM problem recently reported on this newsgoup was caused by a user error in reading the SPROM pinout. This is just for the record, since I always claim that configuration is ( and must be ) a 100% reliable process. Peter Alfke, Xilinx ApplicationsArticle: 10573
Hi all, Just a quicky question... I need to supply about 15-20ma to a LED from the pin of a Xilinx 4005XL. (This is due to a mistake at the schematic level, they were originally designed to work as current sinks). There is an application note in the 1998 databook regarding the I/o characteristics of the XL fpga (XAPP088) that seems to imply that when the device is sourcing current, it can supply 20ma and yet still have an output voltage of 2.5v (approx.). Unfortunatly I cannot confirm this figure, as the datasheet for the XL device does not seem to mention (I probably missed it) the specification for Ioh. Does anyone know whether pulling 20ma from a single pin will hurt the device!!???? (And I have to do it for 4 pins, all in the same corner of the device) Thanks in advance for any technical assistance. Tony -- Sent By Tony Cooper. email: tony.cooper@virgin.netArticle: 10574
We are developing a novel ASIC product and want to sign up some beta customers. We are looking for designs in 20K to 200K gate range. Our technology is 0.35 micron with embedded RAM blocks. Key product features: ZERO NRE. Min. volumes of 1K pcs. 100% scan based for high testability. STD unit pricing follows: Used gates Package Unit pricing for 10K pcs. 20K 100 pqfp $3.00 50K 100 pqfp $4.00 100K 100 pqfp $5.00 200K 100 pqfp $7.50 our preferred interface is HDL or FPGA netlist. Formal product announcement will be in October. Regards, Kash Johal, Macrotech Semiconductor ph: 360 0430 fax: 360 0435 e-mail: kash@ix.netcom.com
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Compare FPGA features and resources
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