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Xilinx used to have (or mabe still have) a program called MAKESRC. This program would take your bitstream file and generate source code (either assembly or C). You could configure it so that it would produce an array of 'whatevers'. Once you get your code you can then compile it into the executeable and do whatever you like with it. Ed McCauley wrote: > Don, > > The .bit file basically contains the same data as the .mcs files > produced by makeprom. > Differences: .mcs contains address info that is used by the prom > programmer to locate the values in the data fields. prom files also > contains row length and check sum values, again used by the prom > programmer, NOT written into the PROM. That's key.... the extra values > don't go into the prom, they only control the operation of the > programmer. > > If you want just the 1s and 0s, you want to turn on the "Produce ASCII > Configuration File" option in the configuration/configuration template. > What are you really trying to do? > > BTW, we flew into Republic a week or so ago and met with John Holst and > Fred LaMarca (the Hamilton salesperson and FAE) to discuss how BLT might > help your company. > > -- > Ed McCauley > Bottom Line Technologies Inc. > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > FAX: (908) 996-0817 > > dfrevele@li.net wrote: > > > > easy question: > > > > I want to configure a single Xilinx from a microprocessor. Can I just download > > the .bit file produced from the implementation tools? I've previously loaded > > multiple daisy-chained Xilinxs from a microprocessor and had to use makeprom > > (promgen) to produce the download file. But for a single device can the .bit > > file be used directly. > > > > Don Frevele > > GEC-Marconi Hazeltine Corp. > > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > > http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum -- ------------ Gareth BaronArticle: 11001
In article <35a42bca.2324283@newshost> allan.herriman.hates.spam@fujitsu.com.au (Allan Herriman) writes: >On Wed, 8 Jul 1998 04:49:36 GMT, fliptron@netcom.com (Philip Freidin) >wrote: > >>The weird assignment of the DOUT pin as a clock input is not unique to the >>Spartan family. This "annoyance" permeates all the XC4000 families: >> XC4000, 4KE, 4KL, 4KH, 4KD, 4KEX, 4KXL, and 4KXV, Spartan. >> >>This is the price of compatibility :-) > >Nope. Spartans have different pinouts. Thus Xilinx could have >assigned DOUT to something other than SGCK4. > >(XCS40-PQ208 has 16 VCC pins, 4020E-HQ208 has only 8.) > >Allan. Nope. Spartans have different bondouts. PhilipArticle: 11002
Yes, I have this, back from around 1991 ! Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11003
How true. This is the first thing they should teach on VHDL courses :) >For all Synthesis tools, the coding style does affect the optimization >of the result. Synthesis is not completely magic, the designer needs to >have inmind the target design and device architecture, and write the >code in a way that generates the design intended. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11004
We DO! -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Peter wrote: > > How true. This is the first thing they should teach on VHDL courses :) > > >For all Synthesis tools, the coding style does affect the optimization > >of the result. Synthesis is not completely magic, the designer needs to > >have inmind the target design and device architecture, and write the > >code in a way that generates the design intended. > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but > remove the X and the Y.Article: 11005
As long as we are wish listing. 1.Could Design Manager please close it's child windows automagicly on exit, or at least bring to front those it can't close? 2 Could fe.log be put in the reports section? It is such a hassle to chase it down with Explorer when you want to look at it.. 4. CLB naming conventions. Could M1 default to naming a CLB after the out nets of the flops before naming them for X or Y outs? In a CLB that has both direct out LUT signals and flop outs, the X output gives the name to the CLB, even when X could be called Net $000023 and the flop out could be called “A_Really_Important_Signal” the CLB will be called Net $00023, now that just is not right. Just a few things..... there are more but how about these fairly straight forward ones.... Paul Walker wrote: > Perhaps you get what you pay for, and the very cheap Foundation Base > package is a pretty good buy, particularly as the "10k gates" limit only > applies to the 4kE family, and the package seems to be able to work with > Spartans up to XCS40. > > But I begin to tear (what's left of) my hair out when saving an edit to > a symbol, and the message appears "Incorrect Pin Name" and it refuses to > save the symbol; No indication which pin, nor what is wrong with the > name; nothing in Help to say what a correct pin name is; nothing > produced from the menu item "test symbol" other than the same "Incorrect > Pin Name". > > Of course there is a workaround to a problem like this --- throw away > all the edits to the symbol and start again, saving this time after > every tiny edit to catch the one that went wrong. But should we really > have to do so? > > This prompts me to write up a few other frustrations. If anyone has any > good ways to avoid them, or has similar experiences with other parts of > Foundation or with other products, please let us know. > > Auto-Placement: The critical timing on a Spartan part, a single level of > logic between the two edges of a clock, was ok but about 80% logic delay > so I wondered if a faster device would go faster. With the same > constraint file, a 4kE-1 actually went slower, not because of this > critical path, but because other paths had been made worse by the > ugliest placement imaginable. I spent about half an hour with EPIC doing > a crude placement based on the rats' nest, and without any reference to > the logic design. Two or three passes of EPIC's router then produced a > routing that went almost twice as fast as the original auto > implementation. > > Copying projects: When you copy a project, the UCF file that constrained > timings or pins is copied across, but a dummy new one is generated for > the new project. Design Manager proceeds to use this new file rather > than the old one. The documentation does actually say this, but there is > a big inconsistency between Project Manager's concept of attaching files > to the project, and Design Managers's concept of using default filenames > regardless. > > Upper and Lower Case: There are dire warnings in some of the > documentation that while M1.4 is case insensitive, M1.5 will be case > sensitive and so users should be consistent. Fine, I'd love to use > signal names such as TxClock and RxClock, and am totally happy to be > consistent with the upper and lower case. But the Schematic entry > package that comes with Foundation insists that all signal names are > upper case, regardless of what I type. I would, politely as I can, > suggest to Xilinx that this is INCONSISTENT_AND_VERY_ANNOYING. > > The old PLDShell software produced by Intel and canned by Altera was and > still is extremely good. We have a number of designs in PLDShell, and > several of these are now designed for a fan-in of four, so are optimised > for Xilinx (and other) FPGA LUTs. We can convert the PLDShell to Abel > for input to Foundation, and this poses no problem. What causes more of > a problem is that ABL2EDIF seems to do its own optimisations which turn > our one level of logic into two or three levels. What's more, there is > no way to turn this optimisation off. Of course it is possible to > convert to VHDL, but at a large increase in cost, a large learning time, > and the expectation suggested by many contributors to this news group > that the performance will be poor. If anyone has any suggestions of how > to take a design for 4-input LUTs straight through to an implementation > which preserves the original design, I'd be most grateful. > > Thanks > > Paul > > PS. In spite of all this, I still like the RAM of the 4kE, and like many > aspects of the Foundation package. The UK help desk has been very > helpful, even when I've not read the manual and even when there is > nothing they can do. > -- > Paul Walker 4Links phone/fax > paul@walker.demon.co.uk P O Box 816, Two Mile Ash +44 1908 > http://www.walker.demon.co.uk Milton Keynes MK8 8NS, UK 566253Article: 11006
Jordan Swartz wrote: > > This is for all those hardware designers using FPGAs who are > tired of waiting several hours (or days?) to compile large circuits: > > For my Master's thesis, I'm working on a high-speed routing tool > that is capable of routing a 20,000 4-LUT circuit in 70 seconds. > (on an architecture similar to the Xilinx 4000EX/XL) > > I would greatly appreciate it if you could take a few minutes > to answer the following questions: > > Would you be interested in a tool that could place and route > your BIG circuits (20,000 4-LUTs) in under 5 minutes? > > If you had to give up some quality (20% in circuit delay > and/or 20% less device utilization than say Xilinx M1), > would you still want to use such a tool? How much quality > would you be willing to give up for high-speed place and > route? > > How much would you be willing to pay for such a tool? (if it > existed) I would not have a use for a tool that produced a less optimal result regardless of speed. The M1 tools already have configurable tradeoffs between processing time and quality of results. The lower quality mode is normally used when you are initially trying a device fit or if you are working a design that does not have difficult constraints. Otherwise, the 20% loss of speed or device utilization can be quite painful in the final design. How about offering a 20% improvement in quality of result with the same execution time??? Now that would be useful to me! -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11007
Hey Nick, how's it going? As you may remember, I'm not with Xilinx (any longer) but I/we teach a lot of their classes for them. I agree with you 66.6%........ > Nick Hartl wrote: > > As long as we are wish listing. > 1.Could Design Manager please close it's child windows automagicly on exit, > or at least bring to front those it can't close? It absolutely should. Next release....... who knows? I'll be SURE to pass this on. Sometimes the simple stuff doesn't seem to make it into the product. ALSO, Sometimes, decision are made for reasons that aren't clear to the casual user - ala: operation across multiple operating systems. > > 2 Could fe.log be put in the reports section? It is such a hassle to chase > it down with Explorer when you want to look at it.. > I BELIEVE that this has been 'fixed' in the upcoming release. > 4. CLB naming conventions. Could M1 default to naming a CLB after the out > nets of the flops before naming them for X or Y outs? In a CLB that has > both direct out LUT signals and flop outs, the X output gives the name to > the CLB, even when X could be called Net $000023 and the flop out could be > called “A_Really_Important_Signal” the CLB will be called Net $00023, now > that just is not right. > This one's a bit more tough... While I agree that the tool should/could (potentially) avoid naming CLBs after clearly temporary names, rules for choosing from one of the (potentially) four outputs is subjective. I agree that FFs should be more important but I know others who would argue the point. If you REALLY want to control the name of stuff you might explore the HBLKNAME attribute on primitives and FMAPS. I assume (dangerously incorrectly perhaps) that you're seeking to control placement via a .UCF file. If you are schematic based, you might consider placing the location or relative location constraint on the schematics. > Just a few things..... there are more but how about these fairly straight > forward ones.... > Your ideas are good. Email them to the Xilinx hotline and the WILL be review for future releases. Keep the mail straight and to the point.... Explain why you're suggesting a specific change, how you'll use it and how it will help you design with the parts/tools. I think you know the drill but others in the group may not. How about Mark P? Do you find he's a good conduit for your ideas? Keep 'em shipping...... -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817Article: 11008
Jordan Swartz wrote: > <SNiped> > Would you be interested in a tool that could place and route > your BIG circuits (20,000 4-LUTs) in under 5 minutes? > Yes would be very usefull for those 'I'll just try this' type scenario's (Oppps - no pun intended!!!) > If you had to give up some quality (20% in circuit delay > and/or 20% less device utilization than say Xilinx M1), > would you still want to use such a tool? How much quality > would you be willing to give up for high-speed place and > route? > Again, only for just the quick test....For final routing, once you have seen the idea work, I would use the Xilinx software. If however you could PPR as well as Xilinx with no performance tradoff's, then I am sure you will be on a winner. > How much would you be willing to pay for such a tool? (if it > existed) > If it is that good Xilinx will buy the technology off you. I am sure they have got a bigger cheque book than most users.... > Thanks in advance for your comments. > > Jordan Swartz > Dept of Electrical and Computer Engineering > University of Toronto > http://www.eecg.toronto.edu/~jsswartz/ No probs Tony -- Sent By Tony Cooper. email: tony.cooper@virgin.net Allow at least 10 working minutes for reply. ;)Article: 11009
Gareth Baron wrote: > Xilinx used to have (or mabe still have) a program called MAKESRC. This program > would take your bitstream file and generate source code (either assembly or C). You > could configure it so that it would produce an array of 'whatevers'. > > Once you get your code you can then compile it into the executeable and do whatever > you like with it. > > Ed McCauley wrote: > > <Snip> Yes I have got it still, and it is still working for me, and has been for about 6 years. It is a brilliant bit of software - why havn't Xilinx incorporated it directly into their tools I don;'t know.....Ho Hummm Tony -- Sent By Tony Cooper. email: tony.cooper@virgin.net Allow at least 10 working minutes for reply. ;)Article: 11010
jsswartz@eecg.utoronto.ca (Jordan Swartz) writes:
> For my Master's thesis, I'm working on a high-speed routing tool
> that is capable of routing a 20,000 4-LUT circuit in 70 seconds.
> (on an architecture similar to the Xilinx 4000EX/XL)
How long does it take for 40,000 and 80,000 LUT (or in CS speak, what
O() does it have)?
> Would you be interested in a tool that could place and route
> your BIG circuits (20,000 4-LUTs) in under 5 minutes?
Interested, yes.
> If you had to give up some quality (20% in circuit delay
> and/or 20% less device utilization than say Xilinx M1),
> would you still want to use such a tool? How much quality
> would you be willing to give up for high-speed place and
> route?
Anything less than optimal is going to hurt. My gut feeling is that
20% is way too much, I'd probably put up with less than 5% only.
> How much would you be willing to pay for such a tool? (if it
> existed)
Dunno.
While it is painful to wait for the result, you can plan accordingly
if you know upfront how long it'll take. That's my biggest gripe with
some of the current tools, they either don't tell you or tell you lies
or are very sensitive to minor changes. Perhaps it would be more
useful if the tools didn't throw away all their analysis of the design
on each run and keep the design hierarchy where appropriate. I don't
mean the thing currently sold as "incremental mode". Another nice
thing would be if you could stop the tool during a run to check the
result and either continue or take what came out until then.
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/{english/}
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 463 - 8325
Article: 11011On Thu, 09 Jul 1998 22:41:43 -0400, Ed McCauley <edmccauley@bltinc.com> wrote: >Hey Nick, how's it going? As you may remember, I'm not with Xilinx (any >longer) but I/we teach a lot of their classes for them. if you intend to carry on "teaching their classes", it might be a good idea to start posting under a pseudonym.Article: 11012
Two Research Associates in Hardware Design and Reconfigurable Computing Department of Computing Imperial College Two posts are available immediately for up to 18 months. The project involves research into theory and practice of hardware design and reconfigurable computing. Preference will be given to applicants who completed or have nearly completed their PhD studies, or with suitable experience. Applicants for the first position should be experienced in theoretical aspects of hardware design, such as hardware verification, partial evaluation, or constraint resolution techniques. Applicants for the second position should be experienced in practical aspects of reconfigurable computing, such as reconfigurable architectures, module generation, or run-time management techniques. Salary on RA1A scale (under review) 17596 - 21892 pounds, inclusive of London allowance, depending on age, qualifications and experience. Applicants should send a current CV to: Dr. W. Luk, Department of Computing, Imperial College, 180 Queen's Gate, London SW7 2BZ, UK. Telephone (+44) 171-594-8313, fax (+44) 171-581-8024, email wl@doc.ic.ac.uk. The applicant should also arrange for two or more support letters to be sent to Dr. Luk at the above address as soon as possible.Article: 11013
Probably because they had a dispute with the firm that wrote it? This is why, I am told, they stopped sending out PDS2XNF and XNFOPT. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 11014
ems wrote: > if you intend to carry on "teaching their classes", it might be a > good idea to start posting under a pseudonym. Why would you suggest that? -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817Article: 11015
I have a board with an XC400E from XILINX and I would like to duplicate it. As I know is the configuration code for the XC4000E stored in an AT17C128 EEprom. If I make the board and copy the eeprom 1:1 can I use it to configure the other board ( which will be just the same ) or do the burn-software write smth on the fpga itself too ?? Does anyone know where I can find XC4000E chips pretty cheap ?? And which is the cheapest software for synthesis,simulation (Abel or VHDL ) ? Thank you in advanceArticle: 11016
The code is just in the EEPROM. The xilinx starts out virgin each time power is reapplied. If you are looking for cheap 4000E, I would suggest you use the spartan parts instead. These are the same as 4000E with some of the extra baggage that is usually not used stripped out and die shrunk. The improved yield allows them to sell for less than the equivalent 4000E parts. I think the cheapest synthesis for these is the xilinx foundation VHDL. Gabriel Margarit wrote: > I have a board with an XC400E from XILINX and I would like to > duplicate it. As I know is the configuration code for the XC4000E > stored in an AT17C128 EEprom. If I make the board and copy the eeprom > 1:1 can I use it to configure the other board ( which will be just the > same ) or do the burn-software write smth on the fpga itself too ?? > > Does anyone know where I can find XC4000E chips pretty cheap ?? > And which is the cheapest software for synthesis,simulation (Abel or > VHDL ) ? > > Thank you in advance -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11017
jsswartz@eecg.utoronto.ca (Jordan Swartz) writes: (snip) >Would you be interested in a tool that could place and route >your BIG circuits (20,000 4-LUTs) in under 5 minutes? >If you had to give up some quality (20% in circuit delay >and/or 20% less device utilization than say Xilinx M1), >would you still want to use such a tool? How much quality >would you be willing to give up for high-speed place and >route? In my designs, speed times density is important. I will run different designs until I get the one that has the highest speed density product. There is some use for fast routing, in quick and dirty testing, but most designs worth putting into production are worth a little extra time routing. The one use I could think of would be a dynamic design, where a running system, probably microprocessor based, would write a design out based on some input, place and route it, then load it and use it. Look at some of the things that VCC is talking about. (probably www.vcc.com). They have boards designed as hardware accelerators. I could imagine a system for, for example, solving differential equations, where it would program the equation into the hardware. (This is just an example, I don't know that it is a useful thing to do.) So, given an equation, the system would generate the design, place and route it, use it to solve the equation, and then never use it again. In this case, where the design is only used for a very short time, P&R speed is important. >How much would you be willing to pay for such a tool? (if it >existed) >Thanks in advance for your comments. >Jordan Swartz >Dept of Electrical and Computer Engineering >University of Toronto >http://www.eecg.toronto.edu/~jsswartz/Article: 11018
Does anyone have or know of a place where I can get a a speed file "3190a.spd" for the Xact 5.1 or 6.0? I have a copy but it has been encrypted and my Xact copy cannot read it. Any help will be appreciated! ThanksArticle: 11019
Yes, I have been routinely using parallel PRBS for high speed digital circuits, where the serial data rate exceeds the FPGA speed, combined with external fast ECL S/P or P/S converters. This configuration has been successfully implemented in several commercial products. A parallel PRBS circuit has the same number of D flip flops of a serial one. For each clock cycle, the state of the parallel circuit changes as it would change in the serial circuit after n clock cycles. One way to convert a serial generator to a parallel one is to start with the serial schematic (shift register plus XOR feedback). Then, for each D flip flop of the shift register, you have to re-arrange its input function in order to meet the previous condition. Example for n=2 Serial (x1) generator Parallel (x2) generator ---------------------------------------------- D2=Q1 D2=XOR(Q3,Q4) D3=Q2 D3=Q1 D4=Q3 D4=Q2 D1=XOR(Q3,Q4) D1=XOR(Q2,Q3) output= Q4 output= first half cycle Q4, second half cycle Q3 QQQQ QQQQ 1234 1234 ---- ---- 1111 1111 0111 0011 0011 0001 1000 1000 0100 0010 0010 1001 1100 1100 0110 1011 1011 0101 1010 1010 1101 1110 1110 1111 repeats! 0111 0111 not yet repeating... 0011 This procedure can be extended to x3, x4 and so on. Also can be used for any polynomial. The parallel circuit has the same "forbidden" state that the serial one has (all outputs at zero for XOR feedback, ones for XNOR feedback), and can be avoided using similar procedures. For BERT purposes you have also to check n bits at a time, and use a combinational encoder followed by an adder instead of a simply error counter. I worked this solution on my own. I would like to hear other solutions from more people. Anecdote: Xilinx supports CRC error checking for the configuration of its LCAs in serial mode (bit at a time), but does not support it in Express Mode (byte at a time). It could have been supported in this way. Hope this helps Juan-Luis Lopez RodriguezArticle: 11020
Bob Myers wrote: > > Actually, I was running on a PII-266 box (128 mb ram, 6 Gb hard disk) > using NT 4.0. I had installed a number of patches from the web site > (such as core_nt12, spd_4kxl_m14, bann_nt3, gui_nt1, li_pc). I haven't > checked the web site in the last two weeks, but I'll go looking there > today to see if any new patches are available. Bob, I had route times like this on a project last year doing a 4026EX design. It was mostly due to the fact that I was migrating some ASIC code that I couldn't change to be emulated in an FPGA. The timing tools had so many levels of logic to look at (about 11 on average) and so many paths that it got bogged down. A few things I tried with varied success was to use the placement from the previous run and turn of the timing engine via an environment variable (forgot which one but ask your FAE). Another thing I did was run each of the parts discretely, that is I ran just the placer with a certain effort and ucf file. Then used the reentry router to route the design with a higher effort. Both of these solutions worked for different designs and failed on some others. All total I did 7 different 4026EX parts that were all migrated ASIC code. Xilinx informed me that they are improving the timing calculator in the PAR tool as this has become a major bottleneck in routing the larger devices. M1.5 should have the first fixes in it and M1.6 may have these issued licked, WE CAN ALL HOPE. Lastly another thing to look at is the current parts meeting your timing goals. For example if you want it to work at 40MHz but the tool comes back with 25MHz then you have a real problem, asking the tool to do the impossible will result in very long times indeed. Did I mention I was on 266MHz HP workstations when I did this work? Hope this helps, TomT... > > What may be causing the problem is that the routing level was set to 5. > I know that 3 is the minimum that's needed with this design before all > nets are routed. Even then, the third pass was completed somewhere in day > 3 or 4 of the 6 1/2 day route. > > In the meanwhile, I'm going to be giving my design to the local Avnet > (Hamilton-Hallmark) group to see if they can determine what the cause > of the lengthy routes might be. > > -Bob -- +------------------------ ---------------------- ----------------------+ : t2design : : 249 Lois Drive : : Louisville, CO 80027 : +------------------------ ---------------------- ----------------------+ : tomt@hdl-design.com * (303)665-6402 * Fax: (303)665-6431 : +------------------------ ---------------------- ----------------------+Article: 11021
> or Memecdesign.com (spin off of Xilinx) ? I don't believe this to be true. They are not a 'spin off' of Xilinx. Some of their employees may have worked for, or done some work for Xilinx, but to call them a 'spin off' is a real stretch. That would mean anyone who worked for IBM was now 'a spin off of IBM' ;-) (an aside joke) ...or did 'you know who' now claim to invent the FPGA too ;-) Austin Franklin darkroom@ix.netcom.comArticle: 11022
Hi, I need to model a 16550 UART, can some one help me out! I need some pointers to the hardware side of the UART. Please e-mail me at sharad@bisquare.com Thanks Sharad -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11023
Does anyone has the footprints from PCI & ISA Bus Slotcard for Protel 2,3 PCB or Orcad PCB? I could not find them in any library . Thank you in advance !Article: 11024
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Let me tell you how this works, and most importantly, why it
works. Also, make sure you print a copy of this article now, so you
can get the information off of it when you need it. The process is very
simple andconsists of THREE easy steps.
==============
HOW IT WORKS
==============
STEP 1:
Get 6 separate pieces of paper and write the following on each piece of
paper:
PLEASE ADD ME TO YOUR MAILING LIST.
$1 US DOLLAR PROCESSING FEE IS ENCLOSED.
(THIS IS KEY AS THIS IS WHAT MAKES IT LEGAL SINCE
YOU ARE PAYING FOR AND LATER OFFERING A SERVICE).
Now get 6 $1.00 bills and place ONE inside EACH of the 6
pieces of paper so the bill will not be seen through the envelope to
prevent theft/robbery. Then, place one paper in each of the 6 envelopes
and seal them. You should now have 6 sealed envelopes, each with a piece
of paper stating the above phrase and an U.S. $1.00 bill.
Mail the 6 envelopes to the following addresses:
#1 Jimmy Eriksson
Tegelbruksv 12C
831 37 stersund
SWEDEN
#2 Rob Martin
263 Freeland drive
Collegeville PA 19426
USA
#3 Patrick "Blunt" Richardson
308 N. Wingate St.
Wake Forest, NC 27587
USA
#4 Jacky Maier
Jacob Jacobstraat 9
2018 Antwerp
Belgium
#5 Paul.W
Blk9, #09-17,
Gloucester Road, S'pore 210009
Singapore
#6 Bill Cheung
P.O.Box 34788
King's Road Post Office
Hong Kong
STEP 2: Now take the #1 name off the list that you see above, move
theother names up (6 becomes 5, 5 becomes 4, etc.) and add YOUR Name as
number 6 on the list. (If you want to remain anonymous put a nickname,
but the address MUST be correct. It, of course, MUST
contain your country, state/district/area, zip code, etc! You wouldn't
want your money to fly away, wouldn't you?).
STEP 3: Now post your amended article to at least 200 newsgroups.
Remember that 200 postings are just a guideline. The more you post, the
more money you make!
Don't know HOW to post in the news groups? Well do exactly the
following:
------------------------------------------------------------------------------------
HOW TO POST TO NEWSGROUPS FAST WITH YOUR WEB
BROWSER:
The fastest way to post a newsletter: Highlight and COPY (Ctrl-C)
the text of this posted message and PASTE (Ctrl-V) it into a plain text
editor (as Wordpad) and save it. After you have made the necessary
changes that are stated above, simply COPY (Ctrl-C) and PASTE
(Ctrl-V) the text into the message composition window, after selecting a
newsgroup, and post it! (Or you can attach the file, without writing
anything to the message window.)
------------------------------------------------------------------------------------
If you have Netscape Navigator 3.0 do the following:
1. Click on any newsgroup like normal, then click on 'TO NEWS'. This
will bring up a box to type a message in.
2. Leave the newsgroup box like it is, change the subject box to
something flashy, something to catch the eye, as "$$$ NEED CASH $$$?
READ HERE! $! $! $" Or "$$$! MAKE FAST CASH, YOU CAN'T LOSE! $$$". Or
you can use my subject title.
3. Now click on 'ATTACHMENTS'. Then click on 'ATTACH FILE'. Find your
file on your Hard Disk (the one you saved from the text
editor). Once you find it, click on it and then click 'OPEN' and 'OK'.
You should now see your file name in the attachments box.
4. Now click on 'SEND'/'POST'. You see? Now you just have 199 to go!
(Don't worry, it's easy and quick once you get used to it.) NOTE: All
the versions of Netscape Navigator's are similar to each other, so
you'll have no problem to do this if you don't have Netscape Navigator
3.0.
------------------------------------------------------------------------------------
! QUICK TIP!
(For Netscape Navigator 3.x and above)
You can post this message to many newsgroups at a time, by simply
selecting a newsgroup near the top of the screen, hold down the
SHIFT, and then select a newsgroup near the bottom of the screen. All of
the newsgroups in/between will be selected. After that, you follow/do
the basic steps, stated below at this letter, except of step #1. You
can go to the page stated below in this letter and click on a newsgroup
to open up the newsgroups window. Once you've done this, in the
same window go to 'OPTIONS', and then mark 'SHOW ALL NEWSGROUPS' and
'SHOW ALL MESSAGES'. Now you can see all the
newsgroups and you can apply easier the above tip.
------------------------------------------------------------------------------------
If you have MS Internet Explorer do the following:
1. Go to the newsgroups and press 'POST AN ARTICLE'. To the new window
type your headline in the subject area and then click in the
large window below. There either PASTE your letter (which it's been
copied from the text editor), or attach the file which contains it.
2. Then click on 'SEND' or 'OK'. NOTE: All versions of MS Internet
Explorer are similar to each other, so you won't have any problem
doing this.
GENERAL NOTES ON POSTING: A nice page where you'll find all the
newsgroups if you want help is http://www.liszt.com/ (When you go to the
home page, click on the link 'Newsgroup Directory'). But I
don't think you'll have any problem posting because it's very easy
once you've found the newsgroups. All these web browsers are similar. It
doesn't matter which one you have. (But it makes it very easy if you
have Netscape Navigator 3.0 or later. You may download it from the
Internet if you don't have it.) You just have to remember the basic
steps, stated below.
BASIC STEPS FOR POSTING:
1. Find a newsgroup and you click on it.
2. You click on 'POST AN/NEW ARTICLE' or 'TO NEWS' or
anything else similar to these.
3. You type your flashy headline in the subject box.
4. Now, either you attach the file containing your amended letter, or
you PASTE the letter. (You have to COPY it from the text editor,
ofcourse, from before.)
5. Finally, you click on 'SEND' or 'POST' or 'OK', whatever is there.
------------------------------------------------------------------------------------
**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL
MAKE! BUT YOU HAVE TO POST A MINIMUM OF 200**
That's it! You will begin receiving money from around the world within
days! You may eventually want to rent a P.O.Box due to the large amount
of mail you receive. If you wish to stay anonymous, you can
invent a name to use, as long as the postman will deliver it.
**JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT. **
------------------------------------------------------------------------------------
================
Now the WHY part:
================
Out of 200 postings; say I receive only 5 replies (a very low
example). So then I made $5.00 with my name at #6 on the letter. Now,
each of the 5 persons who just sent me $1.00 make the MINIMUM 200
postings, eachwith my name at #5 and only 5 persons respond to each of
the original 5, that is another $25.00 for me, now those 25 each make
200 MINIMUM posts with my name at #4 and only 5 replies
each, I will bring in an additional $125.00! Now, those 125 persons
turn around and post the MINIMUM 200 with my name at #3 and only receive
5 replies each, I will make an additional $626.00! OK, now
here is the fun part, each of those 625 persons post a MINIMUM 200
letters with my name at #2 and they each only receive 5 replies, that
just made me $3,125.00! Those 3,125 persons will all deliver this
message to 200 newsgroups with my name at #1 and if still 5 persons per
200 newsgroups react I will receive $15,625,00! With an original
investment of only $6.00! AMAZING! And as I said 5 responses is
actually VERY LOW! Average are probable 20 to 30! So lets put those
figures at just 15 responses per person. Here is what you will make:
at #6 $15.00
at #5 $225.00
at #4 $3,375.00
at #3 $50,625.00
at #2 $759,375.00
at #1 $11,390,625.00
When your name is no longer on the list, you just take the latest
posting in the newsgroups, and send out another $6.00 to names on the
list, putting your name at number 6 again. And start posting again. The
thing to remember is, do you realize that thousands of people all over
the world are joining the internet and reading these articles everyday,
JUST LIKE YOU are now!
So can you afford $6.00 and see if it really works? I think so...
People have said, "what if the plan is played out and no one sends you
the money? So what! What are the chances of that happening when
there are tons of new honest users and new honest people who are joining
the internet and newsgroups everyday and are willing to give it a
try? Estimates are at 20,000 to 50,000 new users, every day, with
thousands of those joining the actual Internet. Remember, play FAIRLY
and HONESTLY and this will work. You just have to be honest. By the way,
if you try to deceive people by posting the messages with your name in
the list and not sending the money to the rest of the
people already on the list, you will NOT get as much. Someone I talked
to knew someone who did that and he only made about $150.00,
and that's after seven or eight weeks! Then he sent the 6 $1.00 bills,
people added him to their lists, and in 4-5 weeks he had over $10k.
This is the fairest and most honest way I have ever seen to share the
wealth of the world without costing anything but our time! You also may
want to buy mailing and e-mail lists for future dollars. Make sure you
print this article out RIGHT NOW, also. Try to keep a list of
everyone that sends you money And always keep an eye on the
newsgroups to make sure everyone is playing fairly. Remember that
HONESTY IS THE BEST POLICY. You don't need to cheat the basic idea to
make the money!
GOOD LUCK to all and please play fairly and reap the huge
rewards from this, which is tons of extra CASH. Please remember to
declare your extra income. Thanks once again...
==================================================
LEGAL? ? ? (Comments from Bob Novak who started this new
version.)
"People have asked me if this is really legal. Well, it is! You
are using the Internet to advertise you business. What is that business?
You are assembling a mailing list of people who are interested in home
based computer and online business and methods of generating income at
home. Remember that people send you a small fee to be added to
your mailing list. It is legal.
" So, build your mailing list, keep good accounts, declare the
income and pay your taxes. By doing this you prove your business
intentions. Keep an eye on the newsgroups and when the cash has
stopped coming (that means your name is no longer on the list), you
just take the latest posting at the newsgroups, send another $6.00 to
the names stated on the list, make your corrections (put your name at
#6) and start posting again.
=================================================
NOTES:
*1. In some countries, the export of the country's exchange is illegal.
But you can get the license to do this from the post office, Explaining
the above statements (that you have an online business, etc. You may
have to pay an extra tax, but that's OK, the amount of the incoming
money is HUGE! And as I said, a few countries have that restriction.
*2. You may want to buy mailing and e-mail lists for future dollars. (Or
Database or Spreadsheet software.)
*3. If you're really not sure or still think this can't be for real,
please
print a copy of this article and pass it along to someone who really
needs the money, and see what happens.
*4. You should start getting responses within 1-2 weeks.
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