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The bit file can not be used directly, because it has a variable length header at the beginning. After the header, the remaining data is directly downloadable, so all you need to do is either create a new file with the header removed, or do what I do: leave the header in there, and the download routine knows how to skip the header. Here's how: 00 00 09 0F F0 0F F0 0F F0 0F F0 00 00 01 61 00 0D a 10 73 72 61 6D 74 65 73 74 2E 6E 63 64 00 62 00 0C sramtest.ncd b 20 34 30 32 38 65 78 68 71 32 34 30 00 63 00 09 39 4028exhq240 c 9 30 38 2F 30 35 2F 32 30 00 64 00 09 31 34 3A 32 31 8/05/20 d 14:21 40 3A 33 36 00 65 00 01 46 43 FF 20 A3 21 1F 5F F7 :36 e FC ! _ 50 EF DE F7 EF 7D FD EF 7E F7 EF 7D FD FB DF B5 FB } ~ } The FF 20 is the real start of the bitstream, so just skip over stuff till you see this sequence (at byte 49 in my example), then start sending bits, including the FF 2X . Remember that the data is shifted from the MSB of each byte in sequence, so the starting sequence is ALWAYS 1 1 1 1 1 1 1 1 0 0 1 0 Note that the '0' of the '20' is the top nibble of the length code, and for chips up to XC4044, it is '0'. For 4052XL, 4062XL, and 4085XL it is a '1', so look for FF 21 Philip Freidin In article <6nrb1d$p6n$1@nnrp1.dejanews.com> dfrevele@li.net writes: >easy question: > >I want to configure a single Xilinx from a microprocessor. Can I just download >the .bit file produced from the implementation tools? I've previously loaded >multiple daisy-chained Xilinxs from a microprocessor and had to use makeprom >(promgen) to produce the download file. But for a single device can the .bit >file be used directly. > > >Don Frevele >GEC-Marconi Hazeltine Corp. > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 10951
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Hello,
I have a small Engineering firm that can possibly help. We have
Xilinx experience, but limited DSP experience. Flat rates are US $
70/hr. or one big fat capped project price. Have you looked at the
Xilinx cores ? or Memecdesign.com (spin off of Xilinx) ? Please respond
directly to Jsmeltze@columbus.rr.com, I don't know if I will ever be in
this news group again.
John
tiltonjones@my-dejanews.com wrote:
> Hi,
>
> My company is looking for a consultant to help us out on a DSP design
> project
> using Xilinx FPGA. We have not used this technology previously but it
> seems
> like a good approach for this particular project.
>
> Can anyone recommend a good consultant in this area? What is the
> going rate
> for this kind of service?
>
> Any pointers appreciated,
>
> Tilton Jones.
>
> -----== Posted via Deja News, The Leader in Internet Discussion
> ==-----
> http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member
> Forum
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email;internet: jsmeltze@columbus.rr.com
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Article: 10952Altera's PLS-WEB 8.3 software is available for download at http://www.altera.com/html/products/pls-web.html. You can also find other free or low-cost downloads of programmable logic software on The Programmable Logic Jump Station at http://www.optimagic.com/lowcost.html. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- koh bongseok wrote in message ... >Hello. > >I want to download MAX+PLUS 8.1 for pc >please tell me where this program is located > >Thank you. > >mail me: stonesys@chollian.net > >Article: 10953
--------------C99A19F0202A516BFD3AA39C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit FPGA Downloader for Altera FPGA/EPLD Works with any voltage of FPGA I/O pins 1.8 - 5.0 V Please visit us at http://www.jps.net/eugenef --------------C99A19F0202A516BFD3AA39C Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> FPGA Downloader for Altera FPGA/EPLD <BR>Works with any voltage of FPGA I/O pins 1.8 - 5.0 V <P><B><FONT SIZE=+1>Please visit us at <A HREF="http://www.jps.net/eugenef">http://www.jps.net/eugenef</A></FONT></B> <BR> <BR> </HTML> --------------C99A19F0202A516BFD3AA39C--Article: 10954
The more I read about Foundation, the more I want to stay with my ancient Viewlogic 4 and XACT6.01. I never saw anything like those problems. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10955
Another *really* helpful post from Philip - well done! Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10956
Greetings, I would like to apologize in advance if this is not the right place to seek for assistance on this issue. I'm looking for some sort of information which could give me a rough idea on how many gate counts will be required to implement the features like serial port, parallel port, etc. as those legacy PC I/O devices so I could estimate how big the chip will if I plan to integrate those aforementioned functions into the design. Thanks in advance for your kindly help. Regards, David Lin r43475@email.sps.mot.comArticle: 10957
Sure dominick. How can I help? -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Dominick Cafarelli wrote: > > Has anyone done CRC's or Pseudo Random Bit Sequences (BERT patterns) in > paralell in FPGA's. > > THanks, > DominickArticle: 10958
I am routing a XC4052XL part, which is using 68% of CLBs. The last time I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. Are routes like this typical??? I am setting my clock period to 25 ns in the .ucf file, along with specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). Any suggestions welcomed as to what I can do to reduce the length of place & route. Regards, BobArticle: 10959
You might take another look at your design style. If your average combinatorial logic delays between registers are more than about half of the 25ns cycle time, it makes it alot harder to find a solution that will meet timing. Most likely, this is the cause of the long route times. It will also help to floorplan the design. Xilinx has a beta floorplanner for M1 which has most of the functionality of the floorplanner in Xact6. If you are real nice to your FAE, he should be able to get you a copy. Otherwise, you can floorplan using lots of graph paper and adding RLOCs to everything like we used to do. Of course, if you are using an HDL, using RLOCs to do the floorplanning is almost out of the question. Even with the floorplanner, it can get confusing as to what is what when dealing with synthesized logic. With proper attention to the device architecture and a little floorplanning, there is no reason for the route to take more than a few hours. Bob Myers wrote: > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10960
You might take another look at your design style. If your average combinatorial logic delays between registers are more than about half of the 25ns cycle time, it makes it alot harder to find a solution that will meet timing. Most likely, this is the cause of the long route times. It will also help to floorplan the design. Xilinx has a beta floorplanner for M1 which has most of the functionality of the floorplanner in Xact6. If you are real nice to your FAE, he should be able to get you a copy. Otherwise, you can floorplan using lots of graph paper and adding RLOCs to everything like we used to do. Of course, if you are using an HDL, using RLOCs to do the floorplanning is almost out of the question. Even with the floorplanner, it can get confusing as to what is what when dealing with synthesized logic. With proper attention to the device architecture and a little floorplanning, there is no reason for the route to take more than a few hours. Bob Myers wrote: > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10961
You might take another look at your design style. If your average combinatorial logic delays between registers are more than about half of the 25ns cycle time, it makes it alot harder to find a solution that will meet timing. Most likely, this is the cause of the long route times. It will also help to floorplan the design. Xilinx has a beta floorplanner for M1 which has most of the functionality of the floorplanner in Xact6. If you are real nice to your FAE, he should be able to get you a copy. Otherwise, you can floorplan using lots of graph paper and adding RLOCs to everything like we used to do. Of course, if you are using an HDL, using RLOCs to do the floorplanning is almost out of the question. Even with the floorplanner, it can get confusing as to what is what when dealing with synthesized logic. With proper attention to the device architecture and a little floorplanning, there is no reason for the route to take more than a few hours. Bob Myers wrote: > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10962
You might also take another look at your design style. If your average combinatorial logic delays between registers are more than about half of the 25ns cycle time, it makes it alot harder to find a solution that will meet timing. Most likely, this is the cause of the long route times. You might also consider floorplanning the design. Xilinx has a beta floorplanner for M1 that has most of the functionality of the Xact6 floorplanner. If you are really nice to your FAE, he'll probably give you a copy to play with. If not, you can floorplan using lots of graph paper and RLOC'ing everything like we used to do in the days before floorplanner. Of course, if your design is synthesized HDL, the graph paper floorplanning won't be very useful. For that matter, even the graphical floorplanner is not all that useful for synthesized designs, as it can be hard to tell what is what. If you pay proper attention to the device architecture in your design and you floorplan it, there is no reason the place and route should take more than a few hours on your machine. On the other hand, throw a random design at it without regard to how it maps to the device, constrain it's timing, and well .... six days sounds about right. Bob Myers wrote: > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10963
You might also take another look at your design style. If your average combinatorial logic delays between registers are more than about half of the 25ns cycle time, it makes it alot harder to find a solution that will meet timing. Most likely, this is the cause of the long route times. You might also consider floorplanning the design. Xilinx has a beta floorplanner for M1 that has most of the functionality of the Xact6 floorplanner. If you are really nice to your FAE, he'll probably give you a copy to play with. If not, you can floorplan using lots of graph paper and RLOC'ing everything like we used to do in the days before floorplanner. Of course, if your design is synthesized HDL, the graph paper floorplanning won't be very useful. For that matter, even the graphical floorplanner is not all that useful for synthesized designs, as it can be hard to tell what is what. If you pay proper attention to the device architecture in your design and you floorplan it, there is no reason the place and route should take more than a few hours on your machine. On the other hand, throw a random design at it without regard to how it maps to the device, constrain it's timing, and well .... six days sounds about right. Bob Myers wrote: > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10964
Oops. First day with the new browser! > - -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 10965
rjmyers@dseg.ti.com (Bob Myers) wrote: > >I am routing a XC4052XL part, which is using 68% of CLBs. The last time >I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. >Are routes like this typical??? > >I am setting my clock period to 25 ns in the .ucf file, along with >specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > >Any suggestions welcomed as to what I can do to reduce the length of >place & route. > >Regards, >Bob > Try floor planing. I have a highly floor planned 4062XL 93% CLB 66% flops 74% 4 input func gen that place and routs in 2 hours 47 min on my Pro 200MHz box with 256M RAM. This is a -3 with a 40ns clock There is a very small picture of the floor plan at http://diabloresearch.com/pages/dsp.html (We have Fliptronics to thank for this floor planing job. Philip merged 3ea 4025Es into one 4062XL for us.) An hour of floor planing the data path once, will save a day of place and routing each time you place and rout. This assumes schematic capture, where hierarchical floor planing is practical using RLOCs. Dave Decker Diablo Research Co. LLC Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 10966
Actually, the timespecs that I'm using for almost all of the pairings (pads-to-pads, pads-to-ffs, etc.) are set to be at 75 ns. It was suggested from the local Avnet/Hamilton-Hallmark FAE that I put the clock spec in. I know about the floorplanner software coming back, along with the old Neocad "divide & conquer" engine being available too. Since this is my first Xilinx design (had done Altera in the past), I was just looking to see if anyone else has run into long times with large designs. -bob In article <35A235C8.3FCBC498@ids.net>, Ray Andraka <no_spam_randraka@ids.net> writes: > You might take another look at your design style. If your average > combinatorial logic delays between registers are more than about half of the > 25ns cycle time, it makes it alot harder to find a solution that will meet > timing. Most likely, this is the cause of the long route times. It will also > help to floorplan the design. Xilinx has a beta floorplanner for M1 which has > most of the functionality of the floorplanner in Xact6. If you are real nice > to your FAE, he should be able to get you a copy. Otherwise, you can > floorplan using lots of graph paper and adding RLOCs to everything like we > used to do. Of course, if you are using an HDL, using RLOCs to do the > floorplanning is almost out of the question. Even with the floorplanner, it > can get confusing as to what is what when dealing with synthesized logic. > > With proper attention to the device architecture and a little floorplanning, > there is no reason for the route to take more than a few hours. > > Bob Myers wrote: > > > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > > Are routes like this typical??? > > > > I am setting my clock period to 25 ns in the .ucf file, along with > > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > > > Any suggestions welcomed as to what I can do to reduce the length of > > place & route. > > > > Regards, > > BobArticle: 10967
Bob Myers wrote: > > I am routing a XC4052XL part, which is using 68% of CLBs. The last time > I did the route, on a PII-266 box with 128 mb ram, it took over 6 days. > Are routes like this typical??? > > I am setting my clock period to 25 ns in the .ucf file, along with > specifying a number of other time specs (pads-to-pads, pads-to-ffs, etc.). > > Any suggestions welcomed as to what I can do to reduce the length of > place & route. > > Regards, > Bob If your system is Win95 based, there is at least 6 patches that needs to be applied to M1.4, one of them address a speed issue on Win95 compared with NT system. All patches should be on Xilinx web site and the one that address the speed issue is win95_m14.zip. Hope this help -- Marc Boulais N O R T E L marc_boulais@com.nt Northern Telecom To reach me, re-order COM and NT in the address.Article: 10968
To use in a chip, I had to design such a logic that had 2 vectors of input, say, a[1:0] and b[3:0], and one vector of output, say, c[3:0]. Design entry is Verilog. I tried to model the logic in algorithmic level but I couldn't do it. Therefore I have written a "function", which includes a case, that defines the output for all of the possible states of a[1:0] and b[3:0], respectively. UDP-alike. I synthesized the approach above on XC4062XL and 6 CLB's came out. I found this number too much. A colleague here had designed a small software during his MSc which gives 1st canonic expansions of several combinational logic functions. The program tries to find common minterms. I entered the output of this program and I obtained 7 CLB's!! 1. Is it possible to put 6-bit input (a[1:0] + b[3:0] = 6 bits) and 4-bit output in 2 CLB's only? 2. Does coding technique play a dramatical role for optimizations? I can't see any improving by partioning combinational logic functions into small sub-functions. Synthesizer is Synplify. -- - Vous me prenez pour l'oncle Picsou? Utku Ozcan, http://www.ehb.itu.edu.tr/~utku/Article: 10969
Does anyone know where I can find a PCB which has a least a footprint or
socket for a Xilinx 4085 in a PG559 package.
Thanks in advance,
David Brown
email : dbrown@adelphia.net
Article: 10970The problem with the M1.x ABL2EDIF is very bad. The only way around it is to use the old path via the .pld file and let NGDBUILD create and XNF file. Comparing the 2 approaches it's clear that the EDIF route can use 50% more CLBs & run 1/3 slower for the same ABEL design. I discussed this with Xilinx earlier this year & found that (i) the responsibility for fixing it was placed with DataIO and (ii) Xilinx intend to abandon ABEL anyway. If (ii) then how am I going to specify my state machines. ABEL's built in state machine syntax is a much nicer way to define them than Foundation's SM editor or VHDLArticle: 10971
Paul Walker wrote: > But I begin to tear (what's left of) my hair out when saving an edit to > a symbol, and the message appears "Incorrect Pin Name" and it refuses to > save the symbol; No indication which pin, nor what is wrong with the > name; nothing in Help to say what a correct pin name is; nothing > produced from the menu item "test symbol" other than the same "Incorrect > Pin Name". ...snip... > This prompts me to write up a few other frustrations. If anyone has any > good ways to avoid them, or has similar experiences with other parts of > Foundation or with other products, please let us know. Have you sent this to Xilinx? I know it feels a lot like tossing your advice down a well, but I do believe that user inputs count, and if enough people complain about a problem it gets bumped up in priority. Ultimately the problems that people complain the most about are the ones that get fixed first... or at all. > Auto-Placement: The critical timing on a Spartan part, a single level of > logic between the two edges of a clock, was ok but about 80% logic delay > so I wondered if a faster device would go faster. With the same > constraint file, a 4kE-1 actually went slower, not because of this > critical path, but because other paths had been made worse by the > ugliest placement imaginable. I spent about half an hour with EPIC doing > a crude placement based on the rats' nest, and without any reference to > the logic design. Two or three passes of EPIC's router then produced a > routing that went almost twice as fast as the original auto > implementation. There are other controls over the PAR process that might help without the handwork. You can set the options to spend more time in the placement stage. The default settings tend to get an adequate solution for many designs without spending a lot of computer time. When you have a tougher problem to solve, you need to tell the software to think about it harder. > Copying projects: When you copy a project, the UCF file that constrained > timings or pins is copied across, but a dummy new one is generated for > the new project. Design Manager proceeds to use this new file rather > than the old one. The documentation does actually say this, but there is > a big inconsistency between Project Manager's concept of attaching files > to the project, and Design Managers's concept of using default filenames > regardless. > > Upper and Lower Case: There are dire warnings in some of the > documentation that while M1.4 is case insensitive, M1.5 will be case > sensitive and so users should be consistent. Fine, I'd love to use > signal names such as TxClock and RxClock, and am totally happy to be > consistent with the upper and lower case. But the Schematic entry > package that comes with Foundation insists that all signal names are > upper case, regardless of what I type. I would, politely as I can, > suggest to Xilinx that this is INCONSISTENT_AND_VERY_ANNOYING. I agree with this 100%. But I know what they will tell you. The M1 software was written by Neocad on Unix platforms by Unix programmers. They are very used to case sensitivity and think it is a good idea. When I tried using the Neocad software, I almost went nuts trying to keep up with lowercase commands and upper case net names, lower case options and upper case constraints... This was one of the main reasons I didn't buy their software. Now Xilinx would have a major rewrite to convert all of the M1 software to be case insensitive. One the other hand, the front end software was written by Aldec from a hardware engineer's viewpoint (I DIDN'T KNOW THERE WAS SUCH A THINK AS A CAPS LOCK KEY??? HOW DO U TURN IT OFF?) Likewise, it would take a lot of work to convert this software and I don't know that Xilinx is even responsible for maintenance. I think Aldec is still doing the work in order to keep it completly compatible with their products. I thought that the M1.4 software had this same problem??? Are you sure that M1.4 is not case sensitive? > The old PLDShell software produced by Intel and canned by Altera was and > still is extremely good. We have a number of designs in PLDShell, and > several of these are now designed for a fan-in of four, so are optimised > for Xilinx (and other) FPGA LUTs. We can convert the PLDShell to Abel > for input to Foundation, and this poses no problem. What causes more of > a problem is that ABL2EDIF seems to do its own optimisations which turn > our one level of logic into two or three levels. What's more, there is > no way to turn this optimisation off. Of course it is possible to > convert to VHDL, but at a large increase in cost, a large learning time, > and the expectation suggested by many contributors to this news group > that the performance will be poor. If anyone has any suggestions of how > to take a design for 4-input LUTs straight through to an implementation > which preserves the original design, I'd be most grateful. I once developed a schematic symbol that consisted of a 16 input mux and an FMAP with a 16 digit parameter which could be used to define a 4 input function generator for Xilinx parts. However this only worked under Viewlogic for DOS (don't remember that version number). When they went to Windows the parameter passing stopped working. I also like to think and work directly in LUTs, but Xilinx has never thought this to be a good idea. You could probably do this in VHDL. But I don't know how you could keep the optimizer from changing the result other than attaching a property to preserve nets. But the optimizer shouldn't make things worse. That wouldn't be optimization, now would it? ;-> -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10972
Utku Ozcan wrote: > > To use in a chip, I had to design such a logic that > had 2 vectors of input, say, a[1:0] and b[3:0], and > one vector of output, say, c[3:0]. Design entry is Verilog. > > I tried to model the logic in algorithmic level but > I couldn't do it. Therefore I have written a "function", > which includes a case, that defines the output for all > of the possible states of a[1:0] and b[3:0], respectively. > UDP-alike. > > I synthesized the approach above on XC4062XL and 6 CLB's > came out. I found this number too much. A colleague here > had designed a small software during his MSc which gives > 1st canonic expansions of several combinational logic > functions. The program tries to find common minterms. > I entered the output of this program and I obtained 7 CLB's!! > > 1. Is it possible to put 6-bit input (a[1:0] + b[3:0] = 6 bits) > and 4-bit output in 2 CLB's only? > > 2. Does coding technique play a dramatical role for optimizations? > I can't see any improving by partioning combinational > logic functions into small sub-functions. The answer to 1 purely depends on the functions you want to implement. You have four functions of 6 inputs. Each function is entirely separate. You may be able to simplify the input/output dependancies by analysing your 6 input lookup table. If not, you can not put your logic into 2 CLBs. Each half of a CLB, the function generator (FGEN) only has four inputs. So it can't possibly implement a 6 input function. You can put any 4 input function into a single FGEN. You can put any 5 input function into a single CLB. To implement any 6 input function, you need two CLBs plus a FGEN to combine the outputs from the CLBs. This would give you 10 CLBs total (I don't remember if the H FGEN can be used for the combine from inputs). However if your logic is not worse case, then you might be able to get away with fewer than two and a half CLBs per output. But, my guess is that if you can't find an equation to define the outputs, then it is not likely you will find a solution that will fit in fewer than the 6 CLBs you got with the Synplify software. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10973
Hi All,
I'm using Express as a schematic entry package
targeting a Xilinx XC3x00A using the Xilinx M1.4
backend tools. I'm having trouble setting
TIMESPECS the way I used to using another
schematic entry package.
Previously, I would add "TNM=MYGROUP" as a parameter
for the flip-flops and counters. Then I would place
a line like "TIMESPEC TS001=FROM:MYGROUP:TO:MYGROUP=30"
in a user constraint file (.ucf).
With Express, I used one of the Xilinx M1 macros
which came with Express to set a "TNM" user property
for some flip-flops and added a line like the one
above to the .ucf file. I then tried to compile the
design but the M1 tools cannot find the "TNM"
parameters even though they do exist in the edif
netlist. I have also tried a number of variations on
this to no avail.
Using the Orcad macro supplied with Express the EDIF
netlist looks like
(property TNM (string "MYGROUP"))
and I've also tried something that produced
(property PARAMS (string "TNM=MYGROUP"))
The error message I'm getting is as follows:
WARNING:basts:19 - The user TIMEGRP "MYGROUP" does
not contain any elements such as pads, latches,
flip-flops, or RAMs, either from direct references
or from include groups. This can be caused either
by other time groups that are empty of these
elements; or if the TIMEGRP was defined as a
predefined group (i.e. FFS(Q*)) and the predefined
group has no elements (i.e., FLIPFLOPS for FFS(Q*)).
Please modify this TIMEGRP so it contains elements.
It looks like the Orcad netlister is writing it out in a
format that the Xilinx software does not understand.
Has anybody else gotten this to work?
Thanks,
Erik
--
-------------------------------
Erik de Castro Lopo
Fairlight ESP Pty Ltd
e.de.castro AT fairlightesp.com.au
Article: 10974The weird assignment of the DOUT pin as a clock input is not unique to the Spartan family. This "annoyance" permeates all the XC4000 families: XC4000, 4KE, 4KL, 4KH, 4KD, 4KEX, 4KXL, and 4KXV, Spartan. This is the price of compatibility :-) One of the challenges of FPGA design is to build a family of devices where any given die (ie specific device size in CLBs) can be placed into any given package (ie pc84, pq208, etc), and all special function pins are always the same package pin. This allows you to pick a package, and change the device size at a later date, without having to re-do the PCB. This can be quite hard to plan, since you need to put signals on bond pads of the die that will be bonded regardless of package, and you need to do this in a compatible way across multiple device sizes. This is also why the the address lines for the parallel eprom config mode are not on adjacent pins on a device like a pq208. The intermixed non address pins are the ones that are not bonded when the die is placed in a smaller package. Xilinx has done this better than any other vendor. Unfortunately this conflicting directional use of the DOUT pin was set in the first XC4000 devices, and has been maintained in all products since. Since the XC4000 devices all have at least 8 clock pins, and good designs only need one clock pin, I recommend you pick one of the other clock pins for you clock input, and use DOUT as an output pin. If you really must use it, then the correct way would be to supply the clock to this pin via a tristateable driver, that is held tristate with either HDC, LDC, or DONE. This pin is always an output during configuration, even if it is the only chip being configured (since there is no way to tell it whether there is a follow on chip in daisy chain). This is probably just as well as this DOUT pin function can be very useful in debugging config issues. Philip Freidin In article <6nr61t$god$1@nnrp1.dejanews.com> dfrevele@li.net writes: >I'm doing a design with a Spartan S30 in a PQ208 package and noticed what I >consider an odd pin assignment. Pin P154 is labeled "I/O, SGCK4, (DOUT)" . So >during configuration the pin acts as DOUT which is an _OUTPUT_ and after that >I can make it SGCK4 which is an _INPUT_. Is this correct? > >If I want to use this pin as a global clock buffer I have to provide a >resistor or something to prevent contention? Is this pin an output during >configuration even if it is the only device being configured? > >Was this a good pin assignment made by Xilinx? > >Don Frevele >GEC-Marconi Hazeltine Corp. > >-----== Posted via Deja News, The Leader in Internet Discussion ==----- >http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
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