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This shifting did remind me to a similar problem.
In one of my designs I need a functions which finds the first 1
in an array, starting from a certain position.
E.g. I have an array of 32 bits (0 to 31), and I need to find the
first position where a '1' is available, starting from (after) a
certain position. If no '1' is found either the start position could
be given back, or a flag, or e.g. 32.
The point is that this function needs to be as fast as possible, and
implemented in a good way into an FPGA (with 4input lookup tables).
Any suggestions/ideas to make an efficient way to obtain this ?
Thanks in advance
--
Koenraad SCHELFHOUT
Switching Systems Division http://www.alcatel.com/
Microelectronics Department - VA21 _______________
________________________________________\ /-___
\ / /
Phone : (32/3) 240 89 93 \ ALCATEL / /
Fax : (32/3) 240 99 88 \ / /
mailto:ksch@sh.bel.alcatel.be \ / /
_____________________________________________\ / /______
\ / /
Francis Wellesplein, 1 v\/
B-2018 Antwerpen
Belgium
Article: 11076If you just need to find the first one, you can use the carry chain to get a one-hot indication of the position of the first one and then encode it if necessary. This is faster than a combinatorial merged tree for data widths from 5 bits to more than 32 bits. For 5 or less bits, using the LUT is easier and faster. If you can accept pipelining or if the carry chain is not available, you can use a merged tree to locate the first one quickly. The tree should compute a 'bar-graph' function of the input so that all bits before the first one are zero and the rest are one. The bar graph is then decoded into a one-hot and then to your encoded position (the one-hot and encoded position decodes can be merged). If you want to shift or rotate the input data so that the first one is in the msb position, you don't need to explicitly detect the position of the first one. Instead, roll the detect into the barrel shift/rotate and do the rotation so that the largest shift is done first. That way, you shift by 2^n if the top 2^n bits are zero, or pass unchanged at each level in the shifter where n decreases by one for each level in the shifter. If you need to find the first one after a given position you can either mask the higher bits, or rotate the input so that the first position to be examined is at the top (using a barrel shift). Koenraad Schelfhout VH14 8993 wrote: > This shifting did remind me to a similar problem. > In one of my designs I need a functions which finds the first 1 > in an array, starting from a certain position. > E.g. I have an array of 32 bits (0 to 31), and I need to find the > first position where a '1' is available, starting from (after) a > certain position. If no '1' is found either the start position could > be given back, or a flag, or e.g. 32. > > The point is that this function needs to be as fast as possible, and > implemented in a good way into an FPGA (with 4input lookup tables). > > Any suggestions/ideas to make an efficient way to obtain this ? > > Thanks in advance > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11077
Carl Christensen wrote: > > While I agree with Ray Andraka's response I just wanted to point out one > thing. > > Why floorplan a 4028? The M1 routing engine combined with all the routing > resource in the 4028 make floorplanning a questionable effort. Bigger Parts > or old 4025s I can see but a 4028????? > > Some good timing constraints to drive the placement should be sufficient in > most cases. Because what "should be sufficient in most cases" may not be sufficient in *your* case. I recently had a timing problem with a 4028XL-based design which, among other things, compared a 128-bit input vector to 4 programmable patterns (could require any input bit HIGH, LOW, or DON'T CARE) and produced 4 output bits. Time budget for the pattern match was about 25 ns in a -3 part, about 50% logic density and 97% I/O usage (HQ 240 package). All the I/O's were pin-locked. The logic-only delay (input IOB, 3 CLB's, output IOB) was only about 12 ns, but with just timing constraints, M1 par couldn't do the job. On closer examination, the problem was placement of the RAM's which did the pattern lookup--par was pushing them to the center of the chip (probably to connect them to longlines for PROGRAMMING the pattern, the speed of which was not an issue for me). Simple floorplanning (forcing the RAM's to be somewhere in the vicinity of their associated IOB's) with LOC attributes allowed the design to meet timing and me to get on with my life. Floorplanning doesn't always work, nor is it always needed, but it is a useful addition to your bag of tricks, and should not be dismissed as "questionable."Article: 11078
The EDTN network has been expanded to include the PLD Design Center. In addition to product information and commentary, a new Tech Notes section has been added. This entire PLD Design Center is updated each week. We invite your visit. http://www.edtn.com/pld Murray Disman EditorArticle: 11079
Hi, I am very new to FPGA field. I've been asked to add something like memory buffer(~160 bit) to our current design(prototyping) which uses MAX9000. I am just wondering if I would have to place 160 registers as memory buffer? or if there is any other way/trick I can use to acheive the same result? (other than RAM device with look-up table). Second question is about CRC-parallel. I read the Altera article on parallel CRC but I am not sure I understand how to implement it in hardware. Could someone describe to me how to implement in hardware? Our design calls for 31 bit data with 8 bit CRC, does the parallel method work here? Thank you very much. Lawrence HauArticle: 11080
Brad Smallridge wrote: I need a hardware implementation to find a unique number for a bit pattern that is shifted. Below is a four bit example although our requirements are for something larger: Input > Transform 0000 > 0000 0001 > 1000 0010 > 1000 0011 > 1100 0100 > 1000 0101 > 1010 0110 > 1100 0111 > 1110 1000 > 1000 1001 > 1001 1010 > 1010 1011 > 1011 1100 > 1100 1101 > 1101 1110 > 1110 1111 > 1111 Obvisously, all I did here was to shift the input pattern until it maximised. The output of the transform is shift invarient, ie. 0001 maps to the same number as 0100. We are considering doing this,shifting and testing for max, however, it takes a lot of clock cycles. I would rather have a logic gate solution. A look-up-table approach is too costly for the input width we have in mind. The transform can also compress data, for example, the 4 bit example above has 16 input vectors and maps to only 10 outputs. Thanks in Advance, Brad Smallridge www.sightech.com Rickman wrote: This is a problem that has been designed many times before. This is the same as the normalization step in a floating point add/sub. You count the leading zeros in the mantissa and shift left the result. This consists of two circuits; one to count the leading zeros, and a barrel shifter to shift the data by the count amount. The barrel shifter is trivial to design although it will take a lot of gates to implement as the word size gets large. I don't remember the best way to design the leading zero counter, but I can suggest one that will work. The brute force method is to add the zeros one bit at a time masking all bits after a one is detected... (be sure to view with a monospaced font) MSB LSB | | | | | | | +--O +--O +--O +--O | |---|-|--R->---|-|--R->---|-|--R--> o o o ---|-|--R->---| | | | | | | | | | | | | INV NOR NOR NOR NOR NOR | __|__ __|__ __|__ __|__ __|__ SHIFT | | | | | | | | | | | COUNT +-| + |===>| + |===>| + |===> ==| + |===>| + |===> |_____| |_____| |_____| |_____| |_____| OUTPUT The count that comes out will be 5 bits wide. This will have a slow ripple time. But that can be sped up by performing parts of the computation in parallel like a carry look ahead adder. Brad Smallridge wrote: Hmm. Good start but consider these two bit fields: 01100011010 01101011000 which, would shift only once according to your algorithm, but are non-the-less shift invarient equivalent. Brad Smallridge www.sightech.com Rickman wrote: I may not understand your question. I thought you were asking for an IMPLEMENTAION of your agorithm to shift a bit pattern so that the most significant "one" bit ended up in the MSb posistion. I don't understand what you are saying about the two patterns above being "shift invarient equivalent". Can you explain that a little more? What result would you like to produce from the above patterns? Brad Smallridge answers: OK. First I made a mistake. As Achim Gratz pointed out. The bit patterns should be: 01100011010 11010011000 so the top pattern should shift 6 times to the left. They would then both be equivalent at 11010011000. And likewise the pattern: 01001100011 should shift left 10 times left and also be equivalent. Should I be using the word rotate instead of shift? So, you see, it's not merely looking for a leading 1. And it seems to be more than looking for the longest run of 1s also. Consider these strings: 01010100101 01001010101 And also I'm not necesarilly looking for an output number that saves the bit pattern of the input. As I stated above, there may be some compression involved, since many patterns will transform to the same output signal. Thanks,Article: 11081
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Ray Andraka wrote > I can't say that I've seen any literature on the art of floorplanning. >Unfortunately really good floorplanning is more of an art than a >science. That should not discourage the neophyte however, as even basic >floorplanning can have dramatic results. The goal is of course to place >the logic in ways that make the routing easier, less congested and >shorter. As a starting point, you might let the tool do the place and >route. After it is finished, read the placed design into the floorplan >tool and start looking for ways you can improve the layout. The first >thing you will probably notice is how awful the automatic placers really >are. Indeed. Steven Schlosser wrote > I'm looking for an introduction to floorplanning for FPGA >designs. Can anyone suggest a good reference? I'm designing for a >Xilinx 4028EX using Synplify and Xilinx M1.4.12 for NT. Thanks! While not a floorplanning cookbook, everyone should read the Xilinx App Note "Improving XC4000 Design Performance" by Camilleri and Lockhard (http://www.xilinx.com/xapp/xapp043.pdf). A few years back I was quite influenced by this concise overview of the issues you must consider to make fast compact Xilinx FPGA designs. FMAPs, pipelining, floorplanning, time specs, are all discussed. It's a little out of date now but still worthwhile. Also, study some of the Xilinx library schematics (ADD16, etc.) -- lots of RLOC'd FMAPs and such. Ah, but Mr. Schlosser is using HDL synthesis. Oh dear. While many folks routinely floorplan using either schematics and/or netlist generators such as PamDC (see http://www.research.digital.com/SRC/pamette/Software.html), is anyone successfully floorplanning with synthesis tools? Is there an HDL to netlist synthesis tool that either -- 1) supports placement constraint attributes on register declarations and/or on subexpressions? (not just pin-locking) or 2) uses systematic, repeatable names for generated elements of the synthesized netlist, enabling external placement constraints? (It is not acceptable if a small change to the HDL source renames all the synthesized stuff, invalidating the external floorplan or guide files.) In lieu of these features, one approach would be to write and verify the entire design in an HDL, then reimplement the significant datapath modules using explicit instantiation and placement via schematics or netlist generator. You get quick design, simulation, synthesis (target other devices), possibility of design reuse, *and* optimal use of FPGA resources so you can use a smaller slower cheaper device. I have been searching for this happy medium myself. As I write on the pleasures of designing processors and systems-on-chip in FPGAs, I want to express the designs 1) in source code, that 2) can be simulated, and which 3) enables compilation to non-Xilinx devices, and 4) enables reuse of preexisting designs from other sources, and 5) uses device features as efficiently as does my netlist generator, e.g. which permits floorplanning. I'd like to use Verilog because of 1-4, anticipating a future Xilinx Student Edition with Verilog -- but I'm not willing to sacrifice my nice, half as large, twice as fast, quick-place-and-route datapaths! Any ideas? Otherwise its going to be either a) 100% netlist generator (sacrificing 3-4) or b) Verilog + datapaths reimiplemented via netlist generator. BTW, http://www3.sympatico.ca/jsgray/sld021.htm is an old example of a floorplanned 32-bit RISC processor datapath in half an XC4010. Jan GrayArticle: 11083
GTE news wrote in message <6oo267$2ov$1@news-2.news.gte.net> ... Oops, guess who just reinstalled his news reading software! Jan Gray jsgray at acm dot orgArticle: 11084
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Jan Gray wrote:: > Is there an HDL to netlist synthesis tool that either -- > 1) supports placement constraint attributes on register declarations and/or > on subexpressions? (not just pin-locking) or > 2) uses systematic, repeatable names for generated elements of the > synthesized netlist, enabling external placement constraints? (It is not > acceptable if a small change to the HDL source renames all the synthesized > stuff, invalidating the external floorplan or guide files.) > NOT YET. My local Exemplar rep claims the new spectrum tool will be able to carry placement info. I haven't played with it yet, so I don't know. This is the reason I still use and advocate schematic entry (I've been accused of working in the dark ages and worse because of this...working in the dark maybe, dark ages: I don't think so). The fact is, if you do hierarchical schematics right, you get just as much reuse (even to different architectures) and I think more readability than the HDLs proport to have. My schematic library consists of a lot of 1 and 2 bit objects (including carry chain stuff) that I can quickly stack to make arbitrary width doo-dads using the array command. After you cut through all the marketing BS, the only real advantages (and not insignificant by any means) that HDLs have over schematics are 1) the ability to simulate the design behaviorally while the design is still just a concept, and 2) the ability to browse an archived design without having a copy of the schematic editor used to create the design. everything else is just as easy to accomplish with a good schematic entry habits. Current shortcomings of HDLs are 1) readability suffers (this is the old a picture is worth a thousand words...of course the schematics need to be done in a way that makes visual sense-a 60 page flat schematic doesn't cut it). The software world is recognizing this and going toward all kinds of GUI's and visual this and that. Meanwhile the hardware guys are moving away from pictoral representation in favor of text. Go figure. 2) the HDLs currently provide no easy means to control placement in the design, and 3) a user has to understand the all the little quirks of the particular version of the synthesis tool he is using to gain any sense of control over the design implementation. I'd really like to have the two advantages I cited, but until the shortcomings are addressed, I will prefer schematics because I get better results in less time. That means more money to me (much of my work is on a fixed price basis) > In lieu of these features, one approach would be to write and verify the > entire design in an HDL, then reimplement the significant datapath modules > using explicit instantiation and placement via schematics or netlist > generator. You get quick design, simulation, synthesis (target other > devices), possibility of design reuse, *and* optimal use of FPGA resources > so you can use a smaller slower cheaper device. > > I have been searching for this happy medium myself. As I write on the > pleasures of designing processors and systems-on-chip in FPGAs, I want to > express the designs > 1) in source code, that > 2) can be simulated, and which > 3) enables compilation to non-Xilinx devices, and > 4) enables reuse of preexisting designs from other sources, and > 5) uses device features as efficiently as does my netlist generator, e.g. > which permits floorplanning. > > I'd like to use Verilog because of 1-4, anticipating a future Xilinx Student > Edition with Verilog -- but I'm not willing to sacrifice my > nice, half as large, twice as fast, quick-place-and-route datapaths! Any > ideas? Otherwise its going to be either a) 100% netlist generator > (sacrificing 3-4) or b) Verilog + datapaths reimiplemented via netlist > generator. Jan, the available cores are increasing, so it is becoming a little easier to get the performance out of an HDL. Often, a core library vendor will include behavioral models (I think it is a requirement to be a xilinx alliance partner) for VHDL and Verilog, a schematic symbol and a placed netlist. Right now the available library doesn't include enough functions to make it all work, but maybe as the libraries grow? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11086
In article <6onvd5$78o@masters0.InterNex.Net>, > so the top pattern should shift 6 times to the left. > They would then both be equivalent at 11010011000. > And likewise the pattern: > 01001100011 > should shift left 10 times left and also be equivalent. > Should I be using the word rotate instead of shift? > So, you see, it's not merely looking for a leading 1. > And it seems to be more than looking for the longest > run of 1s also. Consider these strings: > 01010100101 > 01001010101 > And also I'm not necesarilly looking for an output number > that saves the bit pattern of the input. As I stated above, > there may be some compression involved, since many > patterns will transform to the same output signal. It seems that *rotate* is in fact a more appropriate term; or equivilantly a *circular* shift -- there's no need to distinguish between left and right shifts in this case. So the problem then is how to determine equivalence of bit strings under rotation. This would make the problem a lot different from floating point normalization; but I am sure that this is still a well studied problem. I can write more if this is in fact what you're after. Jacob Hirbawi. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11087
There are 4 devices that are currently on the market that I am aware of that handle partial reconfiguration: Atmel AT40K series, Atmel AT6K series, Dynachip DL6K series and Xilinx 6200. Motorola's part could too, but they just killed their FPGA line a few weeks ago, and National Semiconductor has a series of parts that do it, but so far they are not selling them to the general public. Of these I have worked with the atmel and xilinx parts. I am not familiar with the Dynachip offering. The Atmel 6K series is a direct descendant of the concurrent logic device designed in the late 80's. This device is capable of very high speed operation, but you really need to work at the design at the gate and floorplan level. The routing on the chip is insufficient for the resources available, so it is not well suited for large random logic designs. It is however ideally suited for bit serial computation; I did several bit serial designs with bit clock rates around 125 Mhz in the -2 parts (1994 time frame). The 6010 has an array of 80x80 cells, each of which is basically a half adder with a flip-flop on the sum output. With 6400 flip-flops on the device, it had the highest register count in an FPGA until just recently. This device lacks carry chains, so bit parallel arithmetic is awkward, but not impossible. The small propagation delays through the cells makes it acceptable for bit parallel stuff too (however, a bit serial design will often be capable of a higher overall word rate for the same algorithm). This device is still my first choice for a totally bit serial design (I don't mind doing the floorplanning in that case). Working efficiently with this device requires a trip up a fairly steep learning curve. The National Semiconductor architecture is virtually the same. The Atmel AT40K series is atmel's new offering which was introduced about a year and a half ago. Again, it is a fine grained device. It's cells consist of a pair of 3 LUTs instead of the gating of the AT6K, so the propagation delays are considerably slower. Like the 6K, each cell has one flip-flop, but the array is quite a bit smaller. Atmel did add alot of bus resource (about 5x), so the device is very routable. The use of LUTs instead of gates for the cell logic makes it easier to use (all three input functions are possible--the 6K cells handled a limit set of 2 input functions and a couple of 3 input ones.) Atmel also added a 32x4 dual port RAM at the corner of every 4x4 tile of cells to give the device some memory capability. This capability is no where near as powerful as the clb memory of the xilinx 4000 series though. There is no carry chain in this device, but connections to nearest neighbors in the columns are optimized for speed to minimize the delay of a carry implemented in the logic. There is also a diagonal cell to cell route which is nice for things like an array multiply. Of the devices capable of partial configuration, this is the best choice for random design. Atmel planned it to be able to take xilinx 4K sockets. While it is electrically and mechanically compatible as far as the i/os go, I think functionally and logistically the Xilinx 4K is a better choice in most cases (if you don't need partial reconfig). The xilinx 6200 is a weird chip. It has a hierarchical architecture that is supposed to make using 'hardware objects' relocatable. It also has a microprocessor interface that allows the microprocessor directly access the configuration RAM, which makes it convenient to reprogram. The programming bit stream format is public, so users can manipulate the device program without having to use the xilinx tools. Another nice feature is that there are no illegal bit streams, so you don't have to worry about what you feed it (this feature makes this device the only one acceptable for evolutionary reconfiguration such as genetic programming). The AT6k will accept a bit stream that internally shorts outputs together and can roast the chip in short order. This chip does not implement arithmetic functions very well, as there is no carry chain, and even half adders cannot be realized in one cell. The future of this chip is also uncertain. The safety features and the open bit stream format make this the most popular choice for partial reconfiguration. There is an evaluation design that was done by virtual computer for xilinx and subsequently given to several other companies. The design is a PCI card with a 6200 and some memory on it. It sells for under $1000 from several sources. If you are going to play in reconfiguration, that board is probably the way to do it. If you are going to buy one, I would buy it from Virtual Computer Corp, as they have made improvements to the design and provide the best support. The 6200 is designed specifically for reconfiguration on the fly, but does not implement general logic very well. You would not want to use this chip if you were not using the reconfiguration features. I will be presenting a half day introduction to reconfigurable computing seminar at Wescon'98 at the Annaheim convention center on September 15. You can get more info by calling JoAnn Lindberg at (800)-877-2668, Ext. 244. Pawel E. Tomaszewicz wrote: > Hello, > I'm looking for information about FPGA devices with partial > reprograming. > I found one DL6000 from Dynachip. > I heard about programme/family chip called "Raphael" from Xilinx. Where > can I find any info about it? > > Regards, > Pawel E. Tomaszewicz > > Warsaw University of Technology phone: +48 22 6607894 > Institute of Telecommunications fax: +48 22 8254950 > Nowowiejska 15/19 email: ptomasze@tele.pw.edu.pl > 00-665 Warsaw, POLAND ICQ# 9364632 -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 11088
Everything Ray says is absolutely correct about this subject (that'll be $5 Ray ;-). HDLs do not give a consistent platform for floorplanning unless you instantiate EVERYTHING you are going to floorplan. Even then, if you fart...er change a line of code, you can change the entire structure of the output from the HDL. Even different revisions of the HDL tools will change the names! I also agree with doing regular structures (registers, busses, counters, muxes...) in schematic, so you CAN floorplan then EASILY (and I believe it is far easier to read than HDL). Overall it takes FAR LESS TIME than doing these things in HDLs. I could care less what you want to do your random logic/state machines in, schemtaic or HDLs, but I STRONGLY advise doing regular structures in schematic. It is not archiac, it is using the correct tool CORRECTLY for the job. More than half my contracts are from supposed HDL experts who, when designing for an FPGA, complain that it only runs at 10MHz, and they can't figure out why. Funny how after I either instantiate everything to allow for 'pseudo' consistent naming conventions, and floorplan it, or change their wizardry HDL (cough cough) into schematics, and floorplan it, the design all of a sudden routes in minutes (as opposed to hours) and runs at over 2x-4x (I've seen as high as 10x) speed as the HDLs. Enough said...yes, floorplanning a 4028 (any Xilinx FPGA for that matter that the design uses regular structures) is very prudent. Another gotcha (well, I guess not enough said) that most HDL designers fail on is to NOT use the internal tri-state busses as muxes for register I/O....YOU WANT TO USE THEM IF YOU CAN. They are free logic (not counted in the parts gate count) AND they are fast, and can have a large number of sources/destinations on the 'bus'. Now, enough said...for now ;-) Austin Franklin darkroom@ix.netcom.com Ray Andraka <no_spam_randraka@ids.net> wrote in article <35AFB4F3.FD40122C@ids.net>... > > > Jan Gray wrote:: > > > Is there an HDL to netlist synthesis tool that either -- > > 1) supports placement constraint attributes on register declarations and/or > > on subexpressions? (not just pin-locking) or > > 2) uses systematic, repeatable names for generated elements of the > > synthesized netlist, enabling external placement constraints? (It is not > > acceptable if a small change to the HDL source renames all the synthesized > > stuff, invalidating the external floorplan or guide files.) > > > > NOT YET. My local Exemplar rep claims the new spectrum tool will be able to > carry placement info. I haven't played with it yet, so I don't know. This is > the reason I still use and advocate schematic entry (I've been accused of > working in the dark ages and worse because of this...working in the dark maybe, > dark ages: I don't think so). The fact is, if you do hierarchical schematics > right, you get just as much reuse (even to different architectures) and I think > more readability than the HDLs proport to have. My schematic library consists > of a lot of 1 and 2 bit objects (including carry chain stuff) that I can quickly > stack to make arbitrary width doo-dads using the array command. > > After you cut through all the marketing BS, the only real advantages (and not > insignificant by any means) that HDLs have over schematics are > 1) the ability to simulate the design behaviorally while the design is still > just a concept, and > 2) the ability to browse an archived design without having a copy of the > schematic editor used to create the design. > everything else is just as easy to accomplish with a good schematic entry > habits. Current shortcomings of HDLs are > 1) readability suffers (this is the old a picture is worth a thousand > words...of course the schematics need to be done in a way that makes visual > sense-a 60 page flat schematic doesn't cut it). The software world is > recognizing this and going toward all kinds of GUI's and visual this and that. > Meanwhile the hardware guys are moving away from pictoral representation in > favor of text. Go figure. > 2) the HDLs currently provide no easy means to control placement in the > design, and > 3) a user has to understand the all the little quirks of the particular > version of the synthesis tool he is using to gain any sense of control over the > design implementation. > > I'd really like to have the two advantages I cited, but until the shortcomings > are addressed, I will prefer schematics because I get better results in less > time. That means more money to me (much of my work is on a fixed price basis) > > > In lieu of these features, one approach would be to write and verify the > > entire design in an HDL, then reimplement the significant datapath modules > > using explicit instantiation and placement via schematics or netlist > > generator. You get quick design, simulation, synthesis (target other > > devices), possibility of design reuse, *and* optimal use of FPGA resources > > so you can use a smaller slower cheaper device. > > > > I have been searching for this happy medium myself. As I write on the > > pleasures of designing processors and systems-on-chip in FPGAs, I want to > > express the designs > > 1) in source code, that > > 2) can be simulated, and which > > 3) enables compilation to non-Xilinx devices, and > > 4) enables reuse of preexisting designs from other sources, and > > 5) uses device features as efficiently as does my netlist generator, e.g. > > which permits floorplanning. > > > > I'd like to use Verilog because of 1-4, anticipating a future Xilinx Student > > Edition with Verilog -- but I'm not willing to sacrifice my > > nice, half as large, twice as fast, quick-place-and-route datapaths! Any > > ideas? Otherwise its going to be either a) 100% netlist generator > > (sacrificing 3-4) or b) Verilog + datapaths reimiplemented via netlist > > generator. > > Jan, the available cores are increasing, so it is becoming a little easier to > get the performance out of an HDL. Often, a core library vendor will include > behavioral models (I think it is a requirement to be a xilinx alliance partner) > for VHDL and Verilog, a schematic symbol and a placed netlist. Right now the > available library doesn't include enough functions to make it all work, but > maybe as the libraries grow? > > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > >Article: 11089
I noticed the amount of personal, corporate and head hunter advertising in this news group has increased dramatically. Personally, I find all this advertising in VERY poor taste. I do not believe it is in this groups charter to make this an advertising group, it IS a discussion group. Though people talking about new products, or web sites is great, advertising you offer some consulting service, or are a head hunter looking for names, I believe, is inappropriate. Any body else tired of all this advertising? Austin Franklin darkroom@ix.netcom.comArticle: 11090
I think I have it now. You want a mapping of the set of all inputs for a given bit size to the set of "shift invariant equivalence" groups. This is not so easy. To do this I suspect that you would need to define an ordering sequence for your "shift invariant equivalent" groups. Then you can map your input to the corresponding group by rotating it until it matches the first member of the group. For example, you could define your ordering to be in sequence of magnatude of the binary value. This would provide you with an algorithm of shifting the bit pattern so that the longest string of zeros is at the left, if there is more than one string of zeros of equal maximal length, then you shift to left justify the longest string of zeros with the shortest string of ones on its right, and so on... This will ultimately map all members of a "shift invariant equivalence" group to a single bit pattern, which is what I think you are asking. Now the trick is to identify an ordering sequence that will allow you specify a simple algorithm which can be implemented in combinatoral logic without a multi clock state machine. Some trick, huh? I don't believe you will find a solution to this problem that will be very easy to implement. I think all solutions will either take a great deal of logic, or will require a lot of clock cycles to produce a result. In the case of the latter, you can pipeline it to produce a result on every clock cycle even though it may take many clocks for a given result to work its way through the pipe (both lots of logic and lots of clocks). Does it sound like I understand your problem now? Brad Smallridge wrote: > > Brad Smallridge wrote: > I need a hardware implementation to find a > unique number for a bit pattern that is shifted. > Below is a four bit example although our > requirements are for something larger: > Input > Transform > 0000 > 0000 > 0001 > 1000 > 0010 > 1000 > 0011 > 1100 > 0100 > 1000 > 0101 > 1010 > 0110 > 1100 > 0111 > 1110 > 1000 > 1000 > 1001 > 1001 > 1010 > 1010 > 1011 > 1011 > 1100 > 1100 > 1101 > 1101 > 1110 > 1110 > 1111 > 1111 > Obvisously, all I did here was to shift the input > pattern until it maximised. > The output of the transform is shift invarient, > ie. 0001 maps to the same number as 0100. This is not correct. Here 1001 maps to 1001 while 1100, 0110 and 0011 all map to 1100. In fact all four bit patterns should map to the same "shift invarient equivalent" group. > We are considering doing this,shifting and testing > for max, however, it takes a lot of clock cycles. > I would rather have a logic gate solution. > A look-up-table approach is too costly for > the input width we have in mind. > The transform can also compress data, > for example, the 4 bit example above has > 16 input vectors and maps to only 10 outputs. > Thanks in Advance, > Brad Smallridge > www.sightech.com When you say this transform can compress data, I don't think you will get much compression. As I see it you will be compressing data from 2**n using n bits to (2**n)/n using n - log2(n) bits for a savings of (log2(n)/n) * 100%. For 32 bit words this is only 5/32 or about 15%. Is that worth the trouble? -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11091
Pawel E. Tomaszewicz wrote: > > Hello, > I'm looking for information about FPGA devices with partial > reprograming. > I found one DL6000 from Dynachip. > I heard about programme/family chip called "Raphael" from Xilinx. Where > can I find any info about it? I have not heard about a "Raphael" chip from Xilinx, but there has been an XC6200 series which is partially reprogrammable. But I believe I have heard that it is being discontinued. On the other hand, all of the Atmel FPGA chips are partially reprogrammable. Vist their web site at http://www.atmel.com/ -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11092
Austin Franklin wrote: > > Everything Ray says is absolutely correct about this subject (that'll be $5 > Ray ;-). > > HDLs do not give a consistent platform for floorplanning unless you > instantiate EVERYTHING you are going to floorplan. Even then, if you > fart...er change a line of code, you can change the entire structure of the > output from the HDL. Even different revisions of the HDL tools will change > the names! This is one thing I don't understand about VHDL synthesis. I was told by Orcad support, that your signal names no longer exist once you synthesize the source RTL VHDL into an output. Their attitude is that you should never expect your signal names to ever be preserved. You should expect to reverse engineer the output file to get the synthesized signal names. To me this is ludicrous. That would be like a C compiler tossing all of your variable names and making its own like, aaa001, aaa002...abk345. This is just what the Orcad synthesizer does. Is there some special reason that the source signal names can't be preserved in all cases where the net corresponds to the signal? If this problem were to be fixed, you would have good, known net names to work with. By convention, the object driving the net could be named from the net in some consistant, repeatable manner. This would then provide known object names. Using these object names, constraints could be written to floorplan, set timing and control every aspect of a VHDL design just like a schematic. The problem is not in the VHDL, it is in the names produced by the synthesis engine. I am getting used to VHDL. Maybe to a point where I would prefer (if some of these problems are straightened out) VHDL to schematic. Although a schematic is more visual, I can represent the interconnections of wide registers, busses and other components very concisely in VHDL. I guess I have gotten used to some of the advantages of writing software and would like to be able to design hardware the same way. Even when I draw schematics, I frequently end up drawing sketches of my floorplanning ideas. It would not be so different for me with VHDL. -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 11093
Hi,
I tried gate level simulation after mapping my design to ALTERA device with
MAX+plus II.
As of now I run Verilog-XL as follows.
----- RTL level simulation
$ verilog test_bench.v source_code.v
------ Gate level simulation
$ verilog test_bench.v source_code.vo -v alt_max2.vo
"source_code.vo" can be created by "Verlilog Netlist Writer" in MAX+plus II
Is this OK?
I don't have confidence.
It seem that the simulation result does not contain delay information.
If using sdf file from MAX+plus II, how should I run Verilog-XL?
All I have understood is the following statement is needed in test bench code.
`ifdef SDF
$sdf_annotate("source.sdo",test_bench.source_code);
`endif
But I don't understand which file is needed, what commnad option should be
given Verlog-XL.
Any information would be appreciated.
Bye,
Takanori Fujiki
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Article: 11094The Employment Solution We are currently seeking an Intermediate Hardware Engineer. The ideal candidate will possess the following: · 3-4 years experience in the following: · VHDL · FPGA · Motorola Processors · PCI Bus would be an asset This is a permanent opportunity to develop VHDL work on an FPGA board design on a major project for our client. It involves high speed ASIC processor on board. It is a 50 gig project on a new flagship project. For more information on the above opportunity, contact Stuart Musson at (613) 828-7887. For those who are calling long distance, call toll free at 1-800-818-5469. Resumes can be forwarded for consideration via email at stuartm@tes.net , or through fax to (613) 828-2729. Visit our website http://www.tes.net for more opportunities.Article: 11095
good morning, back in the olden days (ok, the '80s) ANYTHING commercial was quickly shouted down and ppl run out of the newsgroups. i didn't sign on for about, oh, 8 or 9 years and noticed that things have changed, and the internet has gone commercial. while i'm not thrilled about some of the advertising, the volume is relatively low and is clearly identified in the header. so, no significant increase in download times and i just skip over it when i read, hitting 'mark all read' to get rid of them. some of the advertisements, on the other hand, i do find some advertisements quite annoying. this is when the answer to a technical question is 'buy my product' and can't be judged that way from the header - unless i eliminate all posts from certain individuals, clearly not a good plan. these posts does force a waste of time and are annoying. and there are some that are tastefully done, where a technical question is answered, a marvelous answer, with the obvious intent to evoke the reaction, 'damn, i just should hire that guy.' well done and applause for those. just a thought or too, rk p.s. recently plugged my nasa conference (day job), hope this didn't prompt your post! :-) p.s.s. i would like to add that all ppl who post that have a financial interest, i.e., app engineers, distributors, reps, should identify their allegiance in their post. this is generally not a problem but did lead to some nasties a few times. +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Austin Franklin wrote: > I noticed the amount of personal, corporate and head hunter advertising in > this news group has increased dramatically. > > Personally, I find all this advertising in VERY poor taste. I do not > believe it is in this groups charter to make this an advertising group, it > IS a discussion group. > > Though people talking about new products, or web sites is great, > advertising you offer some consulting service, or are a head hunter looking > for names, I believe, is inappropriate. > > Any body else tired of all this advertising? > > Austin Franklin > darkroom@ix.netcom.comArticle: 11096
> p.s. recently plugged my nasa conference (day job), hope this didn't prompt > your post! :-) Nope. Think about it, if every 'so-called' FPGA consultant (everyone claims to be an FPGA consultant these days ;-) posted once a week offering their services, this group would be quite over run by these posts. I have seen a marked increase in these types of posts, and predict it will increase. More and more people are becomming consultants (good and bad) and unless there are rules (news group charter...prohibits advertising), and these rules (charter) are respected, this group might have a 'problem' with all this 'advertising'... Just my opinion... AustinArticle: 11097
Has anyone got Foundation M1.4 DynaText Browser working with Windows NT 4.0 (SP3). I am using NTFS, which may not be a tested configuration. All looks good until I try to open something. For example, Libraries Guide" under "Xilinx Books CD". The CDROM spins for a second, and then I get the message "Cannot open book ...". The same thing happens for all books whether on CD or disk. I have checked (and corrected) the paths in dynatext.ini, and they all make sense. With some very quick system file monitoring I see that DynaText is playing fast and loose with file and directory names. For example, it creates a directory using mixed upper/lower case names, and then accesses it using a different combination of upper and lower case. Not that this shouldn't work, but it is the type of thing that makes me suspect a problem when run under NTFS. It may be worth mentioning that Dynatext worked OK on this system in M1.3. -- George Pontis (Replies to geo at z9 dot com.)Article: 11098
NewTech Computers Corp., a rapidly growing consulting and software company, is URGENTLY looking for at least three (3) hardware designers/engineers with FPGA background (MUST). Additional knowledge of networking, computer telephony, PC Board Level Layout etc. would be a plus. The positions are for our prestigious client, a Fortune 100 corporation in Central New Jersey. The positions are IMMEDIATE and minimum for 6 months. The project may continue beyond 6 months. We offer a competitive compensation package for our employees. Our package includes host of benefits including Health Insurance, Relocation Allowance, Immigration Sponsorship, Workers Compensation, Referral and Performance Bonuses, Computer Training and much more. Independent consultants are welcome to apply. Email your resumes in confidence to "newtech@cybernex.net" For more information contact: Jay Utpat NewTech Computers Corp. 117 Highway 35, Suite 7, Keyport, NJ 07735 Tel: 732-203-0810 Fax: 732-203-0811 Email: newtech@cybernex.net -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member ForumArticle: 11099
NewTech Computers Corp., a rapidly growing consulting and software company, is URGENTLY looking for at least three (3) hardware designers/engineers with FPGA background (MUST). Additional knowledge of networking, computer telephony, PC Board Level Layout etc. would be a plus. The positions are for our prestigious client, a Fortune 100 corporation in Central New Jersey. The positions are IMMEDIATE and minimum for 6 months. The project may continue beyond 6 months. We offer a competitive compensation package for our employees. Our package includes host of benefits including Health Insurance, Relocation Allowance, Immigration Sponsorship, Workers Compensation, Referral and Performance Bonuses, Computer Training and much more. Independent consultants are welcome to apply. Email your resumes in confidence to "newtech@cybernex.net" For more information contact: Jay Utpat NewTech Computers Corp. 117 Highway 35, Suite 7, Keyport, NJ 07735 Tel: 732-203-0810 Fax: 732-203-0811 Email: newtech@cybernex.net -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/rg_mkgrp.xp Create Your Own Free Member Forum
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