Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
FCCM'97 REGISTRATION AND HOTEL INFORMATION
IEEE Symposium on Custom Computing Machines, April 16-18, 1997
Marriott at Napa Valley
3425 Solano Ave., Napa, California 94558
CONFERENCE REGISTRATION
PLEASE TYPE OR PRINT
Name ___________________________________________________________
Company ___________________________________________________________
Address ___________________________________________________________
___________________________________________________________
___________________________________________________________
Email ___________________________________________________________
Phone ____________________________ Fax ________________________
Active IEEE Member Number (Y/N)? ___ Member No: _________________
Registration Fee (see table below): $_____________________________
Credit Card Payers:
Card Holder's Name _____________________________________________
Card Type(MC, Visa) _________________ Exp Date__________________
Card Number _____________________________________________
Signature _____________________________________________
(Credit card payment cannot be made by email--a signature is required)
Student registrants:
I certify that I am a registered student at _______________________
(signed) __________________________________________________________
University address:________________________________________________
The deadline for preregistration is March 25, 1997. Registration
includes a copy of the proceedings, lunch on Wednesday and Thursday,
and dinner on Thursday. The registration fee schedule is as follows:
Preregistration Onsite Registration
IEEE Members 325 375
Non-Members 425 475
Students 150 175
All rates are U.S. dollars. Checks must be drawn on a U.S. bank
and should be made payable to IEEE FCCM Symposium. Checks and
registration forms should be mailed or faxed to:
IEEE FCCM Symposium
c/o Ken Pocek
Intel
Mailstop RN6-18
2200 Mission College Blvd.
Santa Clara, CA 95052 (USA).
Fax: 408-765-5165
HOTEL INFORMATION
Accommodation arrangements should be made directly with the hotel:
Marriott at Napa Valley
3425 Solano
Napa, California 94558
Tel: 707-253-7433 Fax: 707-258-1320
The special FCCM'97 rate is $93/night, single or double occupancy.
Hotel rates are subject to applicable state and local taxes, currently
about $12/night. To guarantee the conference rate, hotel reservation
must be made by March 25, 1997.
For directions to the conference site please see the FCCM web page:
http://www.fccm.org
--
Jeffrey M. Arnold jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace Tel: 619-547-9257
San Diego, CA 92131 Fax: 619-547-9010
USA
Article: 5676
Austin Franklin wrote:
>
> I don't understand what you mean by this. An FPGA that is programmed from
> a serial prom, or even downloaded from a processor, still has a digital bit
> stream, that *is* the entire design. It is so easy to just hook up a logic
> analyzer and 'capture' the bit stream.
I think if you can capture the Xilinx bitstream, it's not very
difficult to convert it to a schematic. At least Xilinx should be
able to do that. But of course, it still doesn't give you much
information on how the whole thing was designed. You lost all
signal names, and modularity.
One thing it could be used for however, is to copy this core in
another design (FPGA or ASIC). This is actually stealing a core
and it would be very difficult to prove that it was stolen. One
would only get suspicious if the detailed features are identical
and the bugs and limitations are the same...
Alain.
--
-----------------------------------------------------------------------
Alain RAYNAUD META SYSTEMS
Batiment Hermes
4, rue Rene Razel
Tel: (33) 01 69 35 10 16 91400 Saclay - FRANCE
E-Mail: Alain_Raynaud@mentorg.com Fax: (33) 01 69 35 10 10
-----------------------------------------------------------------------
Article: 5677
I have a problem with the optimization of a design using Synopsys
and MAXPLUS 7.1 with a FLEX10K30.
entity pld2 is
port(
...
-- RAM Data bus
RDATA :inout STD_LOGIC_VECTOR(7 DOWNTO 0);
...
);
end pld2;
Of course other ports are defined as well.
architecture looks like:
...
RDATA <= "ZZZZZZZZ";
...
It should be a temporary tristate for testing purposes and for unused
pins only.
But after compiling in MAXPLUS the following error occours:
Node RDATA missing source.
Is there a solution to let MAXPLUS ignore unused ports and/or
optimized ports?
Thanx for the answer.
Regards,
Gerhard Wiesinger
Article: 5678Andreas Kugel wrote: > > Steve Baldwin wrote: > > > > Have you looked at Application Note 59 - Configuring FLEX 10K devices ? > > > > The datasheet mentions App note 39 - JTAG Boundary Scan testing in > > Altera devices. I haven't seen that one but it sounds close. > > > > Steve. > > > > =================================================================== > > Very funny Scotty. Now beam down my clothes. > > ------------------------------------------------------------------- > > TLA Microsystems Ltd. PO Box 15-680, New Lynn > > Electronic Product Design Auckland, New Zealand > > Microcontroller Specialists Ph. +64 9 820-2221 > > steveb@kcbbs.gen.nz Fax. +64 9 820-1929 > > =================================================================== > AP NOte 39 covers all JTAG functions EXCEPT CONFIGURATION ! > AP note 59 covers all config modes except via JTAG ! > So these don't help at all. > > I have the Altera CDROM and I looked at all docs related > to configuration or JTAG: there are no details about that topic. > > Any more hints ? > Have you tryed contacting Altera on ther email helpline? I think it is sos@altera.com. If you find an answer, please let us know! //Jörgen BåthArticle: 5679
HI, Xilinx 4002 series have internal RAMs inside, but I understand these RAMs are asynchronous. For some reason, we need a 16x8 Synchronous RAM for our course project. We were just wondering if Xilinx 4002 has an internal synchronous RAM. We did create a 16x8 synchronous RAM with VHDL but the area is huge and it doesn't seem that we can fit the RAM and rest of our design into one 4002 (unfortunately they have to be on one 4002). We guess that all the RAMs were synthesized to flip-flops and didn't use the internal RAMs. Is there anyway to work around this? Your help is greatly appreciated. ------------------------------------------------------------------------------ Louis Zhang 4B Electrical Engineering University of WaterlooArticle: 5680
In article <330B1BDE.4BB6@siemens.at>, Alfred Fuchs <alfred.fuchs@siemens.at> wrote: > Naming programmable devices is a mess. > I think the basic reason is, that every marketing manager is urged to > invent a new name in order not to be a "me-too" runner. Why get so upset about the botched attempt to create two or three catchy acronyms that are supposed to do the impossible: to cleary identify any one of a wide variety of architectures ? It's hopeless. There is such a wide variety that we should not even try to read too much into these acronyms. If it has a PAL-like wide-input AND/Or structure and it is larger than a 22V10, it is a CPLD. If it has many cells, each containing a flip-flop, and the cell- and interconnect structure is a 2-dimensional web, it's an FPGA If it's mask-programmed at the factory, it's an ASIC.. These definitions hold pretty well, except for Altera's 8K and 10K, which are called CPLDs by Altera. Don't try to read any meaning into these names, they are just acronyms This industry has other neaningless acronym, just think of RAM vs ROM. It is silly to name a read/write memory by its access mechanism. Who says names should be logical? A name is just a name, it's no substitute for a 50-page data sheet. Peter Alfke, Xilinx ApplicationsArticle: 5681
Is there a way of bringing waveform files saved in .see format (from earlier version of Viewlogic Workview) into Workview Office 7.2 ViewTrace ? (I am trying to simulate a change to a design done some time ago for which all the input waveforms were saved in .see format, so I need to find a way of seeing the waveforms with ViewTrace 7.2). Any advice will be appreciated. Oleg Sheynin. ----------------------------------------------------------- Oleg Sheynin |Fisher & Paykel Development Engineer |Production Machinery Ltd. Oleg. Sheynin@psc.fp.co.nz |PSC Section Phone +64-9-535 0676 |P.O. Box 58-223, Greenmount Fax +64-9-535 0661 |Auckland, New Zealand -----------------------------------------------------------Article: 5682
Nils Koehler wrote:
Hi There
Does anybody know how to implement Altera`s LPM Function LPM_MUX
into a GDF File .
I dont know how to connect the input busses ( vive in my case ).
Thanks Nils Koehler
Assuming a quad 2 to 1 mux to select between A[3..0] and B[3..0] with
result
C[3..0]. Use WIRE primitives to convert A[] to AB[0][], and B[] to
AB[1][].
Now AB[][] can be connected to the M[][] input of the LPM_MUX symbol.
A[3..0] wire AB[0][3..0]
===============| >==============|| | lpm_mux
||
AB[1..0][3..0] |
B[3..0] wire AB[1][3..0] ||============|
m[][]
===============| >==============|| |
I seem to recall having a problem with using WIREs for this purpose - if
the
above gets complaints from the compiler, replace the WIREs with a pair
of
NOTs. They'll get minimized out.
Woody Johnson
Article: 5683I am a reliability engineer at Boeing assisting a redesign trade study. My task is to assess the reliability impact of redesigning a discrete logic state machine with an FPGA. The subject circuit card has a number of duplicate decision logic channels, each channel would be replaced almost entirely with an FPGA. The existing design originated sometime around 1980. Can someone point out a study that evaluates the reliability aspects of an FPGA as opposed to discrete logic?Article: 5684
Hi, I need to make a decoder and demultiplexer with at least 64 outputs each + related logic. I have used Xilinx FPGAs with Mentor and Synopsys but would prefer a device that is more straightforward to program and with inexpensive tools (personal project). I have considered using CPLDs that would be one-time programmable and it seems to be a good idea. Does anyone have some suggestions. I don't have $millions so I would like something that is inexpensive to program, lot's of i/o, and tools that don't require patches and work-arounds. Thanks, Sam FalakiArticle: 5685
Introducing Renoir for VHDL/Verilog Graphical Entry Full information on a brand new HDL graphical entry tool can be found at: http://www.renoir.com/ You can also download an evaluation copy for Windows, SUN and HP platforms.Article: 5686
The smallest Xilinx XC4000-series FPGA with synchronous (edge-triggered) RAM is the XC4003E. The XC4002 (non-E) does not support synchronous RAM but does support asynchronous (level-sensitive WE) RAM. You can get a full data-sheet on the XC4000E at: http://www.xilinx.com/products/fpgaspec.htm#XC4000 From your posting, it sounds as though you may have written an RTL description of a RAM which will indeed result in flip-flops or combinatorial loops. Instead, you can implement RAMs in your HDL code by instantiating 16x1 or 32x1 RAM functions. If you don't already have it, I'd highly recommend downloading the HDL Synthesis for FPGAs Design Guide at: http://www.xilinx.com/appnotes/hdl_dg.pdf It provides various tricks for creating optimal designs using VHDL/Verilog. See page 3-36 for information on implementing memory. -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Louis Zhang <L3ZHANG@ELECOM2.watstar.uwaterloo.ca> wrote in article <L3ZHANG.16.331F16CC@ELECOM2.watstar.uwaterloo.ca>... | HI, | | Xilinx 4002 series have internal RAMs inside, but I understand | these RAMs are asynchronous. For some reason, we need a | 16x8 Synchronous RAM for our course project. We were just | wondering if Xilinx 4002 has an internal synchronous RAM. | | We did create a 16x8 synchronous RAM with VHDL but the area is huge | and it doesn't seem that we can fit the RAM and rest of our design | into one 4002 (unfortunately they have to be on one 4002). We | guess that all the RAMs were synthesized to flip-flops and didn't | use the internal RAMs. Is there anyway to work around this? | | Your help is greatly appreciated. | ---------------------------------------------------------------------------- -- | Louis Zhang | 4B Electrical Engineering | University of Waterloo | |Article: 5687
> TswvXyooj wrote: > > > Has anyone run into this problem. Does anyone have a "set" > > script (or something like that) that will allow me to > > continue using Rising_Edge(clk) and Falling_Edge(clk) > > functions with Synopsys' tools? Thank-you in advance. This has always annoyed me. Other synthesis tools do support RISING_EDGE (exemplar for one) which IMHO is just a whole lot more intuitive than clk'event AND clk='1'... Unfortunately I can't use it because god...I mean... Synopsys doesn't... I think we should put more pressure on synopsys to support this VERY SIMPLE feature of the 1164 standard... -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 http://www.vautomation.com Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 5688
I was going to send you to see XAPP 031 and especially XAPP 042, at http://www.xilinx.com/apps/xapp.htm. The latter shows how to add a mux and some registers to a 16x8 async SRAM to achieve a synchronous-ish SRAM block -- clocked din, addr, and we. Just the thing for your purposes. Unfortunately, those particular XAPP notes are not available there. And neither is XCell #11, 4Q93, which also has the same article on pp. 26-27. So, get yourself a 1994 Xilinx databook and refer to pp. 8-127 - 8-141. If you are stuck, send me your fax number and I'll send you a copy. > Louis Zhang > 4B Electrical Engineering > University of Waterloo Ah, Waterloo. I'll never forget T.R.Viswanathan: "Hysteresis: I used to have an old Volkswagon whose loose steering wheel exhibited hysteresis..." And does R.E.S. still teach the VIP rule in EE427? Jan Gray, B.Math. (CS/EEE), U.Waterloo, 1987. http://www3.sympatico.ca/jsgray (such as it is)Article: 5689
Hi, is there any way to use one of the configuration pins m0, m1, m2 from a xc4000e part as an output pin? The data book says that i have to call out them by special schematic definitions and place the library components MD0, MD1 or MD2. If possible i can do that with SYNOPSYS, XACT or ViewLogic. Thanks, AndreasArticle: 5690
Look at Model Tech or Viewlogic. Henry Thomas <henry@odo.com> wrote in article <01bc28bd$a306e7c0$e3c32299@infinity>... > Can anyone recommend a good timing simulator that I can use with Cypress > Warp 4.1 that will run under Windows NT 4.0? I don't want to get a whole > new tool chain, I just need a compatible timing simulator, and I would > rather get one that someone else has tried, is using, and works with NT > 4.0. > > - h >Article: 5691
A viewlogic story... I have been using Viewlogic since the late 80s. Workview 4.x for DOS, Powerview for Unix and Workview/Plus for Win 3.1, were excellent products, for both schematic entry and simulation, they even had a decent hot line and knowlegeable tech support. All of the above products were compatible,a schematic entered in Powerview could be read and modifiedin Workview and Workview+, and vice versa. There was support for command line and macros. I would say the only problem with Workview+ was the lack of support of windows printers, but it came with a set of drivers for many printers. Workview+ and Powerview shared the same GUI. In 93/94, they came out with the ProSeries, the only reason to purchase these tools is that they were cheaper than Workview+ and they were windows compliant. They were buggy and lacked many features. In 95/96, ViewOffice was announced and delivered, everyone using Workview+ had a choice of either getting an upgrade for Win3.1 and for Win95/NT, with the understanding that the Win3.1 upgrade would be the last one, with no further product enhancements. When ViewOffice was in beta, Viewlogic received dozens if not hundred of bug reports and enhancements requests,, they decided to ignore most of them and just fix the most glaring bugs that prevented the product from working, gone were the command line, macros, the editing shortcuts, and a few other features that made Workview+ an above average CAD tool. At the same time, their tech support competency disappeared. Viewoffice is now an average to a below average CAD tool. As a consultant, I am asked what CAD tool do I recommend, and used to say Viewlogic. In 96, five of my clients have purchased more than 15 seats of Viewoffice, but no more, now its welcome to Viewlogic HELL. One of these clients decided to get Viewsynthesis against my advice, because Viewlogic made hime a deal he could not refuse. So we set on designing three FPGAs and two ASICs with it, after about three months of trying to debug the logic generated by ViewSynthesis, he wised up and purchased Synopsys. In summary: - Viewsynthesis is BAD! - Viewoffice is usable but less user friendly than the older products. - Viewlogic tech support is non-existent. - I will not recommend ViewOffice to any of my clients anymore. IMHO, Viewlogic decided that they had to compete with Orcad and some of the other low end tools at the same time they were trying to compete with Mentor and Cadence, and they missed the boat. They changed the sales channel, by focusing on distributors (Trilogic in Mass.) for small companies and direct sales for large corp. So my question is: Does Mentor Graphics and or Cadence have CAD tools for Win/NT or a Sparc at a competitive price? Tools I use today are: - Viewdraw and Viewsim (until I find a replacement) - Modeltech for VHDL simulation - FPGA Express for FPGA synthesis - DC for ASIC synthesis Alain Arnaud (arnaud@ecla.com) ECLA Inc.Article: 5692
alain arnaud wrote: > > A viewlogic story... > > I have been using Viewlogic since the late 80s. Workview 4.x for DOS, > Powerview for Unix and Workview/Plus for Win 3.1, were excellent > products, for both schematic entry and simulation, they even had > a decent hot line and knowlegeable tech support. All of the above > products were compatible,a schematic entered in Powerview could be > read and modifiedin Workview and Workview+, and vice versa. > There was support for command line and macros. > I would say the only problem with Workview+ was the lack of support of > windows printers, but it came with a set of drivers for many printers. > Workview+ and Powerview shared the same GUI. > > In 93/94, they came out with the ProSeries, the only reason to purchase > these tools is that they were cheaper than Workview+ and they were > windows compliant. They were buggy and lacked many features. > > In 95/96, ViewOffice was announced and delivered, everyone using Workview+ > had a choice of either getting an upgrade for Win3.1 and for Win95/NT, with > the understanding that the Win3.1 upgrade would be the last one, with no > further product enhancements. > > When ViewOffice was in beta, Viewlogic received dozens if not hundred > of bug reports and enhancements requests,, they decided to ignore most > of them and just fix the most glaring bugs that prevented the product > from working, gone were the command line, macros, the editing shortcuts, > and a few other features that made Workview+ an above average CAD tool. > At the same time, their tech support competency disappeared. Viewoffice > is now an average to a below average CAD tool. > > As a consultant, I am asked what CAD tool do I recommend, and used to say > Viewlogic. In 96, five of my clients have purchased more than 15 seats > of Viewoffice, but no more, now its welcome to Viewlogic HELL. > > One of these clients decided to get Viewsynthesis against my advice, because > Viewlogic made hime a deal he could not refuse. So we set on designing > three FPGAs and two ASICs with it, after about three months of trying > to debug the logic generated by ViewSynthesis, he wised up and > purchased Synopsys. > > In summary: > - Viewsynthesis is BAD! > - Viewoffice is usable but less user friendly than the older > products. > - Viewlogic tech support is non-existent. > - I will not recommend ViewOffice to any of my clients anymore. > > IMHO, Viewlogic decided that they had to compete with Orcad and some > of the other low end tools at the same time they were trying to compete > with Mentor and Cadence, and they missed the boat. They changed the sales > channel, by focusing on distributors (Trilogic in Mass.) for small companies > and direct sales for large corp. > > So my question is: > Does Mentor Graphics and or Cadence have CAD tools for Win/NT or > a Sparc at a competitive price? > > Tools I use today are: > - Viewdraw and Viewsim (until I find a replacement) > - Modeltech for VHDL simulation > - FPGA Express for FPGA synthesis > - DC for ASIC synthesis > > Alain Arnaud (arnaud@ecla.com) > ECLA Inc. I agree with every word you said! I too, used to preach to everyone to buy Viewlogic software, because it used to be quite a powerful set of tools for the price. Boy, did that change with Workview Office!!! It's hard to justify a savings in cost of a software product if it results in SEVERE loss of productivity, to which I can personally attest! It's good to hear that I'm not the only person who shares these concerns! -- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tom Barraza . Telephone: (xxx) xxx-xxxx . . Senior Systems Designer . FAX: (xxx) xxx-xxxx . . Quaker Farms Research . E-mail: tbarraza@qfr.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Article: 5693
This is the final result of my inquiry to ALtera:
Subject:
FW: FLEX10K JTAG Programming: how?
Date:
Thu, 06 Mar 97 09:55:00 PST
From:
Geno Valente <GVALENTE@altera.com>
To:
"'akugel@t-online.de'" <akugel@t-online.de>
Andreas,
Currently we do not support 10k configuration via JTAG with an
embedded
processor. You can do it with the Bit or Byte Blaster. Or use one of
the regular configuration modes; they are just as good as JTAG. I
hope
to have support for 10k configuration via JTAG with an embedded
processor
in late summer.
That is why the information is hard to get... it is not supported.
Regards
Geno Valente
--
Andreas Kugel, Karolinenstr. 4
76135 Karlsruhe, Germany
Phone: (49) 721 377865, Fax (49) 721 937 49 12
E-mail: akugel@t-online.de
Article: 5694Samir Marc Falaki wrote: > > Hi, > > I need to make a decoder and demultiplexer with at least 64 outputs > each + related logic. I have used Xilinx FPGAs with Mentor and > Synopsys but would prefer a device that is more straightforward to > program and with inexpensive tools (personal project). I have > considered using CPLDs that would be one-time programmable and it seems > to be a good idea. Does anyone have some suggestions. I don't have > $millions so I would like something that is inexpensive to program, > lot's of i/o, and tools that don't require patches and work-arounds. > > Thanks, > > Sam Falaki I'd suggest the Lattice isp (in-system programmable) parts such as the ispLSI2096 (96 i/o pins). The isp'ness means that the programming is cheap (about $50 buys you an adapter for a parallel port on your PC). You might be able to find someone that will give you a demo copy of Synario from Data I/O good for 30 days to compile the design. -- -------------------------------------------------------------------- Keith D. Brown, PLD Designs Programmable Logic Device design and programming services. kdbrown@island.net (or kdbrown@bix.com) (250) 390-4205 FAX:(250) 390-4215 <*> --------------------------------------------------------------------Article: 5695
Henry Spencer wrote: > > Does this realization mean that Xilinx will be releasing documentation on > the contents of its bit streams? (Fears of reverse engineering being the > standard excuse, in the past, for not doing so.) Probably not. We did release such documenataion for our XC6200 series parts, but I don't believe Xilinx has any plans to document the bitstreams for the mainstream parts. [I had written a lengthy posting espousing my personal philosophy that Xilinx should provide freeware for programming the parts, but one of my more conservative colleagues read it and declared that I would be shot if I posted it. Email me personally if you are interested in my politically incorrect rantings.] Meanwhile, I'll put my upper-middle management hat back on, and echo Brad's question: Why do you want the bitstream format? Do you really need the bitstream itself, or can you settle for inexpensive or free means of controlling the contents of the bitstream? Is the real issue the cost of tools, or do you need quicker ways than guided ppr to munge the bitstream? ==ericArticle: 5696
>I used 4.1 and used a direct connect parallel post script printer (QMS PS >410) with no problems... Your printer anomaly sounds strange.... Maybe the problem was on the Laserjet only. I could now try a PS printer. Hmmm - interesting. Thanks for the tip. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5697
David Lawrence Hoenig wrote: Has anyone had any experience using the PCI interface VHDL code supplied by Cypress with their parts? We are designing a simple PCI target and are leaning toward Cypress because of the low cost of the Warp development software. Any information would be greatly appreciated. Thank you. -- David Hoenig Student, Computer Engineering, University of Michigan ------------------------------------------------------ Unless you are planning on large volumes, I would save the engineering and use the AMCC 5933(?) PCI interface. It works well, and with the ~$500 development system you get pcb layout, which is critical for PCI. Just my opinions, Dan Dixon Computer Engineer TLA, Inc.Article: 5698
Renoir Support wrote: > > Introducing Renoir for VHDL/Verilog Graphical Entry > > Full information on a brand new HDL graphical entry tool can be found > at: > > http://www.renoir.com/ > Hey, I can't see www.renoir.com. Is the site down??? regards, JimArticle: 5699
Andreas Wehr wrote: > > Hi, > > is there any way to use one of the configuration pins m0, m1, m2 > from a xc4000e part as an output pin? > The data book says that i have to call out them by special > schematic definitions and place the library components MD0, MD1 or MD2. > If possible i can do that with SYNOPSYS, XACT or ViewLogic. > > Thanks, > Andreas Only M1 can be used as an output (and it is only an output). M0 and M2 can only be used as inputs. In viewlogic use the MD1 symbol for the pad. You still need to use an obuf too. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randraka
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z