Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
L3ZHANG@ELECOM2.watstar.uwaterloo.ca (Louis Zhang) wrote:
:HI,
:
:Xilinx 4002 series have internal RAMs inside, but I understand
:these RAMs are asynchronous. For some reason, we need a
:16x8 Synchronous RAM for our course project. We were just
:wondering if Xilinx 4002 has an internal synchronous RAM.
:
[snip]
If by "synchronous" you mean edge-triggered, look at the XC4kE series
parts. They offer exactly that: edge-triggered RAM blocks.
-- Dave Brooks <http://www.iinet.net.au/~daveb>
PGP public key via <http://www.iinet.net.au/~daveb/crypto.html>, or servers
"From" line rigged to foil spambots: daveb <at> iinet.net.au
Article: 5701
In message <01bc29b0$14991190$2ef65ecf@drt1>
"Austin Franklin" <#darkroom@ix.netcom.com#> writes:
> I don't understand what you mean by this. An FPGA that is programmed from
> a serial prom, or even downloaded from a processor, still has a digital bit
> stream, that *is* the entire design. It is so easy to just hook up a logic
> analyzer and 'capture' the bit stream.
.
.
.
> Thanks,
> Austin Franklin
> darkroom@ix.netcom.com
Surely what he means is that although you can capture the bitstream
and replicate the design you cannot work back to the original logic
design unless you know how the bitstream actually configures the
FPGA. You can make a 'Chinese copy' of the system but you cannot do
anything else with it because you haven't got the full design. If
you just want to rip something off its no problem, but that is a bit
dangerous if you don't understand what is happening inside the
system, and you cannot make any 'improvements'.
I still agree that pre-programmed parts, especially anti-fuse, are safer.
Geoff Bostock
--
*************************************************************************** FPGA
Design Consultant and Bed and Breakfast in Wiltshire (UK) *
* See http://www.users.zetnet.co.uk/gbostock *
**************************************************************************
--
*************************************************************************** FPGA
Design Consultant and Bed and Breakfast in Wiltshire (UK) *
* See http://www.users.zetnet.co.uk/gbostock *
**************************************************************************
Article: 5702
(DEADLINE for early registration is March 14)
ADVANCE PROGRAM
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Global Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
R. Panwar (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: C. L. Liu (Illinois)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: E. Yoffa (IBM)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. C.-N. Chu, D. F. Wong (UT-Austin)
* Preserving HDL Synthesis Hierarchy for Cell Placement
Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W. W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C.-N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven
Physical Design into the 21st Century}
R. G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
W. W.-M. Dai (UCSC)
E. Hsieh (Avant!)
M. Hunt (Cadence)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W. W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9292
Hotel Reservations: 1-800-362-2779
(Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at 1-800-362-2779, mentioning ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 14. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 14) (After March 14)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5703
(DEADLINE for early registration is March 14)
ADVANCE PROGRAM
1997 International Symposium on Physical Design
Embassy Suites at Napa Valley, Napa, California
April 14--16, 1997
http://www.cs.virginia.edu/~ispd97/
The International Symposium on Physical Design provides a new and high-quality
forum for the exchange of ideas and results in critical areas related to the
physical design of VLSI systems. The Symposium is an outgrowth of the
ACM/SIGDA Physical Design Workshops held during the years 1987-1996. Its scope
includes all aspects of physical design, from interactions with behavior-
and logic-level synthesis, to back-end performance analysis and verification.
This year's inaugural Symposium focuses on the challenges of high-performance
deep-submicron design, as well as the necessary interactions between physical
design and higher-level synthesis tasks. An outstanding slate of technical
papers has been selected for oral and poster presentation. These developments
are complemented by invited presentations that set forth the contexts and
visions for key areas -- process technology, system architecture, circuit
design and design methodology -- with an emphasis on their implications for
relevant R&D in physical design. The Symposium concludes with a panel of
leading experts who each present their unique perspectives as to the critical
R&D needs of the field.
%%==========================================================================%%
%% Monday, April 14 %%
%%==========================================================================%%
0830-0840 Chairs' Welcome
A. B. Kahng and M. Sarrafzadeh
0840-1010 Keynote Address
* Physical Design: Past and Future, T. C. Hu (UCSD), E. S. Kuh (UCB)
1010-1030 Break
1030-1230 Session 1: Placement and Partitioning
Chairs: D. Hill (Synopsys)
J. Frankle (Aristo Technology)
* Faster Minimization of Linear Wirelength for Global Placement,
C. J. Alpert, T. Chan, D. J. Huang, A. B. Kahng, I. Markov, P. Mulet,
K. Yan (UCLA, Cadence and IBM)
* Network Flow Based Multi-Way Partitioning with Area and Pin Constraints,
H. Liu, D. F. Wong (UT-Austin)
* Partitioning-Based Standard-Cell Global Placement with An Exact Objective,
D. J. Huang, A. B. Kahng (UCLA and Cadence)
* VLSI/PCB Placement with Obstacles Based on Sequence Pair,
H. Murata, K. Fujiyoshi, M. Kaneko (JAIST and Tokyo Inst. of Tech.)
1230--1430 Lunch (Speaker)
* The Quarter Micron Challenge: Integrating Physical and Logic Design
R. Camposano (Synopsys)
1430--1600 Session 2: Synthesis and Layout
Chairs: R. Camposano (Synopsys)
C. Sechen (Washington)
* Timing Driven Placement in Interaction with Netlist Transformations,
G. Stenz, B. R. Riess, B. Rohfleisch, F. M. Johannes (TU-Munich)
* Regular Layout Generation of Logically Optimized Datapaths,
R.X.T. Nijssen, C.A.J. van Eijk (TU-Eindhoven)
* Minimizing Interconnect Energy Through Integrated Low-Power Placement
and Combinational Logic Synthesis,
G. Holt, A. Tyagi (Iowa State)
1600--1630 Break
1630--1830 Session 3: Contexts (Invited)
* Design Technology Trends Based on NTRS Evolution,
P. Verhofstadt, C. D'Angelo (SRC)
* Microprocessor Architecture, Circuit, and Physical Design Trends,
R. Panwar (Sun)
1900--2100 Dinner (Speaker)
* Lithography and Dimensional Trends for Future Processes -- Implications
for Physical Design
P. K. Vasudev (Sematech)
%%==========================================================================%%
%% Tuesday, April 15 %%
%%==========================================================================%%
0830--1000 Session 4: Routing
Chairs: C. L. Liu (Illinois)
D. F. Wong (UT-Austin)
* On Two-Step Routing for FPGAs,
G. G. Lemieux, S. D. Brown, D. Vranesic (Toronto)
* A Simple and Effective Greedy Multilayer Router for MCMs,
Y.-J. Cha (Electronic & Telecomm Research Institute),
C. S. Rim (Sogang U.), K. Nakajima (Maryland)
* Performance Driven Global Routing for Standard Cells,
J. Cong and P. Madden (UCLA)
1000--1030 Break
1030--1200 Session 5: Steiner Tree Constructions
Chairs: M. Marek-Sadowska (UCSB)
N. Sherwani (Intel)
* Min-Cost Flow based Min-Cost Rectilinear Steiner Distance-Preserving
Tree Construction,
J. D. Cho (SungKyunKwan)
* Efficient Heuristics for the Minimum Shortest Path Steiner Arborescence
Problem with Applications to VLSI Physical Design,
J. Cong, A. B. Kahng, K.-S. Leung (UCLA and Cadence)
* Provably Good Routing Tree Construction with Multi-Port Terminals,
C. Bateman, C. S. Helvig, G. Robins, A. Zelikovsky (Virginia)
1200--1330 Lunch
1330--1500 Session 6: Back-End Design Methodology
Chairs: E. Yoffa (IBM)
M. Weisel (Intel)
* A Roadmap of CAD Tool Changes for Sub-Micron Interconnect Problems,
L. Scheffer (Cadence)
* C5M - A Control Logic Layout Synthesis System for High-performance
Microprocessors,
J. Burns, J. Feldman (IBM)
* A VLSI Artwork Legalization Technique Based on a New Criterion of
Minimum Layout Perturbation,
F.-L. Heng, Z. Chen, G. E. Tellez (IBM)
1500--1545 Session 7: Poster Presentations
Chairs: G. Robins (Virginia)
J. D. Cho (SungKyunKwan)
* A Pseudo-Hierarchical Methodology for High Performance
Microprocessor Design,
A. Bertolet, K. Carpenter, K. Carrig, A. Chu, A. Dean, F. Ferraiolo,
S. Kenyon, D. Phan, J. Petrovick, G. Rodgers, D. Willmott (IBM);
T. Bairley, T. Decker, V. Girardi, Y. Lapid, M. Murphy, P. A. Scott,
R. Weiss (Cadence)
* Concurrent Transistor Sizing and Buffer Insertion by Considering
Cost-Delay Tradeoffs,
J. Kim, C. Bamji (Cadence); Y. Jiang, S. Sapatnekar (Iowa State)
* Towards a New Benchmarking Paradigm in EDA,
N. Kapur, D. Ghosh, F. Brglez (NCSU)
* How Good are Slicing Floorplans?,
F. Y. Young, D. F. Wong (UT-Austin)
* Slicibility of Rectangular Graphs and Floorplan Optimization,
P. DasGupta, S. Sur-kolay (Indian Institute of Management)
* Power Optimization for FPGA Look-Up Tables,
M. J. Alexander (Washington State)
* A Matrix Synthesis Approach to Thermal Placement,
C. C.-N. Chu, D. F. Wong (UT-Austin)
* Preserving HDL Synthesis Hierarchy for Cell Placement
Y.-W. Tsay, W.-J. Fang, A. C.-H. Wu and Y.-L. Lin (Tsing Hua)
1545--1715 Session 8: Poster Session
Authors display and discuss one-on-one the posters presented in Poster
Presentation session.
1900--2200 Banquet
%%==========================================================================%%
%% Wednesday, April 16 %%
%%==========================================================================%%
0830--1000 Session 9: Performance Optimization
Chairs: W. W.-M. Dai (UCSC)
L. Jones (Motorola)
* EWA: Exact Wire Sizing Algorithm,
R. Kay, G. Bucheuv, L. Pileggi (CMU)
* Minimization of Chip Size and Power Consumption of High Speed VLSI Buffers,
D. Zhou, X. Y. Liu, X. L. Wang (UNC-Charlotte)
* Closed Form Solution to Simultaneous Buffer Insertion/Sizing and
Wire Sizing,
C. C.-N. Chu, D. F. Wong (UT-Austin)
1000--1030 Break
1030--1230 Session 10: Design Methodology Futures (Invited)
* Chip Hierarchical Design System (CHDS): A Foundation for Timing-Driven
Physical Design into the 21st Century}
R. G. Bushroe (Sematech/HP), S. DasGupta (IBM), R. Steele (Sematech/Intel)
* Physical Design 2010: Back to the Future?
A. R. Newton (UCB)
1230--1430 Lunch (Speaker)
* Physical Design Realities for Digital's StrongARM and Alpha Microprocessors
W. J. Grundmann (DEC)
1430--1700 Session 11: Core Directions (or, Do The Right Thing) (Invited)
* Physical Design Challenges of Performance
D. P. LaPotin (IBM Austin Research Lab)
* Panel: Physical Design R&D: What's Missing?
Moderator: G. Smith (Dataquest)
W. W.-M. Dai (UCSC)
E. Hsieh (Avant!)
M. Hunt (Cadence)
K. Keutzer (Synopsys)
D. P. LaPotin (IBM Austin Research Lab)
N. Sherwani (Intel Hillsboro)
1700 Symposium Closes
%%==========================================================================%%
%% Symposium Organization %%
%%==========================================================================%%
General Chair: A. B. Kahng (UCLA and Cadence)
Past Chair: G. Robins (Virginia)
Steering Committee:
J. P. Cohoon (Virginia),
S. DasGupta (IBM),
S.-M. Kang (Illinois),
B. Preas (Xerox PARC)
Technical Program Chair: M. Sarrafzadeh (Northwestern)
Technical Program Committee:
C.-K. Cheng (UCSD),
W. W.-M. Dai (UCSC),
J. Frankle (Aristo Technology),
D. D. Hill (Synopsys),
J. A. G. Jess (Eindhoven),
L. Jones (Motorola),
Y.-L. Lin (Tsing Hua),
C. L. Liu (Illinois),
M. Marek-Sadowska (UCSB),
C. Sechen (Washington),
K. Takamizawa (NEC),
M. Wiesel (Intel),
D. F. Wong (UT-Austin),
E. Yoffa (IBM)
Publicity Chair: M. J. Alexander (Washington State)
Local Arrangements Chair: J. Lillis (UCB)
Treasurer: S. B. Souvannavong
Sponsors:
ACM Special Interest Group on Design Automation, in cooperation with
IEEE Circuits and Systems Society
Additional Support From:
Avant! Corporation,
Cadence Design Systems, Inc.,
Intel Corporation,
Synopsys Inc., and the
U. S. National Science Foundation.
%%==========================================================================%%
%% Hotel Accommodations and Travel %%
%%==========================================================================%%
ISPD-97 is being held at the Embassy Suites at Napa Valley (formerly the
Inn at Napa Valley) in Napa, California. The hotel is located 55 miles north
of San Francisco, CA in the beautiful Napa Valley. Evans Airport Service
provides daily service between Embassy Suites at Napa Valley and San Francisco
International Airport (SFO) approximately every two hours. On Saturdays and
Sundays, the first departure from SFO is at 8:15am. A one-way fare is $18.00,
and advance reservations are required. Phone 1-707-255-1559 or
FAX 1-707-255-0753. The Embassy Suites at Napa Valley is located at:
1075 California Boulevard
Napa, CA 94559
Phone: 1-707-253-9540
Fax: 1-707-253-9292
Hotel Reservations: 1-800-362-2779
(Central Embassy Suites reservation service.)
A block of rooms is being held for the nights of Sunday through Wednesday
(April 13 through April 16). Room rates are $105 per night for single or
double occupancy. Any individual cancellations within 48 hours from the
date of arrival will be billed for (1) night's stay, plus tax.
+---------------------------------------------------------+
| Please make room reservations directly with the hotel |
| at 1-800-362-2779, mentioning ``GROUP CODE ACM''. |
+---------------------------------------------------------+
The number of rooms available at this rate is limited, and are only being
held through March 14. Early room reservation is highly recommended.
For attendees wishing to stay over Friday and Saturday night, a special rate
of $129 per night, subject to room availablity, has been arranged for
April 11--12 and April 17--19.
%%==========================================================================%%
%% ISPD-97 Advance Registration Form %%
%%==========================================================================%%
Name: _______________________________________________________
Company/University: _________________________________________
Responsibility/Title: _______________________________________
Address: ____________________________________________________
City: _______________________________ State: ________________
Country: ______________________ Postal Code: ________________
Phone: ________________________ Fax: ________________________
Email: ______________________________________________________
Food Choices:
[ ] Vegetarian meals only
[ ] Swordfish or [ ] Filet Mignon (Monday dinner)
Advance Late
(Through March 14) (After March 14)
ACM/IEEE Members [ ] $350 [ ] $425
Non-Members [ ] $425 [ ] $500
Full-Time Students [ ] $175 [ ] $225
Student ID is required if registering as a student.
ACM or IEEE Member No. _____________________________
Registration fee includes meals and Banquet. A limited number of
additional Banquet tickets are available.
_______ Extra Banquet tickets at $50/each.
Payment may be submitted via personal or company check in US funds only and
drawn on a US bank, made payable to ``ACM/1997 International Symposium on
Physical Design''. Payment may also be made with credit card (circle):
Mastercard Visa American Express
Credit Card # _______________________________________________
Expiration Date: ______________ Total Payment: ______________
Name as it appears on credit card: __________________________
Signature: ___________________________ Date: ________________
Please mail or FAX (credit card only) your completed registration form to:
ISPD-97 Symposium Registration
Sally Souvannavong, Treasurer
P.O. Box 395
Pullman, WA 99163-0395
FAX: 1-509-335-3818
Email registration will not be accepted. Cancellations must be in writing
and must be received by March 31, 1997. Questions concerning symposium
registration should be directed to Sally Souvannavong at 1-509-334-3162,
Email: ispd97@eecs.wsu.edu.
%%==========================================================================%%
%% Additional Information %%
%%==========================================================================%%
Check in at Your Convenience:
The symposium registration desk will be open from 4pm to 6pm on Sunday,
April 13th. On Monday, the registration desk will open at 7:30am and
will remain open until 5:00pm.
Experience Springtime in Napa Valley:
Napa Valley weather is very pleasant in April, with an average high temperature
of 78 degrees F and low of 64 degrees F. Attractions include world-famous
wineries offering daily tours, golf and outdoor-recreation facilities, and
easy access to Marine World--Africa USA. Contact the Napa Valley Tourist
Bureau (1-800-523-4353) or Visitors Bureau (1-707-226-7459), or visit the
following websites for additional information:
ISPD-97 Website -- http://www.cs.virginia.edu/~ispd97/
Napa Valley Virtual Visit -- http://www.napavalley.com/cgi-bin/home.o
Conference and Visitors Bureau -- http://www.napavalley.com/nvcvb.html
Driving Directions from East Bay:
Take Hwy 80 to Hwy 37 west, 2 miles to Hwy 29 north, 12 miles to 1st Street
exit to California Boulevard (first left turn off freeway).
Driving Directions from San Francisco:
Take Hwy 101 to Hwy 37 east, 7 miles to Hwy 121 north, then east 15 miles
to Hwy 29 north, 2 miles to 1st Street exit to California Boulevard
(first left turn off freeway).
Article: 5704Hi there all, I am trying to fit a current design into an XC5204-160PQ. I am curious as to how much other designers utilise the I/O capabilities of pins used in the configuration sequence of such devices. The most obvious example is the M[2:0] pins used to set the configuration mode of the device. I can see ways of allowing a fixed set of inputs to these pins during configuration and then other inputs/outputs can be switched in afterwards, but this seems a rather desperate & time consuming option. My second problem is how other configuration pins behave when disabled during bootup. Presumably setting the DOUT pin as an input pin (it doubles as an I/O) will cause problems if the circuitry driving this input isn't disabled during config. so far I have managed to restrict usage of I/O pins to dedicated I/O pins, but I'm not really sure how far I should go in also using the multi-purpose ones. Thanks for any advice. Stu. --------------------------------------------- Stuart Summerville Project Engineer Practel International 442 Torrens Road, Kilkenny, SA 5009 Tel: (61.8) 8268 2196 Fax: (61.8) 8268 2882 Email: stuart.summerville@practel.com.au ---------------------------------------------Article: 5705
Eric Dellinger (ericd@xilinx.com) wrote: : : [I had written a lengthy posting espousing my : personal philosophy that Xilinx should provide : freeware for programming the parts, Do you mean the software just to download the config data into the FPGA's, or you mean the whole development system?Article: 5706
Thanks for your response. I decided to check into things a bit when I saw your name and kept thinking "You know, I've seen that name somewhere before..." and realized it's in half my issues of EE Times!! Thanks again, Wayne In article <01bc29bc$c4117480$61e22399@default>, "Rhondalee Rohleder" <Rhondalee_Rohleder@msn.com> wrote: >Wayne, > Your kind apology accepted. I've been following the programmable logic >market as an analyst for seven years so I just happen to remember a lot of >this stuff! Some of it, admittedly, is market minutae but occasionally it >comes in handy. :-) > >Rhondalee > >Wayne Turner <waynet@goodnet.com> wrote in article ><5fk6bo$cf6$1@news.goodnet.com>... >> After researching further, I found Ms. Rohleder's information given below >> to be entirely correct. My apologies to Ms. Rohleder for doubting her >> accuracy and for any confusion this may have caused. >> >> Wayne >> >> In article <01bc16d5$34c4f760$97e12399@default>, "Rhondalee Rohleder" >> <Rhondalee_Rohleder@msn.com> wrote: >> >Actually, you're *both* right. The devices available in the Intel >> >FLEXlogic line at the time it was sold were EPROM-based. But Intel had >> >planned from the outset to convert the line to FLASH, beginning with the >> >introduction of subsequent devices -- Altera just followed through on >> >Intel's plans after acquiring the line. At the same time, the line was >> >renamed FLASHlogic to avoid confusion with FLEX. >> > >> >Rhondalee Rohleder >> >Pace Technologies (Scottsdale, AZ) >>Article: 5707
Stuart Summerville wrote: > <deleted> > > so far I have managed to restrict usage of I/O pins to dedicated I/O > pins, but I'm not really sure how far I should go in also using the > multi-purpose ones. > You are appropriately cautious. I can only add that you can use the HDC/LDC (high/low during configuration) pins, too, as long as you don't forget that they are active during config - as I did ... once. As outputs, they are probably o.k. unless used unwisely. As inputs, high impedance (or same-polarity) sources only. Obvious, in retrospect. regards, tomArticle: 5708
This is a multi-part message in MIME format.
--------------3C124A502BD1
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Eric Ryherd wrote:
>
> > TswvXyooj wrote:
> >
> > > Has anyone run into this problem. Does anyone have a "set"
> > > script (or something like that) that will allow me to
> > > continue using Rising_Edge(clk) and Falling_Edge(clk)
> > > functions with Synopsys' tools? Thank-you in advance.
>
> This has always annoyed me. Other synthesis tools do support
> RISING_EDGE (exemplar for one) which IMHO is just a whole lot
> more intuitive than clk'event AND clk='1'... Unfortunately I
> can't use it because god...I mean... Synopsys doesn't...
>
> I think we should put more pressure on synopsys to support this
> VERY SIMPLE feature of the 1164 standard...
>
> --
> Eric Ryherd eric@vautomation.com
> VAutomation Inc. Synthesizable VHDL and Verilog Cores
> 20 Trafalgar Sq. #443 http://www.vautomation.com
> Nashua NH 03063 (603) 882-2282 FAX:882-1587
My support !
--------------3C124A502BD1
Content-Type: text/plain; charset=us-ascii; name=".@Signature.World"
Content-Transfer-Encoding: 7bit
Content-Disposition: inline; filename=".@Signature.World"
\\\|/// ir. Jos De Laender
( 0 0 ) Alcatel Telecom - SSD (Switching Systems Division)
oo0-(_)-0oo ASIC design - VH14
_\ ' ` /_
\ \ALCATEL/ / F. Wellesplein 1, B-2018 Antwerp, Belgium
\ TELECOM /
\ \ / / E-mail : mailto:jdla@sh.bel.alcatel.be
\ \ / /
o0 Y 0o Alcatel Bell : http://www.bel.alcatel.be
\|/ Alcatel Telecom : http://www.alcatelecom.be
* Phone : (32)(0) 3 240 74 61
Fax : (32)(0) 3 240 99 47
--------------3C124A502BD1--
Article: 5709Renoir Support renoir@em-wv03.wv.mentorg.com wrote: > Introducing Renoir for VHDL/Verilog Graphical Entry Welcome to the impressionist era of VHDL. Future product plans include: Picasso 1.0 Re-arranges designs sometimes adding extra parts. Warhol '99 Talentless and trite, but strong on marketing.Article: 5710
Henele I Adams wrote: > > I am in a group that is trying to program a XC4003 chip on a demo > board from Xilinx in serial slave mode, without the use of the Xchecker > cable. After looking at the data sheets and using a program that > outputs the data serially from an Intel Hex format in what is apparently > the correct data stream, the done signal still fails to assert. Output > data however, still seems to be in the correct format (preamble, > postamble etc.). Hi, we had a similar problem some time ago with an XC3095 The cause was, that the internal configuration clock was generated from the data stream and that the configuration state machine needed one (or some?) more clock cycle(s) after downloading the data, to get from configuration to start-up mode.. Our solution was to send some more '1' down to the device (a longer postamble).. Good luck Thomas -- ------------------------------------------------------------------- | Thomas Hadlich hadlich@infaut.et.uni-magdeburg.de | | http://infaut.et.uni-magdeburg.de/~hadlich | -------------------------------------------------------------------Article: 5711
Excerpts from netnews.comp.arch.fpga: 10-Mar-97 Re: help:Prog. Xilinx demo .. by Thomas Hadlich@et.uni-ma > we had a similar problem some time ago with an XC3095 > The cause was, that the internal configuration clock was generated from > the > data stream and that the configuration state machine needed one (or > some?) more > clock cycle(s) after downloading the data, to get from configuration to > start-up > mode.. > > Our solution was to send some more '1' down to the device (a longer > postamble).. > you are right. we fixed the problem by sending one more clk signal to the board after done went high. thanks to all who responded, rob migliore srv.ml.orgArticle: 5712
I am considering the usage of a Xilinx FPGA as a DSP chip that also controls memory access to a single SIMM. The FPGA will be the only device accessing the memory. Are there any app notes/example designs on using the Xilinx as memory decoders? Furthermore, I have no knowledge of SIMM operation, so if anyone could fill me in on that I would be very grateful :) -- Christos Dimitrakakis --------------------- mailto:mbge4cd1@fs4.eng.man.ac.uk mailto:mbge4cd1@afs.mcc.ac.uk http://www.man.ac.uk/~mbge4cd1Article: 5713
Hi, any experience with Accolade-Tools (VHDL-Simulation and FPGA-Synthesis) ? Thanks for your comments. Bye, Peter.Article: 5714
Andreas Wehr <wehr@mikro.uni-stuttgart.de> wrote in article <5foune$1vmu@info4.rus.uni-stuttgart.de>... | is there any way to use one of the configuration pins m0, m1, m2 | from a xc4000e part as an output pin? Only the M1 pin can be used as an output, including three-state (M2 and M0 are inputs). You would use the M1 pad symbol connected to either an OBUF or OBUFT symbol. You can do this with VIEWlogic. In the XACT design editor, you would need to use EditBlk to edit the M1 block. In Synopsys, it gets a little more complex. I would recommend that you refer to the "HDL Synthesis for FPGAs Design Guide", beginning on page 3-42. If you don't have this book from Xilinx, you can also download a 2.0 Mb Adobe Acrobat copy from the web at: http://www.xilinx.com/appnotes/hdl_dg.pdf -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic | The data book says that i have to call out them by special | schematic definitions and place the library components MD0, MD1 or MD2. | If possible i can do that with SYNOPSYS, XACT or ViewLogic.Article: 5715
In article <5g176i$694$1@info1.fnal.gov>, Don Husby <husby@fnal.gov> writes >Renoir Support renoir@em-wv03.wv.mentorg.com wrote: >> Introducing Renoir for VHDL/Verilog Graphical Entry > >Welcome to the impressionist era of VHDL. > >Future product plans include: > >Picasso 1.0 Re-arranges designs sometimes adding extra parts. > >Warhol '99 Talentless and trite, but strong on marketing. > > I guess you didn't like it... -- Steve BirdArticle: 5716
Jim, It's a tool developed by Mentor Graphics. Suzanne suzanne@world.std.com Syntest Technologies Jim Mrowca (mrowca@asic.sc.ti.com) wrote: : Renoir Support wrote: : > : > Introducing Renoir for VHDL/Verilog Graphical Entry : > : > Full information on a brand new HDL graphical entry tool can be found : > at: : > : > http://www.renoir.com/ : > : Hey, I can't see www.renoir.com. Is the site down??? : regards, JimArticle: 5717
Christos Dimitrakakis wrote: > > I am considering the usage of a Xilinx FPGA as a DSP chip that also > controls memory access to a single SIMM. The FPGA will be the only > device accessing the memory. > Are there any app notes/example designs on using the Xilinx as memory > decoders? > Furthermore, I have no knowledge of SIMM operation, so if anyone could > fill me in on that I would be very grateful :) > -- > Christos Dimitrakakis > --------------------- > mailto:mbge4cd1@fs4.eng.man.ac.uk > mailto:mbge4cd1@afs.mcc.ac.uk > http://www.man.ac.uk/~mbge4cd1 Going to a single SIMM you won't need a decoder per se. However, if the SIMM is of the ordinary PC variety, it is a Dynamic RAM. This means of course, that the Xilinx design needs to include a DRAM controller. As I recall, there was an app note in the 1994 Xilinx data book on building a deep fifo using DRAM. Perhaps you can use that for some hints. I beleive that design used an LFSR for the address counters and a cute shift scheme to get the row and column addresses. The pinout for standard SIMMs is available on the Hewlett Packard forum in compuserve (at least that is where I got it about a year ago). For timing info, you'll probably have to dig into the data sheets for the DRAMs used on the module. The controller is not atrivial design, but on the other hand a very functional controller can be built in relatively few CLBs. The main things it has to do is mux the row and column addresses, produce the RAS and CAS strobes and generate refresh cycles. Pick one type of access and one type of refresh and you job will be easier. Have fun! -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 FAX 401/884-7950 mailto:randraka@ids.net http://www.ids.net/~randrakaArticle: 5718
Stuart Summerville wrote: > > Hi there all, > > I am trying to fit a current design into an XC5204-160PQ. I am > curious as to how much other designers utilise the I/O capabilities of > pins used in the configuration sequence of such devices. > > The most obvious example is the M[2:0] pins used to set the > configuration mode of the device. I can see ways of allowing a fixed > set of inputs to these pins during configuration and then other > inputs/outputs can be switched in afterwards, but this seems a rather > desperate & time consuming option. > > My second problem is how other configuration pins behave when disabled > during bootup. Presumably setting the DOUT pin as an input pin (it > doubles as an I/O) will cause problems if the circuitry driving this > input isn't disabled during config. > > so far I have managed to restrict usage of I/O pins to dedicated I/O > pins, but I'm not really sure how far I should go in also using the > multi-purpose ones. > The special pins on the Xilinx FPGAs are a real problem to use in a programmable environment. They pins I'm talking about are DIN, DOUT, TDS, TCK, TMS, HDC, LDC, and INIT. We used to just ignore them, but that eliminates 8 pins which can be a substantial penalty. Even worse is the fact that they can sit right in the middle of busses and generally muck up a nice pinout. The basic problem is that when a part is unconfigured, they can act as inputs or outputs. We would like them to be just like the other I/O pins when unconfigured, that is insensitive and tristated. There is a way to use these pins and retain their utility. Place a 'Quickswitch' or 'bus switch' in series with these pins. A quickswitch is a pass transistor. When on, it acts like 5ohm 15 pf RC network, when off it acts like an open switch. The quickswitch enable can be derived from the 'pgm and done' pin. If you are pin limited this can be a pretty cheap fix. These parts are available in a by 10 configuration from Quality Seimconductor for less than $2.00. I still ignore TDO, and M0,M1,M2 - BradArticle: 5719
Samir Marc Falaki wrote: > Hi, I need to make a decoder and demultiplexer with at least 64 outputs each + related logic. I have used Xilinx FPGAs with Mentor and Synopsys but would prefer a device that is more straightforward to program and with inexpensive tools (personal project). I have considered using CPLDs that would be one-time programmable and it seems to be a good idea. Does anyone have some suggestions. I don't have $millions so I would like something that is inexpensive to program, lot's of i/o, and tools that don't require patches and work-arounds. Thanks, Sam Falaki Try Lattice in circuit programmable parts.Article: 5720
Jim Mrowca wrote: Renoir Support wrote: > > Introducing Renoir for VHDL/Verilog Graphical Entry > > Full information on a brand new HDL graphical entry tool can be found > at: > > http://www.renoir.com/ > Hey, I can't see www.renoir.com. Is the site down??? regards, Jim The site is OK. Please check also http://www.mentorg.com/renoir regardsArticle: 5721
On Fri, 7 Mar 1997 15:07:00 GMT, ecla@world.std.com (alain arnaud) wrote: >A viewlogic story... > >I have been using Viewlogic since the late 80s. -snip- >In summary: > - Viewsynthesis is BAD! > - Viewoffice is usable but less user friendly than the older > products. > - Viewlogic tech support is non-existent. > - I will not recommend ViewOffice to any of my clients anymore. > >IMHO, Viewlogic decided that they had to compete with Orcad and some >of the other low end tools at the same time they were trying to compete >with Mentor and Cadence, and they missed the boat. They changed the sales >channel, by focusing on distributors (Trilogic in Mass.) for small companies >and direct sales for large corp. > >So my question is: > Does Mentor Graphics and or Cadence have CAD tools for Win/NT or > a Sparc at a competitive price? > >Tools I use today are: > - Viewdraw and Viewsim (until I find a replacement) > - Modeltech for VHDL simulation > - FPGA Express for FPGA synthesis > - DC for ASIC synthesis > >Alain Arnaud (arnaud@ecla.com) >ECLA Inc. How timely. Just yesterday I received a package from VIEWlogic singing the praises of Workview Office. I guess I should read their hype with a pound of salt. I'm looking to update my NT OS CAD tool set. I was looking at ORCAD but was told by some old school VIEWlogic users that VIEWlogic was superior. Now I'm not so sure. Any suggestions. I need schematic entry for PCB design. I don't need to actually do the PC layout, just produce the schematics, parts list and netlist. -Mike Williams mcw@lightlink.comArticle: 5722
alain arnaud wrote: <snip> > > Tools I use today are: > - Viewdraw and Viewsim (until I find a replacement) > - Modeltech for VHDL simulation > - FPGA Express for FPGA synthesis > - DC for ASIC synthesis > > Alain Arnaud (arnaud@ecla.com) > ECLA Inc. I would recommend looking at Synario's ECS schematic-capture/waveform display tool. it was very solid for us, and had a lot of nice features (VHDL, Verilog, EDIF netlisting, can netlist to PCB layout tools, etc.). We used it with Modeltech and Exemplar, and liked it a lot. We had probably 20-30 copies of ECS. ErikArticle: 5723
Mike Williams wrote: <snip> > I'm looking to update my NT OS CAD tool set. I was looking at ORCAD > but was told by some old school VIEWlogic users that VIEWlogic was > superior. Now I'm not so sure. > > Any suggestions. I need schematic entry for PCB design. I don't need > to actually do the PC layout, just produce the schematics, parts > list and netlist. A long-time user of Capilano Computing's Designworks schematic capture package on the Macintosh, I'd recommend their Win95/NT version. It's not as mainstream as Orcad or Viewlogic, but is powerful and quite easy to use. The package includes a programmable report generator that can create netlists, BOM's etc. in virtually any format. I'm currently running a beta copy of their new version for the Mac (Windows version will follow) and it is very nice. I can now automatically generate solder side test points for surface mount boards. In the past this required post processing of the netlist and hours of manual intervention. Now it's a mouse click (and a little initial investment in symbol attributes, perhaps just a few minutes for a typical PCB). An interactive simulator is included and Xilinx FPGA libraries (currently 2K/3K/4K) are available. Regards, ScottArticle: 5724
Thanks for everyone for your suggestions. You are right about the feature on 4003E and the way that syncRAM shoud be implemented in 4002 (xilinx data book has an article on it). Unfortunately, unlike the discrete RAM and RAM cell in ASIC, the RAM cell in Xilinx 4000 has address and data setup/hold time requirements. We decided to go with Async RAM and got our project done by working around it. :-) Again, thanks everyone for providing helps. ------------------------------------------------------------------------------ Louis Zhang 4B Electrical Engineering University of Waterloo
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z