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----------------------------------------------------------------------------
CHDL '97
ADVANCE PROGRAMME
----------------------------------------------------------------------------
XIII IFIP WG 10.5 Conference on Computer Hardware Description Languages and
Their Applications 1997
Silver Jubilee
Hotel Beatriz - Toledo, Spain - 20-25 April 1997
----------------------------------------------------------------------------
Note: This information about CHDL'97 can be found at
http://www.it.uc3m.es/~ifip/chdl97/ and is mirrored at
http://griao.IRO.UMontreal.CA/ifip/chdl97/
----------------------------------------------------------------------------
Presentations
Session C-1: Specification and Design of Reactive Systems
G. Berry: Synchronous Languages for Hardware and Software
Reactive Systems (Invited Talk)
B. Kleinjohann, J. Tacken, Ch. Tahedl: Towards a Complete Design
Method for Embedded Systems Using Predicate/Transition-Nets
Session C-2: Verification Using Model Checking Techniques (+ Poster
Presentations)
F. Balarin, K. Sajid: Simplifying Data Operations for Formal
Verification
K. Schneider: CTL and Equivalent Sublanguages of CTL*
R. Hojati, D. Dill, R.K. Brayton: Verifying Linear Temporal
Properties of Data Insensitive Controllers Using Finite Instantiations
C.-T. Chou, J.-L. Huang, M. Fujita: A High-Level Language for
Programming Complex Temporal Behaviors and its Translation into
Synchronous Circuits (Poster)
J. Philipps, P. Scholz: System-Level Hardware Design with
mu-Charts (Poster)
M. Auguin, C. Belleudy, G. Gogniat: Interface Synthesis in
Embedded Hardware-Software Systems (Poster)
J.-P. Soininen, J. Saarikettu, V. Veijalainen, T. Huttunen:
TripleS - A Formal Validation Environment for Functional Specifications
(Poster)
R.J. Machado, J.M. Fernandes, A.J. Proenca: SOFHIA: A CAD
Environment to Design Digital Control Systems (Poster)
A. Bardsley, D. Edwards: Compiling the Language Balsa to Delay
Insensitive Hardware (Poster)
C. Mandal, R.M. Zimmer: High-Level Synthesis of Structured Data
Paths (Poster)
Session C-3: Formal Characterizations of Systems
K. Thirunarayan, R. Ewing: Charaterizing a Portable Subset of
Behavioural VHDL-93
B. Berkane, S. Gandrabur, E. Cerny: Algebra of Communicating
Timing Charts for Describing and Verifying Hardware Interfaces
F. Corella, R. Shaw, C. Zhang: A Formal Proof of Absence of
Deadlock for any Acyclic Network of PCI Buses
Session C-4: Analog Languages
V. Moser, H.-P. Amann, F. Pellandini: Behavioural Modelling of
Sampled-Data with HDL-A and ABSynth
Panel: Analog and Mixed-Signal HDLs
Session C-5: Languages in Design Flows
R. Camposano: Hardware Description Languages in Practical
Design Flows (Invited Talk)
J.-M. Daveau, G. Fernandes Marchioro, A.A. Jerraya: VHDL
Generation from SDL Specification
B. Landwehr, P. Marwedel, I. Markhof, R. Doemer: Exploiting
Isomorphism for Speeding Up Binding in an Integrated Scheduling
Allocation and Assignment Approach to Architectural Synthesis (Short
Talk)
Session C-6: Future Trends in Hardware Design (+ Poster Display)
C. Ussery, S. Curry: Design and Verification Flows for Large
Systems in Silicon (Special Talk)
M. Heuchling, W. Ecker, M. Mrva: Applying the Software
V-Process to the Hardware Design
J. Mountjoy, P. Hartel, H. Corporaal: Modular Operational
Semantic Specification of Transport Triggered Architectures
Session C-7: HDLs for the XXI Century
Panel: The Next HDL Paradigms?
Session C-8: Formal Methods for Asynchronous and Distributed Systems
F. Corella: The World of I/O: A Rich Application Area for
Formal Methods (Invited Talk)
H. Barringer, D. Fellows, G. Gough, A. Williams: Abstract
Modelling of Asynchronous Micropipeline Systems using Rainbow
R. Nalumasu, G. Gopalakrishnan: A New Partial Order Reduction
Algorithm for Concurrent System Verification (Short Talk)
----------------------------------------------------------------------------
CHDL'97 Papers in Sessions of the VHDL Users' Forum in Europe
L. Kruse, D. Rabe, W. Nebel: VHDL Power Simulator: Power
Analysis at Gate Level
J. Benzakki, B. Djafri: Object Oriented Extensions to VHDL. The
LaMI Proposal
----------------------------------------------------------------------------
Joint Tutorials
Tutorial 1
J. Bergstra, M. Broy, N. Harman, B. Moeller, A. Ponse: Formal Methods in
Hardware Design
Tutorial 2
J. Bhasker: The IEEE Standard VHDL Synthesis Packages: IEEE Std
1076.3-1996
Tutorial 3
S. Krolikoski, O. Levia, C. Ussery: VHDL Lite - How VHDL Can Be Slimmed
Down
Tutorial 4
L. Jozwiak: Quality-driven Design of Electronic Systems
Tutorial 5
S. Olcoz: VLSI Embedded System Design
Tutorial 6
W. Ecker: Behavioral and System-Level VHDL
Tutorial 7
D. Andreu: Methods of PSPICE Analog, Digital and Mixed Behavioral
Macromodeling of Electronic Devices and Circuits
Tutorial 8
A. Vachoux: VHDL 1076.1 through Examples
----------------------------------------------------------------------------
General Chair
Prof. Dr. Carlos Delgado Kloos
Universidad Carlos III de Madrid
C/Butarque, 15
E-28911 Leganes (Madrid/Spain)
Tel: (+34-1) 624-9979
Fax: (+34-1) 624-9430
E-mail: chdl97@it.uc3m.es
Program Chair
Prof. Dr. Eduard Cerny
Universite de Montreal
C.P. 6128, Succ. Centre-Ville
H3C 3J7 Montreal (Quebec)
Canada
Tel: (+1-514) 343-7472
Fax: (+1-514) 343-5834
E-mail: chdl97@iro.umontreal.ca
Tutorial Chair
Prof. Dr. Przemyslaw Bakowski
IRESTE
University of Nantes
La Chantrerie, CP 3003
F-44087 Nantes cedex 03 (France)
Tel: (+33) 240.68.30.79
Fax: (+33) 240.68.30.66
E-mail: pbakowsk@ireste.fr
Exhibition Chair
Dr. Serafin Olcoz Yanguas
SIDSA
Tel: (+34-1) 8043914
Fax: (+34-1) 8044551
E-mail: sera@www.tgi.es
Local Arrangements
Peter T. Breuer
Salvador Lopez Mendoza
Andres Marin Lopez
Natividad Martinez Madrid
Luis Sanchez Fernandez (UPM)
Aurora Sanchez Garrido
Ingenieria Telematica
Universidad Carlos III de Madrid
C/Butarque, 15
E-28911 Leganes (Madrid/Spain)
Tel: (+34-1) 624-9947
Fax: (+34-1) 624-9430
E-mail: chdl97@it.uc3m.es
Asia-Pacific Representative
Prof. Masaharu Imai
Department of Computer Science
Graduate School of Engineering Science
Osaka University
1-3 Machikane-yama, Toyonaka, Osaka, Japan 560
Tel & Fax: (+81-6) 850-6623
E-mail: imai@ics.es.osaka-u.ac.jp, m.imai@ieee.org
Program Committee
* David Agnew, Canada
* Francois Anceau, France
* Przemyslaw Bakowski, France
* Mario R Barbacci, USA
* Howard Barringer, UK
* Graham Birtwistle, UK
* Dominique Borrione, France
* Raul Camposano, USA
* Eduard Cerny, Canada
* Luc Claesen, Belgium
* Edmund M Clarke, USA
* Francisco Corella, USA
* Werner Damm, Germany
* Carlos Delgado Kloos, Spain
* Nikil D Dutt, USA
* Hans Eveking, Germany
* Norbert Fristacky, Slovakia
* Masahiro Fujita, Japan
* Ganesh Gopalakrishnan, USA
* Werner Grass, Germany
* Reiner Hartenstein, Germany
* Graham Hellestrand, Australia
* Masaharu Imai, Japan
* Steven D Johnson, USA
* Thomas Kropf, Germany
* David C Luckham, USA
* Paul Menchini, USA
* Jean Mermet, France
* Wolfgang Nebel, Germany
* Adam Pawlak, Germany
* Robert Piloty, Germany
* Paolo Prinetto, Italy
* Franz Rammig, Germany
* Peter Schwarz, Germany
* Jorgen Staunstrup, Denmark
* P A Subrahmanyam, USA
* Flavio Wagner, Brazil
* Ronald Waxman, USA
* Akihiko Yamada, Japan
* Michael Yoeli, Israel
----------------------------------------------------------------------------
Toledo
Toledo is without doubt one of the cities with the greatest density of
monuments in the world. Nearly all the different stages of Spanish art
are represented in Toledo, which has Moorish-Mudejar-Jewish buildings,
such as the Transito and Santa Maria la Blanca Synagogues;
Gothic structures, such as the splendid cathedral; and Renaissance
buildings. In the 16th century, the city became home to El Greco, and
Toledo has many of his paintings, among which is "The Burial of the
Count of Orgaz", his masterpiece, which is housed in the Mudejar
Church of Santo Tome. Among its many museums, of special note is
the one located in the old Santa Cruz Hospital.
----------------------------------------------------------------------------
Toledo'97 events comprise CHDL'97, Spring'97 Conference of the VHDL
Users' Forum for CAD in Europe, the Workshop on Libraries, Component
Modelling and Quality Assurance and the Esprit NADA Workshop. There
is only one registration for the combined event and the participants
will receive all the proceedings.
----------------------------------------------------------------------------
=======================================================================
Toledo'97 HOTEL RESERVATION FORM
Hotel Beatriz, Toledo
=======================================================================
A block of rooms has been reserved for Toledo'97 participants.
Please indicate that you attend Toledo'97 when making your
reservation to benefit from the special rates. Please handle your
reservation directly with the hotel *before March 1* to guarantee a
room. 10% of the total amount will be withheld when making the
reservation. Cancellation charge will be 10% of the total.
Hotel Beatriz,
Ctra. de Avila, km. 2,750
E-45005 Toledo, Spain
Tel.: (+34-25) 222211
Fax: (+34-25) 215865
Please book accommodation for:
Last name: ...........................................................
First name: ...........................................................
Affiliation: ...........................................................
Address: ...........................................................
Postal code: ...................... City: ..............................
Country: ...........................................................
Phone: ...................... Fax: ..............................
The rates are: 6.805 Pta (double room + buffet breakfast)
10.015 Pta (double room + buffet breakfast + lunch)
10.540 Pta (single room + buffet breakfast)
13.750 Pta (single room + buffet breakfast + lunch)
(7% VAT included)
Room desired: [ ] Single
[ ] Double (Together with:...............................
..............................................)
[ ] Lunch
Total (in Pta): ..............
Arrival date: ..................... Departure date: .....................
METHODS OF PAYMENT
[ ] Credit card: [ ] MasterCard/Eurocard
[ ] Visa
[ ] Diners
[ ] American Express
Card holder's name ..........................................
Credit card number ..........................................
Expiration date ..........................................
Card holder's signature ..........................................
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Date Signature
[ ] bank transfer to: INPARSA
Account code: 6000023102; Bank code: 2038-5516-95
Bank Name: Caja Madrid
Address: Agen 5, E-45005 Toledo/Spain
*Please indicate participant's name and affiliation in the transfer!*
................... ..........................................
Date Signature
Please send the Hotel Reservation Form to the Hotel and the
Reservation Form to the General Chair
=======================================================================
Toledo'97 REGISTRATION FORM
=======================================================================
Preliminary Conference Structure
Su, 20 April Mo, 21 Tu, 22 We, 23 Th, 24 Fr, 25 Time
April April April April April
Morning C1 C5 V1 C8 V5 L1 V7 L3 L7 N4 9:00-10:30
Tutorials C2 C6 V2 V6 L2 V8 L4 L8 N5 11:00-13:00
Lunch Break
Afternoon C3 N1 N3 V3 Social V9 L5 L9 14:30-16:00
Tutorials C4 N2 C7 V4 Event V10 L6 L10 16:30-18:00
----------------------------------------------------------------------------
C=CHDL97, V=VHDL Users Forum, L=Workshop on Libraries..., N=NADA workshop
----------------------------------------------------------------------------
Please complete and sign this form, and send it by mail or fax to:
Carlos Delgado Kloos
Universidad Carlos III de Madrid
C/Butarque, 15
E-28911 Leganes (Madrid/Spain)
Spain
Tel: (+34-1) 624-9947
Fax: (+34-1) 624-9430
E-mail: chdl97@it.uc3m.es
Please use one form per person and write in block letters.
I will attend the Toledo'97 events.
Last name: .........................................................
First name: .........................................................
Affiliation: .........................................................
Address: .........................................................
Postal code: ...................... City: ............................
Country: .........................................................
Phone: ...................... Fax: ............................
Email: .........................................................
TUTORIALS
If you are going to attend any tutorial, tick which one(s):
Morning Tutorials:
[ ] Tutorial 1: Formal Methods in Hardware Design
[ ] Tutorial 3: VHDL Lite - How VHDL Can Be Slimmed Down
[ ] Tutorial 5: VLSI embedded system design
[ ] Tutorial 7: Methods of PSPICE analog, digital and mixed behavioral
macromodeling of electronic devices and circuits
Afternoon Tutorials:
[ ] Tutorial 2: The IEEE Standard VHDL Synthesis Packages: IEEE Std
1076.3-1996
[ ] Tutorial 4: Quality-driven design of Electronic systems
[ ] Tutorial 6: Behavioral and system-level VHDL
[ ] Tutorial 8: VHDL 1076.1 through examples
Registration Fees (in Pesetas)
------------------------------
on or before after
March 1 March 1
Morning Tutorial: 20.000 20.000 ..........
Afternoon Tutorial: 20.000 20.000 ..........
Conference (Normal) 50.000 55.000 ..........
Conference (Discount) 45.000 50.000 ..........
Student (1): 30.000 35.000 ..........
Social Event (excursion +
banquet) ticket: 10.000 10.000 ..........
Single day 20.000 20.000 ..........
(tick which one(s)) ----------
Mon [ ] Tue [ ] Wed [ ] Thurs [ ] Fri [ ]
TOTAL FEE (in Pesetas): ..........
==========
(1) Please attach proof of student status (will also be requested at
the welcome desk).
* All fees are in Spanish Pesetas (Pta), payable in advance.
* Early registration deadline is *March 1, 1997*.
* Tutorial fee covers: tutorial admission, tutorial notes and
refreshments on April 20, 1997
* Conference fee covers: conference admission, final proceedings
and refreshments on April 21 to 25, 1997, Social Event
on April 23, 1997
* Discount applies to [ ] IFIP, [ ] ATI or [ ] GUVE
members. Membership No:.................
* Student and one day fee don't cover the Social Event.
Methods of payment (all payments in Spanish Pesetas):
I would like to pay the registration fee by
[ ] eurocheque (must accompany registration form) in Pesetas,
payable to Universidad Carlos III de Madrid
[ ] bank transfer to: Univ. Carlos III de Madrid, Ref. 442
Account code: 2110064856; Bank code: 0049-0581-19
Bank Name: Banco Central Hispano;
Address: Juan de la Cierva 38, E-28911 Getafe (Madrid/Spain)
Fees to be charged to the participant; Please indicate
participant's name and affiliation in the transfer!
[ ] cheque (must accompany registration form): in Pesetas, drawn
to a Spanish bank, payable to Universidad Carlos III de
Madrid, fees to be charged to the issuer of the cheque
[ ] credit card: [ ] MasterCard/Eurocard [ ] Visa
Card holder's name ..........................................
Credit card number ..........................................
Expiration date ..........................................
Card holder's signature ..........................................
Cancellation by mail or fax is possible if received by April 1, 1997,
75% of the payment will be refunded. After that date, no refunds will
be made. A substitute participant can be named at any time.
Please specify your dietary requirements for lunch and conference
banquet:
Please specify any other requirements:
................... ..........................................
Date Signature
Please send the Hotel Reservation Form to the Hotel and the
Registration Form to the General Chair.
Article: 5326
In message <5dat53$2ue@ordeal.cts.com>
cwr@cts.com (Will Rose) writes:
> I have a problem with a 16L8 PLD, and I can't find comp...pld,
> so I thought I'd try here - if anyone knows a better source, please
> say so.
> I need to copy a 16L8 to repair some obsolete equipment; I don't
> have a programmer, but can lay my hands on one with some difficulty.
> What I don't know is if it's possible to directly copy a PLD using
> a programmer, or if it's possible to derive the PLD logic and thus
> program another PLD from scratch.
> Any thoughts welcome.
> Will
> cwr@crash.cts.com
Most programmers have a setting 16V8 as 16L8. If the security fuse
is open just read the 16L8 into the programmer - save the JEDEC file
and use this to program a 16V8 as 16L8. If the security fuse is set
and there is no feedback and none of the I/Os is an input you can
throw 1024 test vectors at it and work out the logic. If not, tough...
Geoff Bostock
--
*************************************************************************** FPGA
Design Consultant and Bed and Breakfast in Wiltshire (UK) *
* See http://www.users.zetnet.co.uk/gbostock *
**************************************************************************
Article: 5327
Peter wrote:
If I grab a HCT / 4000 series CMOS databook ( remember those...) they
have a Cpd figure, for all parts
eg HCT595 = 130pF - 8 bit shifter + 8 bit register
HCT161 = 35pF - SYnc 4 bit
HCT4040 = 20pF - Binary Ripple counter
Power(uW) = Cpd.Vcc.Vcc + Sigma (Fo.Cl.Vcc.Vcc)
HEF4094 = 2100.Fi + Sigma (Fo.Cl.Vdd.Vdd) ( -> 84pF )
HEF40161 = 1200.Fi + ....
These translate to close to 8pF Cpd per FlipFlip.
In an FPGA, you would probably split this to Cpd for CLK input + Cpd
for Q out.
Try a 4+4 split, as a first guess, for example.
This does suggest that the sync designs uses in FPGA may not be PD
ideal, and that dividion of a clock
before routing ( with care) would produce lower powers.
Given the numbers being quoted here, there looks to be a need for FPGA
suppliers to state whether
their 10K gate part can actually cope with all cells being clocked at
Fmax, and if not, what the
Pdiss dictated chip usage really is.
- jim granvile.
>
> Power estimation tools have been around for years in the ASIC
> business, but their prices are normally way above even the most
> expensive FPGA design tools.
>
> I cannot see why one could not do a hook into Viewsim (or whatever
> simulator one has) but presumably such a product would undermine the
> marketing of the present solutions.
>
> I too would have found power estimation extremely useful. I have spent
> a lot of time on this myself.
>
> Peter.
>
> Return address is invalid to help stop junk mail.
> E-mail replies to z80@digiserve.com.
Article: 5328Could any one tell me where I could possibly get shareware or a good evaluation version software for FPGA design. I want to learn how to do this type of programming but don't have the hundreds or thousands of dollars to buy a program. Once I learn how to do it then I can apply this technology at work and buy programs to do it but for now I want to learn how to do it. If any one has info on this please email me at tbrisebois@fpmx.com Thanks Todd Brisebois Engineering Fitel-PhotomatrixArticle: 5329
Anybody have or know where I can find some software that can generate a binary JTAG bitstream file from the EZTag produced SVF (or XSVF) files. On our design the JTAG stream is either going to be stored in an onboard EPROM or driven via a very dumb parallel port. There is an apps note on using an 8051 uC but I don't want to go to the expense and trouble of putting another device on board, getting an 8051 C compiler, debugging the code etc. etc. Also can anyone tell me how to o Bypass the XACT-CPLD Design Manager stuff and run the place and route tools in stand alone mode starting with an XNF file. o How to run the eztag program interactively on a PC. Thanks, _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 5330
I think that FPGA dynamic Icc is high because of all the "superfluous" nets which are toggled, rather than due to any property of the silicon process used to make the logic elements. The large (relative to an ASIC, for example) number of toggled nets is the result of two factors: 1. Connections are routed via fixed lines and via muxes, rather than directly; 2. Good FPGA design practice requires the use of a *global* clock net (which goes all over the chip!) and use of clock-enable inputs on D-types to select which one actually gets clocked. So practically the whole chip is bobbing up and down at 4MHz, 50MHz, or whatever. I therefore don't see how one can easily do dynamic Icc estimation based purely on a netlist. To get a figure which is anywhere near in the right area, one would need to take account of *where* everything is routed, and the capacitance of each long line, each mux's I/O, etc. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5331
So I've heard that Altera has a ByteBlaster that is available in
Version 7 of their software and it uses the parallel port to download
the 10K and 8K parts in passive serial mode. I've been using the
81188 and the 10K50 parts but used V6.1 and just moved to V7.1.
I've attached my hack at the same problem. I should have posted earlier
but didn't. If you like the official ByteBlaster at $150 then please
buy one. If you want to build your own, I take no responsibility for
burned up FPGAs (we have never, ever had a problem) and only make
the disclaimer because that is the UseNet way.
Enjoy.
>>>>>>>>>>>> filename="BITBLAST.C"
/* bitblaster - a replacement for the Altera BitBlaster using the printer port */
/* Steve Schossow <ss@tisc.com> 5/8/96 */
/* this version is for a PC running DOS compiled with DJGPP */
#include <stdio.h>
#include <stdlib.h>
#include <pc.h>
static int speed;
/*
* serial routines using the parallel port.
*
* bit 0 of port = data.
* bit 1 of port = clock.
* bit 2 of port = config.
* bit 3 of port = nOE (tri-state control)
*/
#define PAR_PORT 0x378
void short_delay(void) {
int i;
for (i=0;i<(5000/speed);i++);
}
void long_delay(void) {
int i;
for (i=0;i<(50000/speed);i++);
}
void longlong_delay(void) {
int i;
for (i=0;i<(50000/speed);i++);
}
void send_zero(void) {
outportb(PAR_PORT,0x04);
short_delay();
outportb(PAR_PORT,0x06);
short_delay();
}
void send_one(void) {
outportb(PAR_PORT,0x05);
short_delay();
outportb(PAR_PORT,0x07);
short_delay();
}
void send_config(void) {
outportb(PAR_PORT,0x00);
longlong_delay();
outportb(PAR_PORT,0x03);
long_delay();
outportb(PAR_PORT,0x07);
long_delay();
}
void turn_off(void) {
int i;
for (i=0;i<=35;i++) {
send_one();
}
outportb(PAR_PORT,0x0f);
}
void send_dec(int val) {
int i;
#ifdef DEBUG
printf("\nval = %d\n", val);
#endif
for (i=0;i<=7;i++) {
if (val & 0x01) send_one();
else send_zero();
val = val >> 1; /* next bit */
}
}
void send_file(char *filename) {
FILE *fp;
int val, count=0;
if ((fp=fopen(filename,"r"))==NULL) {
printf ("Error: %s can't be opened for reading\n",filename);
return;
}
while (fscanf(fp, "%d,", &val) != EOF) {
send_dec(val);
if ((++count % 1000) == 0) {
printf(".", count);
fflush(stdout);
}
}
printf(" %6.3d\n", count);
}
void main(int argc, char *argv[])
{
if (argc == 1) {
printf("usage: bitblast [-speed] file.ttf (c) 1996 Steve Schossow <ss@tisc.com)\n");
printf(" where 'speed' is an integer describing the speed of your download\n");
printf(" and 'file.ttf' is the Altera download file\n");
printf("\n");
printf("Printer Connector Bit-Blaster\n");
printf(" (25-pin 'D') (10-pin Header)\n");
printf(" |\\ \n");
printf("Pin 2 ---------------| >------ Pin 9 DATA0\n");
printf(" | /O\n");
printf(" 74LS244 Buffer |\n");
printf(" |\\ |\n");
printf("Pin 3 ---------------| >------ Pin 1 DCLK\n");
printf(" | /O\n");
printf(" |\n");
printf(" |\\ |\n");
printf("Pin 4 ---------------| >------ Pin 5 nCONFIG\n");
printf(" | /O\n");
printf(" | --- Pin 4 VCC\n");
printf("Pin 5 ------------------\n");
printf("\n");
printf("Pin 18 ------------------------ Pin 2 GROUND\n");
exit(0);
}
speed = 10000; /* default speed. higher means go faster */
if (*argv[1] == '-') {
sscanf(argv[1], "-%d", &speed);
if (speed < 1) speed = 10;
++argv; --argc;
}
send_config();
while (--argc) {
kbhit();
send_file(*++argv);
}
turn_off();
}
Article: 5332PMFJI, but a brief comment about the response you received from Mike Seither: To say that Lucent (ORCA) is not a major commercial player is not totally accurate. I'm an FPGA market analyst. I estimate that Lucent had $100 million in FPGA merchant market sales in 1996. Lucent is the #3 FPGA supplier, right behind Actel. It's true that -- IN ADDITION to these merchant market sales -- Lucent supplies ORCAs to their own internal operation. But I'd say that $100 million in sales to the general market is probably a "major" vendor. I'm not endorsing either vendor, just like to have the facts straight. Mike is the PR manager at Xilinx. I agree that checking out the Xilinx website would be a good idea -- it has a wealth of info. You can also look at www.lucent.com/micro/fpga and www.altera.com. In applications where you'd consider an antifuse FPGA, see www.actel.com and www.quicklogic.com. Hope this is helpful to you. Rhondalee Rohleder Pace Technologies rhondalee_rohleder@msn.com Ken Krolikoski <kenk@teleport.com> wrote in article <32f96df6.89153336@news.teleport.com>... > On Wed, 05 Feb 1997 18:31:43 GMT, Jason.Wright@ebu.ericsson.com (Jason > T. Wright) wrote: > > >I'm looking at Lucent ORCA2 series & Xilinx 4000E series parts; I also > >looked at Flex10k from Altera. For a previous design I selected a > >F10k50 because the memory requirements fit nicely (number of EABs > >available, distribution of memory, etc.) > > > > > > > >Thanks, > > > >Jason T. Wright > > > > > > > > > Most of Lucents sales comes from captive AT&T accounts. ORCA is not a > major player in the general marketplace. > > Xilinx offers a version of their foundation sw package which offers > vhdl abel or schematic entry. > > The new routing sw that xilinx is releasing now for workstations and > in april for windows NT will significantly improve your route times. > the new 4Kex and 4kxl devices have double the routing resources of the > 4ke. > > the next three parts available from xilinx will be the 4062(now), > 4085(2q97) and 40125(3q97). I found the press release on their web > site. (www.xilinx.com) > > Mike Seither > Xilinx, Inc. > (408) 879-6557 > mike.seither@xilinx.com > >Article: 5333
Hi All, Does anyone have any info on creating a Serial Communication Controller (Zilog/AMD 85C30)? Can this be implemented on a FPGA/CPLD? Thanks GlennArticle: 5334
Gerhard Wiesinger wrote: > > I have troubles using the XILINX Synopsys Interface. > > After doing the "compile -map_effort med" the following error > occours: > > Error: The entity 'inc_dec_ub' depends on the package > 'std_logic_arith' > which has been analyzed more recently. > Please re-analyze the source file for 'inc_dec_ub' and try > again. (LBR-2 > 8) This type of error usually happens when a new version of Synopsys is installed and the designware libraries have not been re-analyzed. I suggest you move the current analyzed designware libs located at $DS401/synopsys/libraries/dw/lib/fpga/xc4000 to a temporary directory (so that you have a way back to where you are now in case something goes wrong) and then re-analyze the libraries for the current version of Synopsys you are using. Details of how to re-analyze the libraries may be found at : http://www.xilinx.com/techdocs/1189.htm -- Brian Philofsky -- ----------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Technical Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -----------------------------------------------------------------------Article: 5335
> On 3 Feb 1997 09:09:40 GMT, pac1@waikato.ac.nz (pac1) wrote: > > >I'm trying to decide if it is worth buying Xilinx Foundation BASE as > >oppose to the standard XACT Step package (because its much cheaper). > > > >Can anyone tell me if it is any good, what are its limitations - I've > >looked on Xilinx home page and can't find a good description of what it > >can or can't do! > > > >Thanks Peter. Peter and Ken, Just in case you didn't know, the Xilinx Foundation tools are OEM'd by Aldec (Henderson, near Las Vegas) http://www.aldec.com. Go to their web site to get more info. I'm an XACTstep user on unix workstations, so I can't comment much on Foundation. I do believe, however, that the METAMOR synth tool (which is OEM'd to Aldec) is also OEM'd to Data IO for use in their Synario system. One drawback with Data IO I've seen is that they typically don't support newer devices as fast as other companies (eg. Synopsys, Mentor). This may not hold true for Aldec because of their tighter relationship with Xilinx. -- Lance Gin "Off the keyboard, over the bridge Delco Systems-GM Hughes Electronics through the gateway, C43LYG@dso.hac.com nothing but NET!"Article: 5336
Peter wrote: > > I think that FPGA dynamic Icc is high because of all the "superfluous" > nets which are toggled, rather than due to any property of the silicon > process used to make the logic elements.... > You hit the nail on the head. This is why the vendors find it so hard to put together a simple power calculator. I know Xilinx has painstakingly measured their devices to characterize the power consumption of various elements in the FPGA, including clock distribution, routing, long-lines, I/Os etc. The results of their research are published in the 1996 databook. Granted, it makes computation of power kind of a pain in the patoot, but at least when you do it, you get an accurate result. Others give simpler formulas that don't seem to take into account all the variables you so aptly identified. While those simpler formulas may be less scary, I, for one am not convinced of their accuracy. I guess its just another case of buyer beware....Now If someone would come up with software that could take that Xilinx data along with switching info for nodes in the design (including clock nets and i/o) and spit out accurate power dissipation numbers. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 5337
Hi, It was very great news that Exemplar released Leonardo for Linux. The benchmark posted here also showed very pleasant results. So I rang the local Exemplar supplier. Now he told me that for a mere AUD37,000 I could have it (basic stuff). I'm not (yet) that rich, I'm afraid. Also, the P&R is not being part of the package, you still have to boot some virus from the Evil Empire before you have a chip in hand. (Well, I can't afford a Sun or HP either.) So, I wonder if any of those family-specific cheap tools would ever be released under Linux ? The Exemplar release should be indicative that there's a potential market. Is it really that hard to port a HP or a Sun version to Linux ? Or, is it shameful to have a Linux version ? I know that probably I won't get a yes/no answer :-) but I wonder if I'm the only one who would prefer Linux over Win to do FPGA and CPLD stuff (in which case I'd better go and buy Win95) ? ZoltanArticle: 5338
>I know that probably I won't get a yes/no answer :-) but I wonder if I'm the >only one who would prefer Linux over Win to do FPGA and CPLD stuff (in which >case I'd better go and buy Win95) ? <begin soapbox> Not in the least. Lesse here, we have a zero-cost operating system with excellent support, near-total system and user interface configurability, and full 32-bit code that, in my three years of using it, has never crashed or hung once. Or, we have an operating system that you have to buy, can't get any effective support for, plenty of 16-bit code for full thunking, "cooperative" "multitasking", near zero system and user interface configurability, editors which make writing things harder rather than easier, frequent crashes, regular hangs, and a habit of putting things in bizzare places in the file system. Which one would *YOU* rather use? <end soapbox> Anyway, when buying software, I make a point of asking for the Linux version. When the company in question says they don't have one, I ask how long until they have one out. When they say they have no plans, I very reluctantly buy the Microsquish version, install it on my Linux box, and run it under dosemu or wine wherever possible. Just my $.02 for encouraging the development of Linux tools. ToddArticle: 5339
Ken, Check http://www.erols.com/aaps They have a complete board kit for the PC ISA bus which comes with the full explanation, schematics and C code which shows you the entire process of down loading .rbt files. The board kit is under #300.00 and it sounds like you could even use it simulate your project Richard Ken Krolikoski wrote: > > On Sat, 18 Jan 1997 19:01:36 -0500, David Charles Hirschfield > <dch+@andrew.cmu.edu> wrote: > > >I'm currently working on a project that requires continuous programming > >and reprogramming of a Xilinx XC4000 FPGA board. > > > >Due to some strange setup requirements, we are not going to be able to > >directly use the xchecker application and cable to program the board. > > > >Does anyone have any information regarding the technical details of > >programming Xilinx boards? > > > >Any help would be greatly appreciated, > >-David Hirschfield > > > >+-===========================================================================-+ > >| --== e-mail ==-- | > >| _/_/_/ _/_/ _/ _/ _/_/_/ dch+@andrew.cmu.edu | > >| _/ _/ _/ _/ _/ _/ _/ or | > >| _/ _/ _/_/_/_/ _/ _/ _/_/ cddch@paleo.giss.nasa.gov | > >| _/ _/ _/ _/ _/_/ _/ | > >| _/_/_/ _/ _/ _/ _/_/_/ --== WWW ==-- | > >| http://www.contrib.andrew.cmu.edu/~dch/ | > >+-===========================================================================-+ > > > try the www.xilinx.com. You can e-mail a question to them from the web > page.Article: 5340
Please check the prices on the full up Foundation software with FPGA ISA board at http://www.erols.com/aaps Ken Krolikoski wrote: > > On 3 Feb 1997 09:09:40 GMT, pac1@waikato.ac.nz (pac1) wrote: > > >I'm trying to decide if it is worth buying Xilinx Foundation BASE as > >oppose to the standard XACT Step package (because its much cheaper). > > > >Can anyone tell me if it is any good, what are its limitations - I've > >looked on Xilinx home page and can't find a good description of what it > >can or can't do! > > > >Thanks Peter. > Peter, > There is also a foundation eval kit available. Call one of the xilinx > distributors, hamilton hallmark, insight or marshall. the limitation > is up to 5000 gates on the base package plus only 3 months support vs > a year for the standard. The base also includes for now an unlimited > site license except for abel. It's a great package for $600.Article: 5341
APS is starting a VHDL examples link and is putting up VHDL examples on the following topics using XILINX FPGAs: Simple counter divider Example PN Sequence Generator Example PN Filter Example POD-ALYZER Logic Analyzer X84 Example Using the X84 Stand Alone w the XCHECKER Cable They are also encouraging students and other users of the board to post their examples, including student Labs done with the board.Article: 5342
This is a great site TONs of listings. Good job Steve! Programmable Logic Jump Station: http://www.netcom.com/~optmagic/index.html Richard Steven K. Knapp wrote: > > This is a repost of a message due to problems reported by Netscape 3.0 news > reader users. > > There is a new site for designers interested in programmable logic. The > Programmable Logic Jump Station provides quick and easy access to > > * all major FPGA, CPLD, and PLD device manufacturers > * most EDA companies that support programmable logic design > * books on programmable logic > * university and industry research groups studying programmable logic and > its applications > * search engines and links to other sources of information on programmable > logic > * design consultants for programmable logic applications > * conferences and trade shows about programmable logic > > Programmable Logic Jump Station: > http://www.netcom.com/~optmagic/index.html > > The Programmable Logic Jump Station was recently named an 'Outstanding > Site' by the PC Webopaedia. > > -- > Steven Knapp > E-mail: optmagic@ix.netcom.com > Programmable Logic Jump Station: http://www.netcom.com/~optmagicArticle: 5343
: Scott McIntosh wrote: : > I'm using a Xilinx 4013E PG223 chip and currently the rest : > of the hardware is to be mounted with wire wrap sockets. Problem : > so far is I'm unable to find an 18x18,223 wire wrap socket. Are : > these just not available? Any other suggestions? Do what everyone else does - buy a handful of the single-inline wire- wrap socket strips, and roll your own. Most of the ZIF sockets will plug into them, making *that* easier, too. I'd recommend soldering down every other pin (minimum) if you're planning on removing the PGA frequently, for obvious reasons. I got a bunch at a local hobby distributor, but they're available from several of the folks that make sockets and headers.Article: 5344
The Verification Technologies area in the IBM Haifa Research Laboratory has a few openings in the Formal Verification and Processor Verification groups. We are involved in the research & development of advanced verification technologies, methodologies and tools, with a high focus on Formal Verification, including: - Symbolic Model Checking - Coverage-Driven Test Program Generation - Specification and Modeling languages - Functional Coverage Analysis Our mission is to develop and apply state-of-art functional formal verification tools to the advantage of IBM processor, ASIC and system design communities. A cornerstone of our work in Formal Verification is the development of an industrial-strength, award-winning Model Checking tool (RuleBase), which is used for H/W design verification across IBM worldwide. RuleBase has also earned considerable attention in the industry and academia. Experts in formal methods (specification languages), formal verification (Model-checking, Theorem-proving), RTL simulation, automatic test generation are encouraged to apply. Fresh college graduates will be also considered. The IBM Haifa Research Laboratory is an exciting organization participating in the development of leading edge products and technologies for IBM. Our environment offers a wide range of activities as well as synergy between our design and verification teams, as well as with worldwide IBM design community. In addition, we encourage staff participation in academic research by attending conferences, driving and mentoring academic research though the Semiconductor Research Corporation (SRC) and other funding channels, and maintaining active working/teaching links with universities. We offer permanent positions as well as visiting (1-2 years) positions in a lively R&D working environment with competitive salaries and benefits. To apply, please send your resume to: Dr. Yaron Wolfsthal (yaron@vnet.ibm.com) Mgr. Formal Verification & Design Automation IBM Haifa Research Laboratory MATAM - Advanced Technology Center Haifa 31905, ISRAEL Fax. +972 4 8296 115Article: 5345
Glenn Carl wrote: > Does anyone have any info on creating a Serial Communication Controller > (Zilog/AMD 85C30)? Can this be implemented on a FPGA/CPLD? I just finished the design entry of a 8274 type function in a Xilinx 4013. This design is now in the test phase. It took approximately 1000 function generators. Datasheets can (currently) be found at: http://www.mds.memec.com/modules.shtml I think that Altera also presented a design at the recent Design Super Con in January.Article: 5346
>function generators. Datasheets can (currently) be found at: > http://www.mds.memec.com/modules.shtml I just went there, but these models are not free. I wonder how much they cost... I remember seeing a UART design in an old Actel app book. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5347
In article <m3u3nnind6.fsf@manocska.bendor.com.au>, Zoltan Kocsi <zoltan@bendor.com.au> writes:
|> Hi,
|>
|> It was very great news that Exemplar released Leonardo for Linux.
|> The benchmark posted here also showed very pleasant results.
|> So I rang the local Exemplar supplier.
|> Now he told me that for a mere AUD37,000 I could have it (basic stuff).
|> I'm not (yet) that rich, I'm afraid.
|> Also, the P&R is not being part of the package, you still have to boot
|> some virus from the Evil Empire before you have a chip in hand.
|> (Well, I can't afford a Sun or HP either.)
|>
|> So, I wonder if any of those family-specific cheap tools would ever be
|> released under Linux ? The Exemplar release should be indicative that there's
|> a potential market. Is it really that hard to port a HP or a Sun version
|> to Linux ? Or, is it shameful to have a Linux version ?
I think that there nearly zero effort to port those programms. I hope that Xilinx
will port their P&R-Tools to Linux, so one can really use the performance of the
cheap 586/686 boards for the time consuming routing. Now I'm using Synopsys on
Sun and transfer the files via floppy to a DOS-PC, because it's much faster than
the old Sun... It would be much more efficent to just 'rlogin' into a Linux PC
and start the routing without wandering around. And Synopsys/Xilinx on WinDOS/NT
has absolutely no use, because you can't do rlogins in these systems...
--
Bye
Georg Acher, acher@informatik.tu-muenchen.de
http://www.informatik.tu-muenchen.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 5348Richard Schwarz wrote: > APS is starting a VHDL examples link and is putting up VHDL examples > on the following topics using XILINX FPGAs: ..... > They are also encouraging students and other users of the board > to post their examples, including student Labs done with the > board. Could you tell us the URL of these postings please?Article: 5349
Actually, you're *both* right. The devices available in the Intel FLEXlogic line at the time it was sold were EPROM-based. But Intel had planned from the outset to convert the line to FLASH, beginning with the introduction of subsequent devices -- Altera just followed through on Intel's plans after acquiring the line. At the same time, the line was renamed FLASHlogic to avoid confusion with FLEX. Rhondalee Rohleder Pace Technologies (Scottsdale, AZ) Dean Brown <deankb@popd.ix.netcom.com> wrote in article <32F2B2A7.568F@popd.ix.netcom.com>... > Wayne Turner wrote: > > > > In article <5cs4oq$cf5@borg.svpal.org>, garyk@svpal.svpal.org (George Noten) wrote: > > >Wayne Turner (waynet@goodnet.com) wrote: > > > 3. Converted? What the hell are you talking about? It was FLASH when Intel > > owned it, it was just called FlexLogic. When Altera bought it they had to > > change the name because they already had the FLEX 8000 family and didn't want > > it to be confused. So they named the part according to what it really was: > > FLASH. Hence the name FlashLogic. > > The Intel part was EPROM based, Altera re-engineered it to Flash, then > dropped it less than a year later. The Flash based EPX880 was a direct > drop in replacement for the IFX780, so customer support shouldn't be > based on the 880 part but on the 780 as well which was available for 4-5 > years. >
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