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I know that you are looking for information outside of the research environment but you might want to look at http://www.netcom.com/~optmagic/research.html for links to various groups investigating reconfigurable computing. Some other commercial links of interest are probably: Metalithic Systems: http://www.metalithic.com/ (they make a musical editing system with multiple FPGAs) Giga Operations: http://www.reconfig.com/giga/rcprodov.htm Virtual Computer Corp.: http://www.vcc.com/ Annapolis Microsystems: http://www.annapmicro.com/wfhtm.html Digital Equipment Corp. (DEC): http://www.research.digital.com/SRC/pamette/ -- Steven Knapp E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Ian <isg100@york.ac.uk> wrote in article <3312FC14.41C6@york.ac.uk>... | Hello FPGA community. | | I'm a researcher at the University of York, UK. I am currently | investigating FPGAs since I am considering their use in a new | project. I need to hear from people who are using these | devices outside of the research environment. | | I am not interested in using FPGAs as | a replacement for random logic circuits, but I am interested in | using them as computing devices (with a particular emphasis | on dynamic/runtime reconfiguration). If you fall into this category, I | would be very gratefull if you could email me. I need to know: | | 1. the broad area of application, | 2. what you judge to be their main advantages/disadvantages. | | Thanks in advance, | | - Ian | _______________________________________________ | Music Technology Group, University of York, UK. | Web: http://www.york.ac.uk/~isg100/ | _______________________________________________ |Article: 5576
a couple of suggestions ...
1. i'm guessing that you're using the "old" placement constraints
that appear in the back of the XACT libraries guide (eg. LOC, RLOC).
i've found that the floorplanner ("fplan") is a better tool for
manual placement and specifying constraints (except i still like
fixing pins with a .CST file). it also has the bonus of allowing
you to view a placed design and can show you a relative routing
density view (bright red indicates highest routing densities).
2. you mentioned "bus bits" so i assume there are some regular
structures (eg. datapaths) in your design. on occassion, i've seen
ppr mess up the bit-ordering along the tristate lines (eg. 2,1,4,3
instead of 1,2,3,4). i use fplan to clean these up. if your design
has a lot of datapath, you may be in for a lot of manual placement
(as suggested by the reply from the highgate consultant). per the
hotline advice you received, you may indeed need to reserve some
row/cols between your bit-slices to get the proper "pitch-matching"
or to make the datapath routable.
3. you might want to contact your local FAE and ask him/her to try
to route your design using the beta version of "PAR" (partition
and route), neocad's replacement for PPR that will be in the
upcoming M1 release. i recently had my FAE route a 4025e for me
using PAR (you must provide the XTF file).
4. does the design have lots of functions that might fit well into some
special architectural features of the target device? for example,
wide decoders, counters, adders? the assumption here is that XABEL
is not "smart enough" to infer these area-efficient primitives
out of your source code. if so, you could schematically capture
these functions, then merge the individual XNF files for the final
design.
5. are there any FF's in the design that can be moved out of the CLB
array and into the IO ring without violating the timing constraints?
hope this helps,
--
Lance Gin "Off the keyboard, over the bridge
Delco Systems-GM Hughes Electronics through the gateway,
C43LYG@dso.hac.com nothing but NET!"
**************************************************************************
Tom Vrankar wrote:
>
> We're designing several larger XC4KE devices under XACT 5.2.1 with XABEL as
> our HDL (long story; absence of timing-driven mapping is annoying, but not
> terminal). Most of the designs are proceeding reasonably. One is giving us
> hell.
>
> We had gotten PPR to produce results that _almost_ met our timing constraints
> several times. After complicating the timing constraints to exclude multicycle
> paths, and a few design adjustments indicated by functional simulation, the
> design now no longer routes.
>
> We have tried to add placement hints in the form of "bounding boxes" (i.e.
> [clb_r1c1 clb_r5c5] kinds of things where the available number of cells in the
> box is about twice what is needed), and more carefully placing bussed items,
> but PPR is producing more and more unroutes with each run.
>
> Both placement and routing efforts are maxed. The design used to complete in
> about 6 hours, but now seems to want to go for days. As part of trying to
> diagnose this problem, we'd been waiting till the ppr.log file indicated
> placement was complete and then issuing a kill -2 to review the placement, but
> have begun to just set route=false.
>
> A symptom seems to be that when the solutions were _almost_ meeting timing,
> the occupied CLBs reported by Floorplanner seemed to be evenly distributed
> across the device (as were the unoccupied CLBs), but now PPR keeps packing the
> CLBs in a tight knot near the center of the device, so it runs out of routing
> channels. It also used to sequence bus bits pretty well, but now scrambles
> them hopelessly (so we now explicitly place key register bits as anchors).
>
> The hotline suggested that we noplace every third row or so to force better
> distribution of CLBs. This sounds like a hack, and we didn't need it before
> (nor on the other designs that use timing constraints). Has anyone else seen
> this kind of behaviour, or have any PPR or constraint tips that might get us
> out of this hole? Can anyone provide a better description of how PPR works,
> what it looks for, what it tries, to give us some insight on how to work
> around it? Any help is appreciated.
Article: 5577In article <01bc22af$39c60070$7c84d9ce@drt1>, "Austin Franklin" <#darkroom@ix.netcom.com#> wrote: >Julian Cox <CoxJA@augustsl.demon.co.uk> wrote in article ><2187cd$b1e36.d9@news.august-systems.co.uk>... >> "Iswada Osumundli" <#io@galofzu.net#> wrote: >> >> >The Lattice parts do not provide enough resources to do a PCI interface, >> >except a simple target. If you want burst target or master >functionality, >> >the Xilinx parts are the only ones that can do it. >> > >> >> IYHBO (In Your Heavily Biassed Opinion) ;-) > >Julian, > >I have done 5 PCI interfaces in FPGAs. I also have some pretty good >qualifications to make the statements I make, they are not unfounded. If >I'm wrong, why not give me some technical data on it, instead of flap. > >The topic was for a PCI interface. There are things that are certain >resources that are required for a PCI interface. I have tried to do a PCI >interface in a CPLD (specifically the Altera 7k and the early Plus Logic >CPLDs, later bought by Xilinx. I have not tried to do it in the Lattice. >If you know that the Lattice can do a PCI interface, enlighten us all, tell >us you've done it, and that the parts do have the resources, like CEs in >the IOBs, both input and output flops, room for the configuration >registers, etc. > >I only speak from my experience of what I have done and learned what is >needed to do a successful PCI interface. Other people may have done it >differently, and their experiences differ, and I like to hear those >experiences. > >If you've got some valuable experience to share, please do, if it's just >flap, keep it to your self. What about in other Altera devices (Flex)? The last EE Times had an article that stated that the Eureka Technology core took 20 percent of an Altera 10K30 (the article started on page 41), ran at 33MHz and offered burst rates of 100 MBits/s. You said that only Xilinx parts can do it. What does Xilinx have that only allows them to do PCI, in your opinion? WayneArticle: 5578
x-no-archive: yes I coded all my previous VHDL designs using Rising_Edge(clk) and Falling_Edge(clk) function in lieu of (clk'event and clk = '1') and (clk'event and clk = '0') respectively. Now, I'm using Synopsys' synthesis tools and I can no longer use the Rising_Edge/Falling_Edge functions. Has anyone run into this problem. Does anyone have a "set" script (or something like that) that will allow me to continue using Rising_Edge(clk) and Falling_Edge(clk) functions with Synopsys' tools? Thank-you in advance. Regards, --TomArticle: 5579
I am looking at options to convert an Actel FPGA into a masked gate array. Unfortunately the conversion houses I have been talking to do not support Mentor backannotated simulation. They do support VITAL which Mentor understands. My question is if you have used VITAL to verify timing on an FPGA to ASIC conversion with Mentor. Thanks -- Steen Larsen, ADC Kentrox #include <disclaimer.std> steenl@kentrox.com Patan llij lliu, ukun kau kau (Caminante no hay camino, se hace camino al andar)Article: 5580
Julian Cox wrote: > > "Austin Franklin" <#darkroom@ix.netcom.com#> wrote: > > >Julian Cox <CoxJA@augustsl.demon.co.uk> wrote in article > ><2187cd$b1e36.d9@news.august-systems.co.uk>... > >> "Iswada Osumundli" <#io@galofzu.net#> wrote: > >> > >> >The Lattice parts do not provide enough resources to do a PCI interface, > >> >except a simple target. If you want burst target or master > >functionality, > >> >the Xilinx parts are the only ones that can do it. > >> > > >> > >> IYHBO (In Your Heavily Biassed Opinion) ;-) > > > >Julian, > > > >I have done 5 PCI interfaces in FPGAs. I also have some pretty good > >qualifications to make the statements I make, they are not unfounded. If > >I'm wrong, why not give me some technical data on it, instead of flap. > > > >The topic was for a PCI interface. There are things that are certain > >resources that are required for a PCI interface. I have tried to do a PCI > >interface in a CPLD (specifically the Altera 7k and the early Plus Logic > >CPLDs, later bought by Xilinx. I have not tried to do it in the Lattice. > >If you know that the Lattice can do a PCI interface, enlighten us all, tell > >us you've done it, and that the parts do have the resources, like CEs in > >the IOBs, both input and output flops, room for the configuration > >registers, etc. > > > >I only speak from my experience of what I have done and learned what is > >needed to do a successful PCI interface. Other people may have done it > >differently, and their experiences differ, and I like to hear those > >experiences. > > > >If you've got some valuable experience to share, please do, if it's just > >flap, keep it to your self. > > > >Austin Franklin > >..darkroom@ix.netcom.com. > > > Austin / Iswada > > I have little doubt that your experience of designing PCI interfaces > is greater than mine. In fact, PCI design is little more than a hobby > for me. FPGA design, however, is not. > > I do try to share my experiences and offer advice when I think it may > be appreciated. I do also try, whenever writing such articles, to > give a balanced and unbiased opinion. > > I have absolutely no grounds on which to state that any particular > manufacturers parts can or cannot accommodate a PCI interface. > > I do know though that Altera recommend Logic Innovations Inc > (www.logici.com) for 32 and 64 bit PCI Verilog and VHDL models for PCI > Bus Masters for use with Altera parts. Similarly, Actel offer CorePCI > macros to do a variety of PCI functions including 33Mhz 0ws 32bit > Master on Actel silicon. (www.actel.com/products/pci/pcifaq.html) > > Are both these manufacturers lying to us? Is the silicon incapable of > performing these functions despite their claims? I doubt it. > > If it is _your experience_ that Xilinx parts are the only ones that > you have successfully used for PCI masters then would it have hurt to > say so in your original post? > > Your statement, 'If you want burst target or master functionality, the > Xilinx parts are the only ones that can do it.' is, I believe, false. > > If I have offended you by suggesting that you have a leaning towards > Xilinx then I unreservedly apologise. > > If 'flap' is defined as making wild, unsubstantiated comments, than I > am indeed guilty. Just as guilty as you Austin. > > All of the above is, of course, IMHO :-) > > Julian You need to be very careful about what you call a PCI interface. You need to meet certain electrical drive requirements and speed requirements, particularly for clocks. Not all vendors are able to meet all the requirements in a design Also, many of the FPGA solutions are very sensitive to the design placement in the device. Some routes may meet the PCI requiremnts others mat not. EdArticle: 5581
Jonathon, I don't know how defaults work in a state machine in AHDL. However, if what you are trying to do is to retarget your state machine to Xilinx devices, the Exemplar Logic products, such as Galileo, can help. In this case, Galileo could read in the compiled netlist from Altera, and output either a XNF netlist, or output technology independent VHDL (which might help you understand a bit more about the state machine). Larry Lapides Exemplar Logic larry@exemplar.comArticle: 5582
TswvXyooj wrote: > > x-no-archive: yes > > I coded all my previous VHDL designs using Rising_Edge(clk) and > Falling_Edge(clk) function in lieu of (clk'event and clk = '1') > and (clk'event and clk = '0') respectively. Now, I'm using Synopsys' > synthesis tools and I can no longer use the > Rising_Edge/Falling_Edge functions. > > --Tom Very nice Tom. It should be done like this in VHDL. But you'd better never forget that Synopsys gives only a very limited VHDL support. Also - but not only - in the 'event on clocks they are very picky. They do not allow a function but they want to see very literally the clk'event and clk='1'. I hate it too, especially because I don't see many reasons for such a restriction, knowing that Synopsys handles functions by _inlining_ them, which must make it really easy to recognize. Kind regards, ir. Jos De Laender Alcatel Telecom Antwerp, BelgiumArticle: 5583
Hello,
I just want to have your opinion on the slew-rate control feature
in the Xilinx XC4000E device.
When you read all the stuff about "slew-rate control" the basic
message you get is that the behaviour of your output pin will
change from .... to ...
_______ _____
| /
| /
______|disabled _____/enabled
for a fixed output situation (that is external R+C combination remains
the same).
However, a colleague of mine warned me about this being "not quite so
the case". He measured the behaviour on the pin with feature enabled
and with feature disabled and the only thing that he could detect
was that the "slew-rate control" feature enabled, only results
in an additional delay (some ns) but that the rate of ascend/descend
of the slope remained exactly the same.
_______ ______
| |
| |
______|disabled __________|enabled
Apparently, this was confirmed by Xilinx Support with the saying
that "this is a frequently encountered misunderstanding".
Now I'm going to verify this feature myself, but I just want to have
your experiences / comments on this feature.
Is it usefull? Is it a hoax? I know that the 1996 Databook, page 4.28,
topic "Output Slew Rate", third paragraph mentions that there is
indeed some capacity added when enabled, but it is not exactly of a
clear statement.
I would be very grateful for YOUR experiences in this field and how
to modify a Xilinx to "smoother" output characteristics without changing
the board situation.
Regards,
David Rademaker, Alcatel Telecom Belgium
email: ?rademakd@sh.bel.alcatel.be? (note "?" = to be deleted)
Article: 5584Understood. I actually meant what you said. I suppose it depends on what one means by "deduce the FPGA design". It is of course obvious that there is no direct way to deduce the original design (i.e. the schematic) from the FPGA. The FPGA does not contain the Viewlogic .wir, .sym etc files! But with a lot of work one could deduce a functionally equivalent netlist. The difficulty of doing this depends on what is inside the FPGA. It might be something quite simple, comprising perhaps 50 D-types. If one had the bitstream info (i.e. the info which Neocad worked out) then it would not take long to work out *that* design. This expertise is not exactly non-existent. I have been reliably advised that there are firms in Hong Kong who specialise in reverse-engineering ASICs into netlists, for relatively modest amounts, typically less than $50k. A RAM-based FPGA would not be vulnerable to this analysis but if one had the bitstream info (which we *know* can be worked out) then the procedure would be similar. >> >Reverse engineering is far more difficult. It is almost impossible to >> >deduce the FPGA design from the bitstream. >> >> Is this not what Neocad must obviously have done? Before Xilinx bought >> them, I mean :) > >No, this is not what NeoCAD did. > >NeoCAD reverse-engineered the semantics of each bit in each data frame >of the bitstream. This allowed us to develop tools to target designs to Xilinx >FPGAs. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 5585
Phil, Try the site for EDA market researcher EDA Today. Url is http://www.edat.com P Nibbs <pnibbs@icd.com.au> wrote in article <33110411.7579@icd.com.au>... > > I would be very greatful if anybody was aware of a site on the WWW where > I could find information on the market share of the major FPGA EDA > vendors - in particular in relation to their synthesis tools. >Article: 5586
In article <3314AD65.14AC@qfr.com>, tbarraza@qfr.com says... > Fellow ASIC designers, Help! > > Our company has recently switched from the UNIX based Powerview > products to the M$ Windoze NT based Workview Office products > for cost reasons, but we were informed that the same capabilities > were built in to the PC products, namely, the same 'look' and > 'feel', as well as the same level of customization via macros > (ViewScript, etc.) > > Well, Viewdraw in Windoze NT and Viewdraw in UNIX are now two > very different programs; although, they used to be the same in > both DOS and UNIX when I last used Workview 4.1 ... > > I have been told that the only customization which can be done > in Workview Office 7.3 (Viewdraw) is via the "Tools" Menu, > which seems to allow the user to add 'DOS' level executable > (batch) files to this menu. > > While I believe that this is a nice feature to have in Viewdraw, > it is by no means anything close to what the Unix version of > Viewdraw allows you to do. I have also been told by Viewlogic > customer support that key bindings are not supported, macros are > not supported, and ViewScript is not supported! I find this hard > to believe, given the fact that Workview 4.x, which runs in DOS, > supports function key mapping and macro execution (and that > product came out more than 5 years ago!); I hope that this > is not the case! > > Has anyone out there been able to make the PC based Workview Office > Viewdraw product 'behave' like the UNIX Viewdraw product? Why did > Viewlogic decide to diverge Viewdraw between UNIX & M$ Windoze? > What are the secrets to really using Viewdraw? The new on-line > docs leave much to be desired compared to the well-documented > Unix version of Viewdraw, and the VCS product by Chronologic > (now, owned by Viewlogic) ... > > I'm sure we're not the only company going through this CAE culture > shock! > > PLEASE ADVISE! Well, OK. Pretty much everything you have been told is true. You get no command line, no user macros, and so on. If you had used Pro Series for Windows you would be equally shocked. For some perverse reason, Viewlogic crippled Workview Office as far as expert level users are concerned. I was heartily bummed when I found out the command line was gone. It appears that the people who wrote/ported the old program new a great deal about CAD software but were horrible Windows programmers. It looks like Workview Office was developed by OK Windows programmers who know nothing about CAD. What I can't understand is why the BETA tester's input was ignored. I know for a fact the everyone was screaming for them to keep the command line and the other features but they chose not to. Only Viewlogic knows why. Oh yeah. Wait till you try ViewSim. You'll love the performance un-enhancement. Good Luck, Jeff Hutchings hutch@Convergent-Design.comArticle: 5587
In article <33140E84.41C67EA6@sh.bel.alcatel.be>, "D. Rademaker VH233 4717" <rademakd@sh.bel.alcatel.be> wrote: > Hello, > > I just want to have your opinion on the slew-rate control feature > in the Xilinx XC4000E device. > > _______ _____ > | / > | / > ______|disabled _____/enabled > What you drew so nicely is exactly what is happening when you enable the slew-rate-limited option in Xilinx devices. Your friend must have used a very slow oscilloscope when he measured the outputs, or he made some other fundamental mistake. The circuitry inside the chip that achieves this has been modified a few times, for we want to make sure that you get the full benefit of reduced slew rate withou unnecessary avoidable extra delay. Obviously the delay is inevitably longer, since it is measured to the 1.5 V crossing. Aat reduced slew rate, this takes longer. Rest assured that we know what we are doing. Slew-rate-limtation-enabled is actually the default condition, since it reduce transmission-line and ground-bounce problems. So we make sure that you as a user have to consciously call for the fast option, and -hopefully- you know how to cope with the associated problems. The difference in slew rate is about 3 to 1. That means, even slew-rate limited outputs are pretty fast. Heavy capacitive loading reduces the difference, since the slew rate is then only determined by the I/V characteristic of the output. I hope everybody understands that the slew-rate option does not affect the output dc sink and source capability ( well, it does in XC4000H, but only there ). Peter Alfke, Xilinx ApplicationsArticle: 5588
Fellow ASIC designers, Help! Our company has recently switched from the UNIX based Powerview products to the M$ Windoze NT based Workview Office products for cost reasons, but we were informed that the same capabilities were built in to the PC products, namely, the same 'look' and 'feel', as well as the same level of customization via macros (ViewScript, etc.) Well, Viewdraw in Windoze NT and Viewdraw in UNIX are now two very different programs; although, they used to be the same in both DOS and UNIX when I last used Workview 4.1 ... I have been told that the only customization which can be done in Workview Office 7.3 (Viewdraw) is via the "Tools" Menu, which seems to allow the user to add 'DOS' level executable (batch) files to this menu. While I believe that this is a nice feature to have in Viewdraw, it is by no means anything close to what the Unix version of Viewdraw allows you to do. I have also been told by Viewlogic customer support that key bindings are not supported, macros are not supported, and ViewScript is not supported! I find this hard to believe, given the fact that Workview 4.x, which runs in DOS, supports function key mapping and macro execution (and that product came out more than 5 years ago!); I hope that this is not the case! Has anyone out there been able to make the PC based Workview Office Viewdraw product 'behave' like the UNIX Viewdraw product? Why did Viewlogic decide to diverge Viewdraw between UNIX & M$ Windoze? What are the secrets to really using Viewdraw? The new on-line docs leave much to be desired compared to the well-documented Unix version of Viewdraw, and the VCS product by Chronologic (now, owned by Viewlogic) ... I'm sure we're not the only company going through this CAE culture shock! PLEASE ADVISE! (Note: The opinions expressed here ARE shared by many in this company!) -- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tom Barraza . Telephone: (xxx) xxx-xxxx . . Senior Systems Designer . FAX: (xxx) xxx-xxxx . . Quaker Farms Research . E-mail: tbarraza@qfr.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Article: 5589
Tom Barraza wrote: > > Fellow ASIC designers, Help! > > Our company has recently switched from the UNIX based Powerview > products to the M$ Windoze NT based Workview Office products > for cost reasons, but we were informed that the same capabilities > were built in to the PC products, namely, the same 'look' and > 'feel', as well as the same level of customization via macros > (ViewScript, etc.) > Yeah we believed the salesman too! Not once, but twice over a period of nine years. > Well, Viewdraw in Windoze NT and Viewdraw in UNIX are now two > very different programs; although, they used to be the same in > both DOS and UNIX when I last used Workview 4.1 ... > Yup. Actually the history (somewhat second hand but I have some evidence of its veracity) is interesting. The first foray into windoze was 4.1 with a Visual Basic front end glued on by an outfit in Delhi India. (Pro-Series). The current product looks about the same. > I have been told that the only customization which can be done > in Workview Office 7.3 (Viewdraw) is via the "Tools" Menu, > which seems to allow the user to add 'DOS' level executable > (batch) files to this menu. Actually, you can run any windoze app. In theory you could launch a windoze app that used OLE to do what you would really have liked VD to do but then it would probably be easier to just manipulate the .SCH files directly. I have gotten so frustrated trying to create symbols that it was easier to pop out and use a text editor! > > While I believe that this is a nice feature to have in Viewdraw, > it is by no means anything close to what the Unix version of > Viewdraw allows you to do. I have also been told by Viewlogic > customer support that key bindings are not supported, macros are > not supported, and ViewScript is not supported! I find this hard > to believe, given the fact that Workview 4.x, which runs in DOS, > supports function key mapping and macro execution (and that > product came out more than 5 years ago!); I hope that this > is not the case! Believe it! > > Has anyone out there been able to make the PC based Workview Office > Viewdraw product 'behave' like the UNIX Viewdraw product? Can't be done. >Why did > Viewlogic decide to diverge Viewdraw between UNIX & M$ Windoze? > What are the secrets to really using Viewdraw? The new on-line > docs leave much to be desired compared to the well-documented > Unix version of Viewdraw, and the VCS product by Chronologic > (now, owned by Viewlogic) ... We just today decided to cut our losses and canned the stuff altogether. > > I'm sure we're not the only company going through this CAE culture > shock! > > PLEASE ADVISE! Sure am glad to know we were not the only ones who were having problems as well. > > (Note: The opinions expressed here ARE shared by many in this company!) > > -- > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > . . . > . Tom Barraza . Telephone: (xxx) xxx-xxxx . > . Senior Systems Designer . FAX: (xxx) xxx-xxxx . > . Quaker Farms Research . E-mail: tbarraza@qfr.com . > . . . > . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Robert H. Owen remove the # to mail --------------------------------------------- Why did ViewLogic rename their products WorkView. Because they finally admitted that one had to Work damn hard to View anything.Article: 5590
Iswada Osumundli wrote: > > The Lattice parts do not provide enough resources to do a PCI interface, > except a simple target. If you want burst target or master functionality, > the Xilinx parts are the only ones that can do it. > > Austin Franklin > ..darkroom@ix.netcom.com.You may also want to consider Lucent ORCA FPGAs. They have both targets and masters implemented in their devices. These designs are available in VHDL or Verilog, so they may save you some design time. Charles Kaseff ckaseff@techdesigns.com Technology Designs, Inc.Article: 5591
In <MPG.d7e9dc5f52665bd989681@news.xmission.com>, hutch@convergent-design.com (Jeffrey L. Hutchings) writes: >In article <3314AD65.14AC@qfr.com>, tbarraza@qfr.com says... >> Fellow ASIC designers, Help! >> >> Our company has recently switched from the UNIX based Powerview >> products to the M$ Windoze NT based Workview Office products >> for cost reasons, but we were informed that the same capabilities >> were built in to the PC products, namely, the same 'look' and >> 'feel', as well as the same level of customization via macros >> (ViewScript, etc.) >> > >Well, OK. Pretty much everything you have been told is true. >You get no command line, no user macros, and so on. If you >had used Pro Series for Windows you would be equally shocked. >For some perverse reason, Viewlogic crippled Workview Office >as far as expert level users are concerned. I was heartily >bummed when I found out the command line was gone. > I used the original PC Powerview under OS/2 with 'far' better results than running under Win 3.1. Tried to bug the local office to shoot for porting the UNIX version to OS/2, even to shipping a copy of OS/2 with the program. I think that the port would have been trivial, and some of the features of OS/2 would provide enhancements that UNIX would not match. I have experience with ViewLogic / WorkView since version 0.8, even before the UNIX port. Ron Springer, independent design consultantArticle: 5592
On 22 Feb 1997 02:17:06 GMT, erikd@zip.com.au (Erik de Castro Lopo) wrote: >Peter Alfke (peter@xilinx.com) wrote: >: Robert, you did not get a meaningful response the first time. I suppose >: that's because the question is too general. FPGAs vary in complexity from >: 1000 gates to astronomical 100 k gates or more, depending on where >: marketing puts the upper limit. I really want to ask it that general. I'm not interested within a particular field but want to get a feeling for the applications and especially for the low-level functions which are implemented using FPGAs. > >I'd agree with what Robert has to say. FPGAs and CPLD are just means of >replacing 74XX series logic and small PALs (ie Lattice 22v10). > ... snipp snapp .... >Hope this helps, >Erik. Yes! Thanks a lot. Robert M. Muench SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany --> Answer to: r.m.muench+ieee.org <-- --> replace the + with @ <-- PGP-Fingerprint: 08 E9 EE 9F 33 ED 46 11 A5 CD BE FC 9D ED 75 14Article: 5593
Hi, I am a user of Synopsys and Mentor Graphics Autologic. I am currently developingsome teaching/labarotory materiel for MSc level work. Does anyone out there know how to instantiate Xilinx elemnts directly into the VHDL code to add elements like the osc4 (XC4000) library. The intention is then to run through Mentor Autologic to synthesize the design.If anyone has an example of how to do this it would be great... Sorry if this seesm like a dumb question, but I have been pulling whats left of my hair out over the last few weeks because of this... ;-( ------------------------------------------------------------------------- Austin Cassidy, Senior Engineer Dept. of Electrical Eng Tel: 44 1232 274275 Queen's University of Belfast Fax: 44 1232 667023 Ashby Building, Stranmillis Road E-mail: A.Cassidy@ee.qub.ac.uk Belfast, BT9 5AH, NORTHERN IRELAND http://www-dsp.ee.qub.ac.uk/oz.html -------------------------------------------------------------------------Article: 5594
If you don't already have it, I would recommend downloading the following Adobe Acrobat document from the Xilinx web site. It has lots of tips and techniques for designing FPGAs using synthesis. It seems to be directed mostly toward Synopsys but the techniques should be fairly universal. It is a big document (about 2.0 Mb). HDL Synthesis for FPGAs Design Guide: http://www.xilinx.com/appnotes/hdl_dg.pdf I could not find a specific reference for the OSC4 oscillator. However, it should be similar for other dedicated functions like boundary scan. Below is a clipping from the section on using the boundary scan function: --- BEGIN --- Instantiating the Boundary Scan Symbol To incorporate the XC4000 boundary scan capability in a configured FPGA using Synopsys tools, you must manually instantiate boundary scan library primitives at the source code level. These primitives include TDI, TMS, TCK, TDO, and BSCAN. The example in Figure 3-20 shows how to instantiate the boundary scan symbol, BSCAN, into your HDL code. In this example, the four TAP pins are declared as ports. The schematic for this design is shown in Figure 3-21. You must assign a Synopsys Don’t Touch attribute to the net connected to the TDO pad before you use the Insert_pads and Compile commands. Otherwise, the TDO pad is removed by the compiler. In addition, you do not need IBUFs or OBUFs for the TDI, TMS, TCK, and TDO pads. These special pads connect directly to the Xilinx boundary scan module. --- END --- There is an example that follows in the text but it seems to have been saved as a graphic rather than text in the Acrobat document. Some of the other references on my page may be of interest. http://www.netcom.com/~optmagic/index.html#Synthesis -- Steven Knapp OptiMagic Logic Design Solutions E-mail: optmagic@ix.netcom.com Programmable Logic Jump Station: http://www.netcom.com/~optmagic Austin Cassidy <oz@vsprsun_18> wrote in article <1997Feb27.112430.7603@queens-belfast.ac.uk>... | Hi, | | I am a user of Synopsys and Mentor Graphics Autologic. I am currently developingsome teaching/labarotory materiel for MSc level work. Does anyone out there | know how to instantiate Xilinx elemnts directly into the VHDL code to add | elements like the osc4 (XC4000) library. The intention is then to run through | Mentor Autologic to synthesize the design.If anyone has an example of how to do this it would be great... | | Sorry if this seesm like a dumb question, but I have been pulling whats left | of my hair out over the last few weeks because of this... ;-( | | | ------------------------------------------------------------------------- | Austin Cassidy, Senior Engineer | Dept. of Electrical Eng Tel: 44 1232 274275 | Queen's University of Belfast Fax: 44 1232 667023 | Ashby Building, Stranmillis Road E-mail: A.Cassidy@ee.qub.ac.uk | Belfast, BT9 5AH, NORTHERN IRELAND http://www-dsp.ee.qub.ac.uk/oz.html | ------------------------------------------------------------------------- | |Article: 5595
Hi, I am looking to buy an SMT Assembly/Rework soldering tool. I have looked at the Leister 7S and the price of the main unit is good, the nozzle prices are absurd... I know you can get the OK nozzels or Hako nozzels to fit this unit, and they can be priced quite a bit better (the OK at least)... Weller makes a not air unit too that has real good prices on the nozzels... Anyone have any experience/opinions with this unit, or can recommend any other? I like the idea that the Leister 7S is easily portable... This unit will only be used for prototype rework and small assembly... Thanks, Austin Franklin ..darkroom@ix.netcom.com.Article: 5596
http://www.synplicity.com or http://www.aceo.com Both offer a very good fpga synthesis tool. Suzanne Southworth ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ P Nibbs (pnibbs@icd.com.au) wrote: : Hi All, : I would be very greatful if anybody was aware of a site on the WWW where : I could find information on the market share of the major FPGA EDA : vendors - in particular in relation to their synthesis tools. : Thanks in advance for any help, : Cheers, : Phil.Article: 5597
Peter Alfke wrote: > = > Well, well. > This was an attack on the accuracy of my app note about driving 3.3 V > devices with our XC4000 outputs, see the Xilinx Data Book, page 6-3/4. > That app note was 100% my idea and my writing, so here I am: > = > The explanation is =B3long drawn-out=B2 because the issue is complex. The= word > =B3nominally=B2 was only used to demonstrate that it is important to use > worst-case rules. > I invite everybody to read the analysis. It assumes worst-case conditions= =2E > It talks about the possibility of 5 V and 3.3 V supplies "tracking > reasonably=B2 , but then analyses the worst case where they do not. And i= t > says clearly that the nominally 5 V supply must not go to 5.5 V when the > nominally 3.3 V supply is simultaneously at 3.0 V. I leave it to the > designer to draw the proper conclusion. > = > I stand behind this app note. It was meant to show that there is more to > an IC than the data sheet numbers. Most manufacturers still claim that > input excursions in excess of 0.5 V beyond the supply are dangerous. They= > are not, as long as the current is limited. After careful investigation > and testing, we changed the Xilinx data sheet to allow up to 10 mA > forever, and 2 V for a typical reflection of max 20 ns. > My app note is carefully phrased and gives the potential user all the > information needed to use it, or reject it. This was not written by > Marketing.cut > Yes, I would fly in a plane that uses an XC4000 to drive a nominally 3.3 = V > input. Why not ! Peter - I read your note, it seemed well reasoned, and I'm currently checking out the proto of a design using 3.3 V Burst Cache SRAM connected to 5V 4000= E. Will let group know in a week or two how it works, and in about 6 months how it holds up in production. Keep up the good information. -- = John L. Smith Univision Technologies, Inc. 6 Fortune Drive Billerica, MA 01821-3917 jsmith@univision.comArticle: 5598
Don Husby wrote: > > But, they kept the feature where a schematic always comes up > zoomed halfway out inside a small window within another small > window. You still have to click in three different places to > bring up your schematic to a reasonable view. Hah! but you must have 7.2 or earlier. 7.3 will zoom a sheet to the same level as the last time you shut it down. Or you can do some exploring and write a simple OLE controller as I did using Delphi 2.0 to not only force a full image but to automatically load the last used file. Before we dropped the product, I was about to expand it to allow me to start it up with any chosen sheet. Robert H. Owen remove the # to email.Article: 5599
Thanks to everyone who replied to my query on search engines for electronic components. Below is a summary of those sites that I found useful/interesting. I've divided them into 3 catagories. You'll notice that my search broadened a bit beyond search engines, but all these sites provide a wealth of info if you're looking for part information. Enjoy! 1. Electronic Component Search Engines IC Master Online (Paid Subscribers Only) http://www.icmaster.com/ IHS CapsXpert (Paid Subscribers Only) http://www.ihs.com/ Chip Directory @hitex (CA US Mirror) http://www.hitex.com/chipdir/chipdir.html Part.Net (Includes electro-mechanical parts) http://www.part.net:80/partnet/home.htm QuestLink Technology - The IC Index http://www.questlink.com/ 2. Online Datasheets DesignInfo (Searchable Engineering Catalogs/Datasheets on the Net) http://www.designinfo.com/ The EE Shop @Univ of Nebraska, Lincoln http://www.engr.unl.edu/ee/eeshop/databook.html Global Semiconductor Datasheets Library - Icesoft, Taiwan (Kanji text!) http://www.semi.com.tw/ Nico Coesel's Online Datasheet URL's http://homepage.cistron.nl/~nctnico/databook.htm 3. Semiconductor Manufacturer Lists/Sites EEM Online (Can do part searching here too) http://www.eemonline.com Gray Creager's Web Site (The "verbose" listing is handy) http://www.scruz.net/~gcreager Roger Sligar's Semiconductor Resource Page http://www.mindspring.com/~the1/semi.html -- Lance Gin "Off the keyboard, over the bridge Delco Systems-GM Hughes Electronics through the gateway, C43LYG@dso.hac.com nothing but NET!"
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