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kurt@emphasys.de wrote:
>I'am designing Xilinx FPGAs with mixed mode entry: Schematic entry and
>ABEL, using the Synario-System. In the schematic entry system, it is
>possible to use CLBMAP and TIMESPECS. But with ABEL it is not.
I have some tools that extend Viewlogic to allow Equations, CLBMAPs,
and ROMS to be placed as text directly on a schematic page. This is
extremely useful to me - I wouldn't do a design without it. I'd sure like
to see it (or something like it) become a standard supported by Xilinx or
Viewlogic or AT&T.
I've put these tools at an FTP site before, if anyone wants the most
recent version, let me know, and I'll put it there.
Here's the help page:
========================================
xfunc.awk (xfunc.exe):
Add extended functions to workview schematic files.
This allows you to add function generators (FUNCS), ROMs, and map
attributes to a workview schematic. These can be added either as
schematic symbols or as unattached attributes. The XFUNC program works by
post-processing .wir files and converting FUNC, ROM, and MAP attributes
into symbols that are recognized by WIR2XNF (or other WIR processors).
Xfunc should be run after a schematic change and before WIR2XNF or XMAKE.
It can be added to an XMAKE makefile.
Usage:
Xfunc [-d <wir>] <files> [-all]
<files> A list of files to be processed. Wildcards can be used. If
no file type is specified, then .1 is used.
-all Process all .wir files in the directory.
-d <wir> Specify a directory to find .wir files. Default is .\wir.
-copya Copy symbol attributes to all symbols in function.
(Default is to put attributes on output gate or FF only).
Examples:
Xfunc tester.* ! Do all sheets of .\wir\tester
Xfunc -all ! Do all files in .\wir
Xfunc -d \wv\usrlib\wir -all ! Do all files in usrlib
FUNCs: UFUNC, FFUNC, HFUNC
FUNCs are Workview schematic symbols or attibutes that allow
functionality to specified in terms of equations rather than gates. The
FFUNC and HFUNC parts are similar to the X4000 FMAP and HMAP parts: they
specify the contents of a single CLB function generator. The UFUNC is an
unconstrained function generator that can be used in X4000 or X3000
schematics. When used as an attribute, it takes the form:
UFUNC <name>=<equation>
or
UFUNC <name>(<clk>,<cke>,<clr>)=<equation>
<name> is an output signal name and must be a valid viewdraw net name.
<equation> is a logic equation that uses other viewdraw nets.
The second form allows a flip-flop to be added to the output. The <clk>,
<cke>, and <clr> fields are names of nets to be connected to the flip-flop
control signals. If <cke> or <clr> are left blank, they are un-connected.
If <clk> is left blank, it defaults to the name "CLK".
Examples:
UFUNC PARITY=DB0@DB1@DB2@DB3 ! generate 4 bits of XOR parity
UFUNC STATE4(CLK,,RESET)=STATE3*DRDY ! a flip-flop output
UFUNC STATE5()=STATE4*MRDY ! also a FF output with default CLK.
FFUNC ACK=STATE4*/STATE5 ! Ouput mapped with X4000 FMAP.
SYMBOL VERSION:
When used as a schematic symbol, a FUNC looks like this:
_
U= _|-- Basic symbol.
_
U=EN*(SEL*A+/SEL*B) _|-- Symbol with function specified
_
CE=EN3 Q=EN*(SEL?A:B) _|-- Registered function with clk enable.
The part has only one pin - the output pin. Input signals are implied
in the equation and are attached automatically to existing nets with the
same names. The function text is specified as an attribute. It is
entered by selecting the part and executing the Workview CA command. The
text must not contain any spaces. A flip-flop can be added by attaching
a clock attribute (K=), enable attribute (CE=), or clear attribute (RD=).
The FUNC symbol has one advantage over the FUNC attribute: it can accept
other attributes. In particular, it can take a label, BLKNAME, or LOC
attribute.
OPERATORS:
FUNCs can use the following operators in order of increasing precedence:
a?b:c select (translates to a*b+/a*c)
a+b or
a@b xor
a*b and
/a invert
() grouping.
ROMS:
A ROM allows functionality to be specified in terms of vectors. It's
similar to the standard xilinx ROM parts, except that it works on X3000 as
well as X4000, and the inputs are not constrained by function generators.
As with FUNCs, a ROM can be specified as an attribute or a symbol.
As an attribute, the ROM takes the form:
GROM <output>,<inputs>=<vector>
<output> is the output net name.
<inputs> is a list of inputs (address bits) separated by commas.
The list can be a bus of the form A[n:m]. The inputs are
specified from most-significant to least-significant.
<vector> is a hex number that specifies the bit pattern for the rom.
The most significant digit maps to higher addresses as per the
Xilinx ROM part.
As a symbol, the ROM is a 2-pin device. The output pin is a single net.
The input pin is a bus. The vector is specified as an attribute (F=).
The symbol must have a name that starts with the letters GROM.
Examples:
GROM THREE,I[2:0]=08 ! THREE=/I2*I1*I0
GROM SEG0,B3,B2,B1,B0=c7ed ! Top segment on 7-seg display.
MAPs:
MAPs are the same as xilinx standard FMAP,HMAP,and CLBMAPs, except that
they can be specified as unattached attributes. They take the form:
FMAP <output>=<in1>,<in2>,<in3>,<in4>,<Attr>=<value>...
HMAP <output>=<in1>,<in2>,<in3>,<Attr>=<value>...
CLBMAP x,y=a,b,c,d,e,f,k,ec,rd,di,<Attr>=<value>...
NOTES:
1) This is compatible with earlier versions of FUNC that were implemented
as XNF-file processors. FUNCs can now be included in any level of the
heirarchy without requiring them to be viewdraw "Modules".
2) The FFUNC part allows a maximum of 4 unique signal names in the
function. If there are more, XFUNC.AWK will print a warning message, but
will not declare a fatal error. HFUNC allows a maximum of three unique
names. Usually, two of the inputs to an HFUNC should be from FFUNCs.
4) Reliablility: I have used earlier versions of FFUNC and HFUNC
extensively in several X3000 and X4000 designs. This version has been used
in a few X3000 designs and many AT&T ORCA designs. Basic functionality has
been tested with small test designs.
5) Future plans: I plan to add an optimizer to the GROM parts and extend
the vector format to include "don't care" and binary vectors.
FILES:
xfunc.awk Awk source code.
xfunc.exe Executable
xfunc3k.inc Include files. Copy 3k or 4k version to the design
xfunc4k.inc directory depending on which part you are using.
xfuncneo.inc
xfunc.man This help file
.\wir\*.1i Temporory file used to process wir file.
Article: 3301In article <HOLMES.96May9134714@yaz.chrysal.com>, holmes@yaz.chrysal.com (Christopher G. Holmes) wrote: Xilinx is ramping > down production on the 7318's, so they're now more expensive than the 7336 That is true, and I was wrong. Although the XC7318 is smaller, it was only produced in the fastest speed grades, and the XC7336 is actually cheaper now than the XC7318. Common sense and extrapolation does not always produce the correct answer, but at least I'm willing to admit it. I will repent over the weekend. Peter Alfke, still Xilinx Applications.Article: 3302
Hello, With the various responses, I did eventually solve it. If anyone is interested in the schematic I used, please e-mail me, or I can post it here. Peter.Article: 3303
>I am looking for free tools (or shareware) to program for >instance the XC3030. >I dont need schematic capture etc. for me it is sufficiant if I >can enter logic equations. It would be great if there is maybe a >subset of VHDL implemented to describe state machines. I am sure these have never existed. The Xilinx tools have been dongled from the start. This is of course somewhat silly, since they can hardly be used for anything other than programming Xilinx's chips! Even the Orcad route, which is arguably the cheapest, costs money because you need the basic DS502 place/route kit with the Orcad library. This costs $3000 approx, if you already have Orcad SDT. But for anything other than trivial designs you will also need a simulator, and in my experience the Orcad one is not very good. The more usual solution, Viewlogic and DS502, costs around $8000, although this varies a lot. Peter.Article: 3304
Looking at the market, the Orcad PLD 386+ pld complier is the only one we can afford. We already have Orcad schematic capture and PCB tools. Does anyone out there have experience of this programable logic compiler ? Can anyone compare it with other generic tools on the market? We do not want to be tied into a single device vendor, but we might have to rethink if no one is able to put in a good word for Orcad. Cheers -- Steve Dewey Steve@s-dewey.demon.co.uk Too boring to have an interesting or witty .sig file.Article: 3305
Steve Dewey <Steve@s-dewey.demon.co.uk> wrote:
>Looking at the market, the Orcad PLD 386+ pld complier is the only one we can
>afford. We already have Orcad schematic capture and PCB tools.
>Does anyone out there have experience of this programable logic compiler ?
>Can anyone compare it with other generic tools on the market? We do not want
>to be tied into a single device vendor, but we might have to rethink if no one
>is able to put in a good word for Orcad.
>Cheers
>--
>Steve Dewey
>Steve@s-dewey.demon.co.uk
>Too boring to have an interesting or witty .sig file.
Steve, we bought Orcad PLD 3-4 years ago. I found it very useful, and
for the specific project we wanted it for it was very valuable.
However, my experience is based only on programming smaller chips,
specifically PEEL18CV8. How well Ordcad works on larger chips I cannot
say. My main complaint about the one I bought is that it is a DOS
package which will not run in a Win3.1x DOS window. It also *demanded*
a non-Microsoft memory manager (I have Quemm 386) which makes the
setup of my computer very precarious (i.e. I daren't change anything).
If the version you are looking at is non-windows, be prepared to lock
a machine in the past with it. (I could be off the mark here, as I've
not kept my Orcad upgraded. I also *resent* buying a DOS product for
over $3000 then being told some months later it is going to cost a
bundle to convert to Win)
BTW, we don't have any other Orcad products, so our selection was
based on price and functionality only. I spent a lot of time looking
at supported chips, as at that stage the chip was also being selected,
and Orcad seemed to have good coverage. If you are looking at modern,
_huge_ chips, then I believe the compilers actually use add-ins from
the chips maker, which obviously makes the situation much more
complex.
Not much help, am I?
David
Microconsultants http://www.microconsultants.com
SPLat low cost programmable industrial controller
GaugeLink digital caliper interface
Support software is free for download
for ftp: ftp://ftp.microconsultants.com
Article: 3306
Kim KuHwan <kimkh@pusan.ac.kr> wrote:
>I need to know the mailing list about SYNOPSYS and XILINX(XSI) and VHDL.
>Is there mailing list for these.
Kim, I run the grassroots "E-mail Synopsys Users Group (ESNUG)" which is
a group of about 4000 design engineers who share the bugs, their workarounds
and their opinions on Synopsys and EDA related products in a free weekly
e-mail newsletter. This is not something Synopsys, Inc. controls; it's
something user-driven. A typical sample of what we've recently talked about:
* - rules of thumb for synthesizing ROM's.
* - what (anonymous) users have reported about the new cycle based
simulators various EDA vendors are working on.
* - what are the best & worst available PCI parts/models available.
* - useful Verilog checking tools.
* - a variety of Synopsys bugs & workarounds.
* - initial customer impressions of Synopsys Behavioral Compiler.
* - is Power Compiler really useful?
* - how to port from Synopsys to { Mentor, Cadence, ViewLogic }
* - doing incremental synthesis on SRAM based FPGA's
In running ESNUG I allow engineers to post their info anonymously (if they
request it) because many times that's the only way we can get the real
story. To join, all you have to do is send an e-mail to me at
"jcooley@world.std.com" with your CORRECT e-mail address in the body
of your e-mail and I'll gladly add you to the distrubution list.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4258 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 3307Hi Steve --- I've used the OrCad PLD package in an earlier version (V4.xx) and have had very good success with it. I've used the CUPL compiler at work and the OrCad package is a -lot- more friendly and easier to use. The library supplied with it is able to handle many different chip configurations, including some unique ones. If you're used to the OrCad schematic package, the PLD package is a natural follow-on. You have an option of describing your PLD circuit in equation format, in a combination of equations on a schematic format, or in schematic format. I've always used the schematic method, as it visibly defines the oper- ation of the PLD. The manuals that came with it were all very clear and included a tutorial section for a typical application. I think the 386 version is pretty much the same as V4.x. I hope this helps. DaveArticle: 3308
David, >However, my experience is based only on programming smaller chips, >specifically PEEL18CV8. The other thing here is that whereas equation entry etc is the standard design method for small PLDs, one would not use it for the big ones, unless the contents is something which particularly lends itself to that type of design, or unless one is into VHDL and the learning curve there. >My main complaint about the one I bought is that it is a DOS >package which will not run in a Win3.1x DOS window. It also *demanded* >a non-Microsoft memory manager (I have Quemm 386) which makes the >setup of my computer very precarious This is very bad, and sounds like some mid-1980s crappy DOS extender program. I have a 1994 version of SDT/386 which runs fine in a win3.x DOS box, regardless of memory manager (full screen only of course, being 1024x768 graphical) but not under NT. And who will be running 3.x in a few years' time? But I am very happy with this DOS product. It will always run, under DOS, long after win3.x is gone. >I also *resent* buying a DOS product for >over $3000 then being told some months later it is going to cost a >bundle to convert to Win) Quite. Especially given the reported buginess of the Windows version. Orcad got too late to Windows, and this is also a bad time to make a choice, because win3.x is on its way out, so any tool one buys today which needs to be reasonably future-proof must run under NT (and win95 if you intend to play with that in the meantime). >Not much help, am I? Nor am I :) I would advise the original poster to get CUPL. I have been using this for years, and its state machine processor is excellent. There are also routes to FPGA designs; I have been doing Xilinx designs in both schematic entry (Viewlogic) and CUPL. Peter.Article: 3309
In message <<3194494f.3914010@news.dial.pipex.com>> ft63@dial.pipex.com writes: > >I am looking for free tools (or shareware) to program for > >instance the XC3030. > >I dont need schematic capture etc. for me it is sufficiant if I > >can enter logic equations. It would be great if there is maybe a > >subset of VHDL implemented to describe state machines. > > I am sure these have never existed. The Xilinx tools have been dongled > from the start. This is of course somewhat silly, since they can > hardly be used for anything other than programming Xilinx's chips! > This , more than any other factor, has to be a great reason to use Altera devices. The software is reasonably priced/free (the PLS/ES package) Doesnt have the bloody dongle, has all the bells & whistles like onboard schematic entry. Xilinx's high cost software precludes its use by small players. If your design can fit into an EEPLD, the AMD MACH devices are worthy of consideration (free MACHXL software) and Lattice (reasonably priced Synario system). MArticle: 3310
In article <4996132.32037.23705@kcbbs.gen.nz>, Mike Diack <moby@kcbbs.gen.nz> wrote: >In message <<3194494f.3914010@news.dial.pipex.com>> ft63@dial.pipex.com writes: >> >I am looking for free tools (or shareware) to program for >> >instance the XC3030. >> I am sure these have never existed. The Xilinx tools have been dongled >> from the start. This is of course somewhat silly, since they can >> hardly be used for anything other than programming Xilinx's chips! >> > >This , more than any other factor, has to be a great reason to use >Altera devices. The software is reasonably priced/free (the PLS/ES >package) Doesnt have the bloody dongle, has all the bells & whistles >like onboard schematic entry. Xilinx's high cost software precludes its >use by small players. If your design can fit into an EEPLD, the AMD >MACH devices are worthy of consideration (free MACHXL software) and >Lattice (reasonably priced Synario system). I don't think you were reading the first post. There is a basic up-to-3030 package from Xilinx for a pretty low cost. Ask your disti, as I recall it was around $1K. That still doesn't buy a front end, but there are tools around on the net that generate XNF, if you have a sniff around. don't look for any support on them, though. FWIW, Arnim. -- Arnim Littek arnim@actrix.gen.nz Actrix Networks Ltd. fax +64-4-499-1130 uucp/PPP/SLIP/BBS accounts tel +64-4-499-1122Article: 3311
Peter wrote: > This is very bad, and sounds like some mid-1980s crappy DOS extender > program. I have a 1994 version of SDT/386 which runs fine in a win3.x > DOS box, regardless of memory manager (full screen only of course, > being 1024x768 graphical) but not under NT. And who will be running > 3.x in a few years' time? But I am very happy with this DOS product. > It will always run, under DOS, long after win3.x is gone. Of course, it now doesn't work in the DOS mode of Windows 95. So, if you buy the DOS version of OrCAD, expect it to fail if you upgrade your operating system. Also, expect a lot of trouble with high-resolution display drivers if you plan to use them. Time for a nap... -- Rune Baeverrud <r@acte.no> Field Application Engineer |\ _,,,---,,_ ScandComp, ACTE NC Norway AS ZZzz /,`.-'`' -. ;-;;,_ P.O. Box 190, N-2020 Skedsmokorset, Norway |,4- ) )-,_..;\ ( `'-' Tel: +47 6389 8900 Fax: +47 6389 8979 '---''(_/--' `-'\_)Article: 3312
Christopher <101337.2254@CompuServe.COM> wrote: >Hi guys out there in the world, > >I am looking for free tools (or shareware) to program for >instance the XC3030. >I dont need schematic capture etc. for me it is sufficiant if I >can enter logic equations. It would be great if there is maybe a >subset of VHDL implemented to describe state machines. > >Anybody who can point me into the right direction? > >thanks very much >Chris Re: Looking for free FPGA softw./Xilinx Hi I'm pretty sure you won't find a tool free of charge. But you can try an evaluation version of LOG/iC2 which is unlimited and runs for 30 days. This version can be downloaded end of may from ISDATA's homepage: http://www.isdsta.de Here is a desciption of LOG/iC2: LOG/iC2 is a system for design entry, synthesis and simulation for CPLDs and FPGAs LOG/iC2 was developed especially for the design of complex systems. A large design can be divided into neatly arranged partial designs with the graphical hierarchy editor. For every partial design you can use the most suitable description format, e. g. VHDL, LOG/iC HDL (Boolean equations, function tables, state machines), macros, or 74xx elements. The LOG/iC2 macrogenerator is a very powerful tool to synthezize regular strucures like adders, counters, parity generators etc. within seconds. The hierarchical procedure allows you to focus on testing a partial design. The LOG/iC2 system automatically tests each module for consistency, incomplete circuit definitions and deadlocks. The LOG/iC2 simulator features functional, pre- and postlayout timing simulation. For PLDs and CPLDs the proven FACT optimizer, which is well known from the LOG/iC Classic series, is applied for synthesizing a design using a minimum number of product terms. For FPGAs LOG/iC2 performs the so-called "Technology Oriented Synthesis" which leads to much better results than the library based approach. For Xilinx LCAs a functional decomposition is done, for Actel FPGAs LOG/iC2 uses BDD and boolean matching algorithms. LOG/iC2 supports all Simple PLDs, all popular CPLDs like AMD MACH, Altera MAX, Atmel, Cypress FLASH, Lattice pLSI, Philips PXA, Xilinx EPLD and FPGAs like Xilinx LCAs and Actel FPGAs. All LOG/iC2 modules are 32 bit applications and run under Windows 3.11 and Windows 95. LOG/iC2 is structured modular and the price depends on the modules you choose. Pricing starts from DM 10.000. NEW - NEW- NEW - NEW- NEW - NEW- NEW - NEW- We have a new series: LOG/iC2 CL LOG/iC2 CL offers a low cost entry to LOG/iC2. It is full compatible to LOG/iC2. The only difference is the limitation of supported devices. We will have four versions: 1. LOG/iC2 CL PLD DM 980.- Supports all Simple PLDs 2. LOG/iC2 CL CPLD DM 1980.- Supports all CPLDs up to 96 macrocells 3. LOG/iC2 CL Xilinx DM 1980.- Supports all LCAs up to 3000 gates 4. LOG/iC2 CL Actel DM 1980.- Supports all Actel FPGAs up to 2500 gates All versions include hierachical design entry supported by our graphical hierarchy editor, the 74xx library, the macrogenerator, the optimizers and the simulator. We have a free of charge limited evaluation version which supports 16V8, 20V8 and 22V10. Best Regards By the way: >From may on we are on the internet and can be found at http://www.isdata.deArticle: 3313
Hi, The CAD-Team of our school has just opened a new list of interesting sites for designers in electronics. You will find many links to firms, data books and also information about our team. This page is unfortunatly still in French but in will be translated in the next weeks (don't worry, a list of links is easy to understand in any language :-D) The URL is: http://www.efrei.fr/Efrei/es-cao/ FranckArticle: 3314
In <4n26vb$jhv@news.mel.aone.net.au>, dgibson@microconsultants.com (David Gibson) writes: >Steve Dewey <Steve@s-dewey.demon.co.uk> wrote: > > >>Looking at the market, the Orcad PLD 386+ pld complier is the only one we can >>afford. We already have Orcad schematic capture and PCB tools. > >>Does anyone out there have experience of this programable logic compiler ? >>Can anyone compare it with other generic tools on the market? We do not want >>to be tied into a single device vendor, but we might have to rethink if no one >>is able to put in a good word for Orcad. > >Steve, we bought Orcad PLD 3-4 years ago. I found it very useful, and >for the specific project we wanted it for it was very valuable. > >However, my experience is based only on programming smaller chips, >specifically PEEL18CV8. How well Ordcad works on larger chips I cannot >say. My main complaint about the one I bought is that it is a DOS >package which will not run in a Win3.1x DOS window. It also *demanded* >a non-Microsoft memory manager (I have Quemm 386) which makes the >setup of my computer very precarious (i.e. I daren't change anything). >If the version you are looking at is non-windows, be prepared to lock >a machine in the past with it. (I could be off the mark here, as I've >not kept my Orcad upgraded. I also *resent* buying a DOS product for >over $3000 then being told some months later it is going to cost a >bundle to convert to Win) OrCAD SDT, PCB and PLD 386+ run very well in a DOS session of OS/2. Absolutely no problems as fas as the OS environment is concerned. Frank Bures, Dept. of Chemistry, University of Toronto, ON fbures@alchemy.chem.utoronto.ca CompuServe:71324,1515 Frank_Bures@compuserve.comArticle: 3315
In <3196EC89.20F@acte.no>, Rune Baeverrud <r@acte.no> writes: >Peter wrote: > >> This is very bad, and sounds like some mid-1980s crappy DOS extender >> program. I have a 1994 version of SDT/386 which runs fine in a win3.x >> DOS box, regardless of memory manager (full screen only of course, >> being 1024x768 graphical) but not under NT. And who will be running >> 3.x in a few years' time? But I am very happy with this DOS product. >> It will always run, under DOS, long after win3.x is gone. > >Of course, it now doesn't work in the DOS mode of Windows 95. So, if you buy the >DOS version of OrCAD, expect it to fail if you upgrade your operating system. >Also, expect a lot of trouble with high-resolution display drivers if you plan >to use them. I have run OrCAD SDT, PCB and PLD in a DOS session of OS/2 in 1024x768 for more than a year. No problems at all. I frequently switch from OrCAD to telnet (I keep an eye on our UNIX systems) and back. I am very satisfied with the product. Frank Bures, Dept. of Chemistry, University of Toronto, ON fbures@alchemy.chem.utoronto.ca CompuServe:71324,1515 Frank_Bures@compuserve.comArticle: 3316
cool, thats just the direction I looked for. thanks very much!Article: 3317
We are looking for some good people who can do any of these: DSP algorithms, array signal processing, VHDL/ASIC/FPGA, digital board design (including CPU boards) OR junior software and PC support. Also, we would like to meet consultants who have had experience in DSP algorithms, array signal processing OR CPU and digital board design. We are located on the North Shore in Massachusetts. For more info, email details of your technical skills to the GPS Systems Engineering Department.Article: 3318
>This , more than any other factor, has to be a great reason to use >Altera devices. The software is reasonably priced/free (the PLS/ES >package) Doesnt have the bloody dongle, has all the bells & whistles >like onboard schematic entry. Xilinx's high cost software precludes its >use by small players. If your design can fit into an EEPLD, the AMD >MACH devices are worthy of consideration (free MACHXL software) and >Lattice (reasonably priced Synario system). >M There are as many opinion camps on FPGAs as there are pop groups :) I think the ideal FPGA would be EEPROM/FLASH-based, with few-wires in-circuit reprogrammability, few-ns pin-pin delay, near-100% routability, cheap, with free software and free support. Given a few more years, you will get all but the last two of these. I asked Xilinx why they don't give their place/route s/w away, and they told me it was thus priced to limit their tech support workload. And this cannot be underestimated. The learning curve can be awesome, and this is in addition to the long learning curve for the schematic/simulation tools themselves. This is why Xilinx (I am *not* defending them) tend to offer the Viewlogic kit; a lot of large-firm users already know it. I have been doing Xilinx design for a few years, and I still use only a small part of the functions of these tools. For example, I totally ignore the "floorplanning" crap; I just start the placer and go to bed, and see what turns up in the morning. I have often looked at the AMD and Lattice parts. While their tools are indeed cheap, I ask myself "will these tools still be supported in a few years' time?". In the case of win3.x tools, the answer has to be "no", because few people will still be running win3.x then, and American firms are generally very quick to dump "legacy" environments. So one ends up keeping an old PC in the corner somewhere, in case you have to revisit that project sometime in the future. But for someone with a very small budget, and more time to play around, these parts are probably the ideal solution. Peter.Article: 3319
Hi, Anyone have experience with Exemplar and Xilinx 4013s where it was only 80% utlilized but wouldn't route? In synopsys language, I think I need to increase the "porocity" of the design. I have other designs that are 90% and route, but for some reason this one is real bad. The design in nearly completely random logic. only 42 DFFs. I've tried all of the settings in Xilinx PPR, various seeds, max place & route effort... I even tried PPR on some of the less than optimal netlists from Exemplar. But still won't route. Any options that might help??? We'll use the 4020 if we have too, but they're hard to get... The design is in VHDL. IOs are locked (don't get on my case here!!! unlocking the IOs only goes from about 200 to 100 unroutes). I tried synthesizing with another synthesizer but it came up with 105% utilization... -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable HDL Cores 20 Trafalgar Square http://www.vautomation.com Suite 443 Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 3320
On Fri, 10 May 1996 14:19:30 +0100, Andy Gulliver <andy.gulliver@crossprod.co.uk> wrote: >Christopher wrote: >> >> Hi guys out there in the world, >> >> I am looking for free tools (or shareware) to program for >> instance the XC3030. >> I dont need schematic capture etc. for me it is sufficiant if I >> can enter logic equations. It would be great if there is maybe a >> subset of VHDL implemented to describe state machines. >Unlikely, I would have thought :-( >Even the cheapest XILINX tools are around 1000ukp minimum ,3rd party s/w >tends to be even more expensive..... For up to 2000 gates, look at Lattice Logic's smallest ispLSI devices. If they will fit your needs, good. Lattice do a starter kit for 70 UK pounds ( $100ish?) with software, a couple of devices, and "programmer" (printer port download cable). Entry is a mixture of graphics to place and interconnect blocks, (not schematic capture exactly) and equations to define your own blocks. Fairly easy to use. The drawback is that the starter software is limited to the smallest devices in the family (hence the 2000 gate limit) though for fairly reasonable prices ( $1K or so) you can buy the full software, handling devices up to 12-18000 gates. (Don't quote me on exact gates/prices though) IMO The ISPlsi starter kit is worth looking at for your needs. - BrianArticle: 3321
Volker Kurt Kamp wrote:
> I'am designing Xilinx FPGAs with mixed mode entry: Schematic entry and
> ABEL, using the Synario-System. In the schematic entry system, it is
> possible to use CLBMAP and TIMESPECS. But with ABEL it is not.
Enclosed are ABEL examples for CLBMAP and TIMESPEC. You use almost every
"schematic" feature in Synario's ABEL and VHDL. The CLBMAP example is
from the Synario 2.2 online help while the TIMESPEC example is a
translation of the online VHDL example.
Michael Holley
Synario Design Automation
ABEL Example for CLBMAP
module clbmap1
library 'xc_3000'; "so macros can be used
"inputs
in0,in1,in2,in3,in4,in5,clk pin;
"internal nodes
and01,and23,and45 node;
in_and node;
"outputs
out pin istype 'reg' ;
equations
and01 = in0 & in1;
and23 = in2 & in3;
and45 = in4 & in5;
in_and = and01 & and23 & and45;
out := in_and;
out.clk = clk;
declarations
CLBMAP (PLC LOC=BC A=in0 B=in1 C=and23 D=in4 E=in5 K=clk Y=out)
end
ABEL example for Timespec
MODULE FFPERF1
title 'XACT Performance Example
How to specify Path-Type performance
XACT 5 Reference Guide, Volume 1, Page 1-101'
" Inputs
NA4,NA3,NA2,NA1,NA0 pin;
D_ENABLE,D_A,CLK1,CLK2 pin;
" Outputs
A,B,C,D pin istype 'reg,buffer';
" Internal Node
NAND_O node;
" LCA properity macro library
library 'xc_4000';
" Force clocks to BUFGP
BUFGP (CLK1 CLK2)
" Attach TS flags to nets
FLAGNET (TS02 CLK2)
FLAGNET (TS03 B)
FLAGNET (TS04 D_ENABLE)
" Create TIMESPEC symbols
TIMESPEC (TS01=DC2P:50 TS02=C2P:40 TS03=C2P:30)
TIMESPEC (TS04=C2P:20)
EQUATIONS
NAND_O = !(NA4 & NA3 & NA2 & NA1 & NA0);
A := D_A;
A.clk = CLK1;
B := NAND_O & A;
B.clk = CLK2;
C := !(NAND_O $ B);
C.clk = CLK2;
D := !(NAND_O & !B);
D.clk = CLK2;
D.ce = D_ENABLE;
END
Article: 3322In article <31973371.9233661@news.dial.pipex.com>, ft63@dial.pipex.com (Peter) wrote: Xilinx's high cost software precludes itsuse by small players. No more! If you thought that Xilinx software used to be too expensive, there now is a very attractively priced Windows-based package: Xilinx sells ³Foundation Base² for US$ 995, a ³shrink-wrapped² complete package without a dongel (!). It has a Schematic Editor and Gate-level Simulator. Design Manager, Flow Engine, Timing Aanalyzer, Hardware debugger and PROM File Formatter are all included. The package supports low-complexity FPGAs ( up to and including XC3042, XC4003, XC5204) and all XC7300 and XC9500 CPLD. XABEL is also included, but it requires a dongel. For US$ 500 more, VHDL Synthesis and XBLOX are added to the package. Prices in the UK and in NZ should be roughly equivalent. $ 1000 is not exactly ³free², but should qualify as ³affordable² for many. Sorry for the commercial, but I had to refute those obsolete postings. Peter Alfke, Xilinx Applications ( different "Peter" )Article: 3323
Rune Baeverrud <r@acte.no> writes:
>> 3.x in a few years' time? But I am very happy with this DOS product.
>> It will always run, under DOS, long after win3.x is gone.
>Of course, it now doesn't work in the DOS mode of Windows 95. So, if you buy
>the DOS version of OrCAD, expect it to fail if you upgrade your operating
>system.
Or you could get OS/2 Warp. The only program which broke after I upgraded was
the Borland C++ debugger for Windows; but that was so buggy as to be unusable
anyway (I could only get it to go on a 286 with "virgin" Win 3.1).
Frithiof Jensen.
===============================================================================
The above article is the personal view of the poster and should not be
considered as an official comment from the JET Joint Undertaking
===============================================================================
Article: 3324Has anyone used the Xilinx XACT 6.0 tools with Windows NT or run Cypress Warp 2 or 3 tools (with Workview Office) with Windows NT? Any experiences or warnings welcome :) TIA -Rich Auletta University of Colorado Denver
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