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In article <31a17b14.401501@news.dial.pipex.com>
ft63@dial.pipex.com "Peter" writes:
"
"The Pro series Viewlogic uses a DOS extender which works only under
"win3.x, not win95 or winNT.
"
"Viewlogic have dropped the Pro series quite some time ago (didn't
"sell, reportedly), but Xilinx still sell it.
"
No, Viewlogic dropped PRO Series in favour of products designed to
take advantage of Win32 operating systems. PRO Capture certainly
wasn't perfect, but is still the most widely used entry tool for
FPGA design.
It has been a great tradition of this group over the last three
years to pour scorn on market leaders (i.e. Xilinx for devices and
Viewlogic for EDA). Now that Peter Alfke has come onto the scene,
the Xilinx bashing has all but stopped, and I think the group has
benefitted. Maybe someone from Viewlogic is reading...
--
David Pashley <
------------------------ < < < ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd < < < < > Tel: +44 1280 700262 |
| *The EDA Source* < < < Fax: +44 1280 700577 |
--------------------------- < ------------------------------------------
Article: 3376
I am a graduate student in CAD/VLSI and I need some help.
I am trying to port Berkeley's SIS Xilinx mapped .blif output to
a chip.
SIS have a list of command to place a logic level design in Xilinx's
CLB form. However, SIS's output is still .blif file and I don't know
how to convert this into a Xilinx readable format.
With Dr. Fuminori Kobayashi's (Kyushu Institude of Technology,Japan)
help,
I can map a design using SIS' mcnc.genlib and then run it through
xnfmerge, xnfprep,ppr. This is great, but I would like to see what
SIS' xl... commands do for the design.
Thank you for all your help.
Please email me or post an answer if anyone have any idea.
--
Joe aka. Varin Udompanyanan x(
vjoe@engrhub.ucsb.edu | http://www.engineering.ucsb.edu/~vjoe :%
Maybe a road less traveled is less traveled for a reason =p
GRRrrr... 8b
Article: 3377> > Peter Alfke, Xilinx Applications wrote: > > I think you are right, there are only two types of devices, Atmel's and Xilinx > XC6200. > > Atmel's has internal 3-sate buffers, which means it cannot tolerate a random > bitstream. I would like to thank Peter for that constructive comment (NOT!). If it was worth the effort I would *FLAME* him for lowering the news group to the level of "commercial" attacks. Informing customers of available products is a valuble service that programmable logic vendors provide (I hope), but I would say that 'trashing' competitor products is not something that this newsgroup should stoop to - we (the vendors) can all play that game, almost all of us choose to promote our strengths instead. If you want the real story and not the Xilinx marketing hype see the contact details below. I will also say that Atmel provides several s/w tools to engineer the bitstreams to help prevent this problem but yep your right if you are not careful you can cause internal contention on routing. Interestingly from our direct customer feedback we see that Engineers want to change the logic around the routing and not the routing itself in almost all 'commercial' cases where Dynamic CacheLogic(tm) is used, so tri-state buffers have little or no impact on the reconfigurable designs. Many companies are shipping Atmel product using CacheLogic in commercial products. Reconfigurable hardware is no longer restricted to the research arena. What is much more important here is the s/w support tools to help you design CacheLogic systems - and Atmel has significant experience in this area. If you would like more information check out one of the following sources : Fax on demand 1-800-29-ATMEL (Doc #600) WWW http://www.atmel.com e-mail martin@atmel.com Martin Mason FPGA/AT17CXXX Apps. Engineer Atmel Corp.Article: 3378
For those interested in reconfigurable computing, you will find a report on the FCCM (FPGAs in Custom Computing Machines) on the web at -- and http://www.pldsite.com/features. -- http://www.reconfig.com Stan Baker Editor, "Programming Silicon" (pldsite.com) ********************************************** * SBAssociates, Inc. * * sbaker@best.com * * Ph 408-356-5119 Fax 408-356-9018 * * 504 Nino Ave. * * Los Gatos, CA 95032 * **********************************************Article: 3379
Hi, I get a strange error message from the Floorplanner: I have a simple 4-bit adder design with a carry-look-ahead circuit. When I specify a constraint by using Assign icon (give an area of 7-by-7 for the CLA circuit) it works OK (i.e. it passes the floorplan check and places and routes). However, if I save this constraint to a file and read it again, it gives error (it says "potential error in LOCs or constraints"), and cannot pass the floorplan check. FPLAN.LOG also says: "Cannot place symbol x on block y because it is occupied". In another try, I removed all the files (except my xnf files and the cst file. After mapping, reading the constraint file gives the same error message. Does anyone know what the problem is? Please let me know if you would like to try it and I will send you the .xnf files and the .cst file. Regards, Morteza ____________________________________________________________ Morteza Saheb Zamani E-mail: morteza@vast.unsw.edu.au VaST Lab, School of Computer Sc. & Eng. University of N.S.W. Phone: +61 2 385-4898 Sydney, 2052, AUSTRALIA FAX: +61 2 385-5995 ____________________________________________________________Article: 3380
David Pashley wrote: [cut] > PRO Series 6.0, to which the original poster refers, is about a year > old, and therefore totally predates Windows95. The final version of > PRO Series was 6.1 > > Late last year, Viewlogic unveiled new tools written especially for > Windows95 and WindowsNT, called Workview Office. These new tools > are available for those operating systems, and work very well. > > These are the facts. Please beware of comparing the latest from > "Vendor A" with something historical of unspecified product name or > version from "Vendor B". Ah yes, but whilst Viewlogic are shipping PROseries 6.1, Xilinx are *still* shipping 6.0 - which is what we are stuck with with our XACT system. Xilinx are well aware of the problem, but seem unable/unwilling to help beyond suggesting using Windows 3.11 - not very practical in most cases :-( This experience, plus evaluation of the new Xilinx s/w will probably lead us to drop the Viewlogic approach in favour of the Aldec-based package. This is not necessarily the fault of Viewlogic, who have clearly addressed the issue, but between them Xilinx and Viewlogic haven't got their act together. -- Regards AndyGArticle: 3381
I'd like to use ROMs in a XC 4000 FPGA. For this I created a *.mem File with the Rom Table and started xact memgen program for this file and as a result i got a *.xnf file for this ROM. My problem is now to create a Symbol to use in Mentors Design Architect. The Mentor Manual says that i have to design a symbol with the proerty FILE and VaALUE filename but this doesn't work. Thereis no connection between the Pins of the generated memory and the Symbol pin. It is possible to add this connections manually but that takes long time .. Is there a easier way or where is my mistake? Thanks -- Manfred Aigner alias maigner@sbox.tu-graz.ac.atArticle: 3382
Dear Friends,
I might be wrong but I believe that no synthesizer can optimize
finte state machine (in VHDL) today!
Say I have a state vector, declared in enumarated type
(S0,S1,S2,S3,....,S15) -- the length of the vector is only
an example here.
Almost all synthesizers suggest we use one-hot encoding for
state vector. Well, it does not help synthesizers in optimization
either.
The following statements are typical in a finite state machine
VHDL code (of course we can write it in variation):
-- state transition process
if (CLK'event and CLK='1') then
case state is
when S0 =>
if (some condition is true) then
state <= S1;
else
state <= S3;
end if;
when S1 =>
........
-- register output process
if (CLK'event and CLK='1') then
case state is
when S0 =>
if (some condition is true) then
register_output <= !@@#; -- some signal to update registers
end if;
when S1 =>
.......
-- combinational output process
with state select
combinational_output <= &^&%$$ when S0,
<= !#((# when S1,
...
Ya, have you noticed that how many decoding logics are on the
"WHOLE state vector" in a FSM? I emphasize the word "WHOLE" since
it causes tremendous overhead. In the one-hot encoded FSM, one state
is represented with one single bit and therefore we actually need
bit-comparison rather than vector decoding to control the behavior
of the FSM. Also, it is not necessary to compare every state bit,
because not every output (no matetr registered or combinational) are
sensitive to all state bits.
I do not expect that any Synthesizer can reduce the state operation
from vector to bit-wise. well, thanks the high level description
language that we can avoid the explicit assignment of state bits,
but there is a big bill to pay!
Any comment will be appreciated.
Regards,
Felix K.C. CHEN
--
---------------------------------
Felix, Kuan-chih CHEN (³¯ «a §Ó)
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw
Machines and tools are only as
good as the people who use it.
---------------------------------
Article: 3383You can buy theese sockets in Germany: SELTRONICS GmbH Beethovenstr. 35 D-85521 Ottobrunn Tel. +49 89 609 1001 Fax. +49 89 609 1005 Ask for Mr. Ploeckinger. Good luck. Manfred Kraus, CESYS GmbHArticle: 3384
In article <4n9eaa$m25@rzsun02.rrz.uni-hamburg.de>, klindwor@tech17.informatik.uni-hamburg.de says... > > >I just finished the logic design for an Altera MAX9560RC240-20 CPLD, >but the project doesn't fit. According to the report file, the design >uses 182 out of 191 pins and 485 of the 560 logic cells so a fit may >be possible. The problem is that the compiler gives no hint what causes >the fitting failure. I only get the message > > Error: Project doesn't fit > >The report file refers to the Error Summary section which shall >give detailed error information, but is empty. So I have no idea >what causes the failure. I tried changing some synthesis options >(e.g soft buffer insertion ON, advanced fitter settings), but that >didn't help > >Has anybody experienced a situation like this before and my suggest >how it may be overcome? >How good are my chances to make the project fit by detailed floor-planning? > >Thanks for help, >Andre' Klindworth - speaking for TRINAMIC Electronic System Design GmbH i.G. > >-- >------------------------------------------------------------------------- -- >Andre' Klindworth Universitaet Hamburg, FB Informatik >klindwor@informatik.uni-hamburg.de Vogt-Koelln-Str.30, D-22527 Hamburg >http://tech-www.informatik.uni-hamburg.de/Personal/klindwor/Klindworth.ht ml I have seen this before with a FLEX8000 design that I was using. The problem that I had with this device was that i specified too many separate Tri-state busses. The design had 3 tristate busses but I beleive Upon examination of the global routing and control signals for the design I only had room for two internally so I ended up routing a signal outside then back into one of the global resource signals in the device for the third tristate bus Your problem may not be the size of the device that you are using but instead the way the archecture is trying to fit it - ralph Ralph Watson Systems Group rwwatson@ti.com i don't speak for Texas Instruments and all that other stuff that lawyers like to hearArticle: 3385
>>>>> "MM" == * Atmel FPGA Apps * <* <martin@atmel.com>> writes:
>> Peter Alfke, Xilinx Applications wrote:
>>
>> I think you are right, there are only two types of devices,
>> Atmel's and Xilinx XC6200.
>>
>> Atmel's has internal 3-sate buffers, which means it cannot
>> tolerate a random bitstream.
MM> I would like to thank Peter for that constructive comment
MM> (NOT!). If it was worth the effort I would *FLAME* him for
MM> lowering the news group to the level of "commercial" attacks.
[...]
I've read your post and that of Peter over and over, but I have to
conclude that Peters statement is correct. He didn't say this is bad
and his companies products are better. Atmel parts don't tolerate a
random bitstream, period. Your company provides software that is
aware of that fact and creates bitstreams that are OK. Seems
sensible, but no need to flame anyone.
--
Achim Gratz.
--+<[ It's the small pleasures that make life so miserable. ]>+--
WWW: http://www.inf.tu-dresden.de/~ag7/
E-Mail: gratz@ite.inf.tu-dresden.de
Phone: +49 351 4575 - 325
Article: 3386david@fpga.demon.co.uk wrote: > No, Viewlogic dropped PRO Series in favour of products designed to > take advantage of Win32 operating systems. PRO Capture certainly > wasn't perfect, but is still the most widely used entry tool for > FPGA design. > > It has been a great tradition of this group over the last three > years to pour scorn on market leaders (i.e. Xilinx for devices and > Viewlogic for EDA). Well, who can resist the invitation: A while back, I gave Pro-series viewdraw a favorable review on comp.arch.fpga. Something like: "It has a few rough edges that can easily be cleaned up in the next release, but all things considered, it's a step forward from DOS-based viewdraw." Even running under Win95, it wasn't too unpleasant. I've been using Viewdraw-Office now for a couple of weeks and have the following humble opinion: They've added more rough edges and taken away some really useful stuff. Primarily: They've completely removed command-line entry and macro capability. Operations like changing grid spacing, text orientation, and sheet size are now awkward menu operations. Text orientation, for example, used to be a simple two-keystroke command. Now you have to traverse two menus and then try to select the proper orientation from a list. Object selection no longer works well-- in some cases it's impossible to select text if it's inside a box. Text attributes are no longer sticky -- you have to set text size and orientation each time you enter text, or go to a completely different menu to permanently alter them. Automatic label expansion works differently -- It's no longer possible to select a group of existing labels on a bus and re-label them. The change-component command is gone. To change a component, you have to delete the old component and add the new one. It's no longer possible to customize tool bars. There are 4 fixed toolbars, inconveniently located at each edge of the screen. They waste a lot of screen space and are awkward to use. Dialog boxes disappear without doing anything when you hit ENTER. For example if you bring up the Add-Component dialog, type the name of a component, and press Enter, the box closes and nothing happens. The project manager is confusing and can cause major problems before you figure it out. Improvements include: The user interface is more Win95 compatible -- multiple selection, drag-n-drop, and copying all work well. The right mouse button pulls up a menu of useful things. Font support has been added! Text and labels can now be readable and take up a reasonably small space. Unfortunatly, this causes printing and redraw to take a small fraction of forever. Printing has improved significantly. Object attributing works a bit better. Text wildcard selection now works on attributes. Text can be imported from a file. In theory a WordPad box can be dropped right on the schematic, but this feature doesn’t work right. ============ A note on company bashing: While I realize it’s very difficult to produce software of this complexity without a few rough edges, I also realize that a company will get by with whatever it can. Marketing and engineering concerns to not always coincide. Viewlogic has to balance a lot of issues: Their PC products are less profitable (now) than their fully-blown (and very expensive) workstation products. However, as the functionality of their cheap products approaches that of their expensive ones, they feel a major squeeze. The tendancy is to try to support to more profitable market more, while just barely keeping up with the competition on the emerging cheaper market. This may work for a while, but as DEC and SUN (and even IBM) learned the hard way, if you resist the emerging market, you’ll find yourself struggling to catch up. I’m discouraged by this release of Workview Office. It appears that Viewlogic may be spread too thin and this product is suffering. While this may be understandable, it’s also understandable that the best recourse that I have is to complain. If enough people complain, especially in public forums, then perhaps they will listen and make some changes. Again, Viewdraw-Office would be a wonderful product if they would just put in the effort to clean up a few things and exercise some reasonable quality control. > > Now that Peter Alfke has come onto the scene, > the Xilinx bashing has all but stopped, and I think the group has > benefitted. Maybe someone from Viewlogic is reading... Or there could be another explanation. Silence on my part means that I’ve moved on to another product. Xilinx has some nice-looking new products that I would like to try, but unfortunately, I'm already knee deep in ORCA and haven't got too many complaints. Maybe someone from Viewlogic is reading...??Article: 3387
What is optimal? Area? Speed? Minimal route resources used?Article: 3388
In article <832784803snz@fpga.demon.co.uk>, david@fpga.demon.co.uk wrote: > > It has been a great tradition of this group over the last three > years to pour scorn on market leaders (i.e. Xilinx for devices and > Viewlogic for EDA). Now that Peter Alfke has come onto the scene, > the Xilinx bashing has all but stopped, and I think the group has > benefitted. Thank you very much for the kind words, I take them as a compliment, but I want to emphasize that I am not a spy or a cop. Xilinx never asked or appointed me to this newsgroup. I see myself as an information resource, a mentor or a teacher. I will not hesitate to speak out, instantly and frankly ( bluntly?) on silicon-related issues, because I understand them pretty well. I will be more cautious and slower to respond to development-system related issues, because they are far more complex, and they are not my specialty. Finally let me take this opportunity to cangratulate this group on maintaining a professional tone, avoiding the personal attacks, insults, four-letter words and other signs of immaturity that populate so many other newsgroups. It is a joy listening to you. And keep ventilating your gripes, even with Xilinx devices. Hard as we try, we are not perfect, yet :-) Peter Alfke, Xilinx ApplicationsArticle: 3389
John Cooley wrote: [...] > Also, like a fool, the night before the contest I thought I'd be a clever boy > by doing some last minute changes on the design problem. This meant changes > to the test vectors, too. When done, I egotistically thought: "Finished in > just a few hours doing it in both Verilog and VHDL! Damn, I'm good!" It > was during the opening part of the actual competition where I got to > personally relearn how God likes to enforce his "Pride Commith Before The > Fall" rule for people who suffer from occassional bouts of bigheadedness like > myself. I had just explained what the design problem and was showing the > contestants the template that they were to put their designs in (so they > could run in the testbench) when suddenly someone chirped up that the port > list for the template and the testbench instantiation of it were very > different. Yikes! I forgot to update the template lastnight! AAAAAAH! > So, I got to go through 40 highly embarassing minutes in front of 30 miffed > contestants and 80 or so wispering onlookers, as I nervously fix both the > Verilog and VHDL testbenches before we could officially start the contest. > (OK, God, I got the message!) [...] Did you really get the message? I tried to do the contest at home (hand-coding in Verilog), and I say you, test vectors and your ASCII art aren't conforming (especially for dstate and estate, and for output vector i). It took me 30 minutes to finish the original design (including guessing out of the test vectors what was really wanted), and 10 minutes for the post-ECO design (guessing and correcting both times took about 5 minutes). I don't have any synthesis tools at home, so I don't report any gate delay times. But IMHO the best results for finite state machines are obtained, if you code straight forward (using a Verilog case statement), and this was what I did. -- Bernd Paysan "Late answers are wrong answers!" http://www.informatik.tu-muenchen.de/~paysan/Article: 3390
Andy Gulliver wrote: > We are currently evaluating the new Aldec-based package from Xilinx > which is much cheaper and appears to have (a) much better schematic > capture than Viewlogic (b) the version we have includes VHDL *and* a > version of the Esperan Masterclass tutorial - oh yes, and it runs OK > under Win95 (It does have a couple of little bugs, though....) Is there any compatibility in between the Aldec-based design capture SW and the ViewLogic PRO series? If there *isn't*, then why is the Aldec package (in particular) so interesting? If you are going to re-capture in a new design environment, without any notion of preserving the specific design files (i.e. the design has to be re-entered), then all the options should be considered. *IF* this is the case (and I'm asking, not dictating from experience), then I would suggest that the new release of OrCad tools deserves a look. I've played with them for a couple of weeks, and I'm impressed (not a stockholder, employee, etc.). The tools are much more "professional" that their previous generations. Being native windows apps really helps. The tools run under W95, NT, and maybe even under W3.11 (with w32s). They look very polished, they seem to have good Xilinx (and others) support, and *the price is not so painful!* I've looked at the capture tool only. I haven't yet played with the simulator or the synthesis tools. If anyone else has some experience, please jump in... that's what this newsgroup is all about! I'm sure OrCad has a web page... yup, http://www.orcad.com If someone would follow up on the Aldec/ViewLogic design database interchange question, I think lots of us would appreciate it. Regards, Bob Elkind ************************************************************************** Bob Elkind email:eteam@aracnet.com CIS:72022,21 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ******** Video processing, R&D, ASIC, FPGA design consulting *************Article: 3391
PRESS RELEASE
05/21 1130 Fintronic extends Enhanced Cycle Simulation
and introduces novel code coverage tool
Menlo Park, CA (May 21, 1996) Fintronic USA, Inc. which recently
introduced the innovative Enhanced Cycle Simulation Technology
(ECST) to its line of EDA products, announces today that it has
successfully extended this ground-breaking technology to a wider
class of Verilog designs for which the cycle simulation paradigm
could not be used before. FinSim-ECS which supports the entire
Verilog HDL consists of FinSim, a full fledged Verilog simulator
and the ECS engine. FinSim-ECS automatically identifies the
parts of the circuit that are suitable for simulation on the ECS
engine and the rest is simulated by FinSim. Fintronic has im-
proved the ECS engine so that modules with full timing specifica-
tions as well as some RTL-level modules can be now simulated by
the ECS kernel without any change in the original Verilog code.
Fintronic has specifically made a point out of testing its new
technology on designs known in the industry for some time, such
as the CMU and the DA Solutions benchmarks, in order to prove
that this technology does not require a new design methodology.
``Our measurements show that by combining intelligent analysis of
the designs with fast ECST, FinSim-ECS is able to achieve on some
designs of the DA Solutions benchmark, speedups between 8 and 12
times over the performance of all Verilog software simulators re-
ported upon in 1995 by DA Solutions. Of course, given a circuit
designed to suit our cycle simulation paradigm, we would get 100
fold speedups, but the main point we want to emphasize is that
this technology applies also to existing benchmarks, without any
change in the designs`` says Dr Alec Stanculescu, president of
Fintronic USA.
In addition, John Hillawi, Managing Director of DA Solutions men-
tions: ``The new release of FinSim-ECS has produced an overall
speed up of x8-x12 and in one benchmark (Raynet) it has given as
much as x100, without changing the design of the benchmark''.
Fintronic also continued to fulfill its commitment to improve the
performance on the RTL-level designs by restructuring the front
end of the simulator to increase the scope of existing optimiza-
tions and integrate them with more advanced ones. Thus, compared
to FinSim 4.0 introduced at DAC 95, FinSim-ECS now shows up to
three times speedups for the CMU benchmarks, the popular bench-
marks for RTL-level.
Also today, Fintronic announces that it has added to its port-
folio of EDA tools FinCov, a fast code coverage product which
features a promising new technology. Whereas other code coverage
tools are provided by third party vendors and interact with the
simulation engine via the PLI interface, Fintronic's product is
tightly integrated with FinSim's kernel allowing therefore for
very fast data collection times. The users of FinCov will be able
to run far more test vectors in the same amount of time it now
takes them with PLI based code coverage tools. They will find out
sooner which part of their design is redundant and will result in
waste of silicon, which part has not been sufficiently tested or
which part is over-tested consuming valuable simulation cycles.
The announcements today reaffirm Fintronic's strong commitment to
provide the Verilog user community with accurate, powerful tools
which will ultimately minimize the turnaround time of the design
cycle and will substantially increase the productivity of our
customers.
Platform support:
FinSim features the highest platform versatility in the
industry by running on all popular platforms including UNIX for
SUN, SGI, HP, DEC and Sony NEWS, Windows NT, Windows 3.1, Windows
95 and Linux.
Third Party Integration:
FinSim is tightly integrated with third party graphical
environments such as SignalScan from Design Acceleration, Veri-
best from Veribest Inc., Ishizue from IK Technology, Undertow
from Veritools, and ECS from Data I/O.
Pricing and Availability:
Fintronic USA's FinSim simulator featuring high perfor-
mance Verilog Simulation is priced from $995 to $12,500 depending
on product configuration and platform, and is available now. It
is sold by Fintronic USA Inc., IK Technology, and Intergraph.
FinSim-ECS which includes both FinSim and the ECS kernel has a
list price between $20,000 and $25,000. The Verilog Analyzer from
Fintronic USA, is currently part of products sold by Intergraph,
Nextwave, ZyCAD, IST, IKT, and IKOS. FinCov will be available in
Q3 1996. Fintronic has a Web page at http://www.fintronic.com,
which can be used for placing orders, requesting demo licenses,
checking prices, etc. Fintronic provides hotline support and
software distribution via the Internet. For more information
contact Dr Alec Stanculescu, president, at (415) 325 4474/x105 or
e-mail him at alec@fintronic.com.
Mission:
Fintronic has a mission to supply the highest performance
Verilog HDL simulators available for full language design verifi-
cation and timing simulation. It is privately held and privately
funded.
Acknowledgments:
Fintronic USA, Inc. acknowledges trademarks or re-
gistered trademarks of other organizations for their respective
products and services. For further information on the DA Solu-
tions Benchmark Report, please contact DA Solutions at
info@dasl.compulink.co.uk or telephone John Hillawi at +44 1705
365 473.
Article: 3392In article <4o0jqn$7cl@nntp1.best.com>, sbaker@best.com writes: >For those interested in reconfigurable computing, >you will find a report on the FCCM (FPGAs in Custom Computing Machines) on the web at >-- and http://www.pldsite.com/features. Instead of this link, use http://www.pldsite.com/fccm/fccm96.htm >-- http://www.reconfig.com > __ _ | \ | | |__/ __ | _|_ | \ | | | | | \ |__| | | Rolf Engstrand PHONE: +46 8 7195779 CadLab (ÄL/EKA/N/SD) FAX: +46 8 7195319 Ericsson Components AB E-MAIL: Rolf.Engstrand@cubt.ericsson.se S-125 82 STOCKHOLM MEMO: EKA.EKARGE Sweden Location: Götalandsvägen 230Article: 3393
In article <1996May23.000947.2300@super.org>,
* Atmel FPGA Apps * <martin@atmel.com> wrote:
>
>>
>> Peter Alfke, Xilinx Applications wrote:
>>
>> I think you are right, there are only two types of devices, Atmel's and Xilinx
>> XC6200.
>>
>> Atmel's has internal 3-sate buffers, which means it cannot tolerate a random
>> bitstream.
>
>I would like to thank Peter for that constructive comment (NOT!). If it
>was worth the effort I would *FLAME* him for lowering the news group to
>the level of "commercial" attacks. Informing customers of available
>products is a valuble service that programmable logic vendors
>provide (I hope), but I would say that 'trashing' competitor products is
>not something that this newsgroup should stoop to - we (the vendors) can
>...
>Martin Mason
>Atmel Corp.
Dear Martin:
As far as I know this thread deals with evolvable hardware. In order to do
this, random bitstreams are generated and downloaded to an FPGA. With that
goal in mind, Peter is right in stating that the AT6000's tri-state buses
are problematic. He didn't attack the architecture per se, he merely said
that the Xilinx 6200 is probably better suited for evolvable hardware than
Atmel's 6000, because it only has unidirectional wires.
No need to feel attacked.
Cheers, Stefan (who has used CAL-1, CLi 6000, AT 6000, and XC6200)
--------------
Stefan H-M Ludwig mailto:ludwig@inf.ethz.ch
http://www-cs.inf.ethz.ch/~ludwig
Institute for Computer Systems
Swiss Federal Institute of Technology (ETH)
CH-8092 Zurich, Switzerland
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Article: 3394In article <319AA34C.7E0BCC04@pobox.com>, Jeffrey Ebert <ebert@pobox.com> wrote: > A guy asks for freeware/shareware and you're giving price quotes from US$ > 500-6000. Sheesh. > You still need place and route software to get to an LCA file and something > like makebits to get to a useable bitstream. Perhaps someone else knows of a > cheap/free way of doing the back-end stuff. Before you post, remember that > cheap in this context probably means cheap enough for hobby work. Not cheap > enough to get your boss to buy it for you. ;-) > Has anybody looked at the Motorola FPGA line? It seems to be a new product and the design software is available for downloading on the internet, or they will sell you a CD rom for $13 if you don't want to download 14 megabytes. They apparently have an evaulation kit to get you started though I haven't called them to see what it costs. They are at http://design-net.com/fpga Dan Schultz schultz@cddis.gsfc.nasa.govArticle: 3395
In article <319AA34C.7E0BCC04@pobox.com>, Jeffrey Ebert <ebert@pobox.com> wrote: > A guy asks for freeware/shareware and you're giving price quotes from US$ > 500-6000. Sheesh. > You still need place and route software to get to an LCA file and something > like makebits to get to a useable bitstream. Perhaps someone else knows of a > cheap/free way of doing the back-end stuff. Before you post, remember that > cheap in this context probably means cheap enough for hobby work. Not cheap > enough to get your boss to buy it for you. ;-) > Has anybody looked at the Motorola FPGA line? It seems to be a new product and the design software is available for downloading on the internet, or they will sell you a CD rom for $13 if you don't want to download 14 megabytes. They apparently have an evaulation kit to get you started though I haven't called them to see what it costs. They are at http://design-net.com/fpga Dan Schultz schultz@cddis.gsfc.nasa.govArticle: 3396
Bob Elkind wrote: [cut] > Is there any compatibility in between the Aldec-based design capture > SW and the ViewLogic PRO series? If there *isn't*, then why is the > Aldec package (in particular) so interesting? If you are going to > re-capture in a new design environment, without any notion of > preserving the specific design files (i.e. the design has to be > re-entered), then all the options should be considered. As it happens, the Aldec-based system includes a facility to translate older Viewlogic schematics (not sure about PROseries - we've not been able to use it yet). Some user interaction is needed to complete the process, but on the design we're using for evaluation the process seems relatively smooth. This facility allows us to continue maintaining the last 4 years of Xilinx designs and is a plus point for the new s/w. -- Regards AndyGArticle: 3397
Dr Edmund Lai wrote: > > I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series > software tools. We are having a lot of problems with ProCapture and > Prosim running under Windows 95 in a Pentium machine with 16Mb RAM. > > The "add-component" window of ProCapture has to be turned off. > Otherwise the system will crash. Also, we cannot get Prosim running > at all. Even under Windows 3.11, 16 MB of RAM is not enough if you want to use ProSim with a medium size schematic with many simulation vectors. Patrick.Article: 3398
Felix, As I recall, some synthesizers don't require you to explicitly code your FSM using one-hots; you can tell the synthesizer to implement the FSM in one-hots. Then, you get the real point of any HDL: - your code reflects the functionality required, but doesn't dictate the implemenation. - the synthesis tool chooses the best implementation, under your guidance. Exemplar, at least, could do this. I recall Compass being able to do it, and I would be shocked if Synopsys couldn't. Erik JessenArticle: 3399
In article <1996May23.000947.2300@super.org>, * Atmel FPGA Apps * <martin@atmel.com> wrote: > I would like to thank Peter for that constructive comment (NOT!). If it > was worth the effort I would *FLAME* him for lowering the news group to > the level of "commercial" attacks. Newsgroup volatility. At first, I got very upset about this accusation. I am trying very hard to avoid contaminating this newsgroup with marketing hype or negativism. But then I realized that Martin Mason simply doesn¹t know what he is talking about. His diatribe just shows how volatile the internet can be: 1. Jim Toerresen asked for advice on a highly esoteric subject: a way to program FPGAs with random bitstreams, then changing these bitstreams randomly, then selecting the best one, adding more random changes, thus emulating Mutation and Selective Breeding and the ³Origin of Species². I know that one researcher in England had made successful experiments, using XC6200 devices. 2. I e-mailed Jim what I knew, and I added that Atmel FPGAs have 3-state buffers, and do not tolerate random bitstreams. That was a simple helpful explanation of an undisputable fact. I would also have explained this honestly if Atmel were applicable, and Xilinx were not. I am an engineer, not a whore. Because of the highly exotic subject, and because I had to mention something ³negative² about a competitor, I did not post this to the group, but rather e-mailed it to Jim directly. 3. Jim then posted every response he had got, including personal remarks and jokes, to this newsgroup. That was not very smart, but a researcher in pristine Trondhjem, a beautiful place in majestic Norway (I¹ve been there), may not understand the paranoia and the persecution complexes rampant in this overheated incestuous Silicon Valley. Jim, you are forgiven, but you did light the match that set the barn on fire. 4. Martin Mason of Atmel reads that posting, obviously doesn¹t have an inkling of the subject being discussed, but rushes to the defense of his company and flames me. Martin, 3-state buffers driving Longline are good, almost all Xilinx devices have them also. But any device used in the particular highly exotic application discussed here, must tolerate a random bitstream, and should therefore never have the possibility of contention. That excludes the Atmel devices from this one, commercially insignificant application. The lesson we should all learn is how volatile a newsgroup can be. One frank personal e-mail, one careless posting, one ignorant and temperamental response, and we get mayhem. I am glad this is the rare exception. This has been a very civilized newsgroup, and I hope it remains so. Peter Alfke, Xilinx Applications.
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