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> I've been using Viewdraw-Office now for a couple of weeks and have the >following humble opinion: They've added more rough edges and taken away >some really useful stuff. Primarily: [snip] Speaking as a Viewlogic/Xilinx (old 1991 DOS version!) user, it seems that you list half of the bits which make a productive program. In particular, the removal of some command line functions is typical "Windows application" stupidity. Command line entry is very useful; in fact this is often the fastest way to do things. Peter.Article: 3401
I missed the original post but Emulation Technology (sold in the UK by Trace Technology) sell lots of different FPGA sockets.Article: 3402
Hello, I have a board (a PC card) with 32 XC3064A (TQ144 package) devices, loaded serially (CCLK+DATA) and all 32 simultaneously. Each contains an identical circuit, basically a very slow but complex pulse counting function. Only a few pins on each FPGA are actually used; the rest are unconfigured so they use the internal pullup. It is a 6-layer (2 planes, VCC+GND) board, with plenty of decoupling (four 100nF multilayers per device), attention to noise, overshoots, long tracks driven via resistors with optional RC terminations at far end, i.e. the absolute business. When I originally I did this design 3 years ago, I loaded the 32 devices in series, i.e. the data file has 32 copies of the data. This should of course work, but the load-up failed about 90% of the time. The D/P remained low. I spent weeks on it with a 300MHz scope and a logic analyser, and by tweaking the CCLK driver (74HC244) and with auto retry in the load-up code, I was able to deliver it to the customer. (This was a 4-layer board, using XC3064, PLCC84 package). I also had to break the 32-long chain into two, i.e. load each group of 16 devices in series. I do all the proper reset things, using a dedicated reset controller. All 32 devices get reset while D/P=0, both while VCC rises, and again with a 10ms pulse afterwards. IOW - everything possible. I even repeat this reset sequence 100 times (it is software controllable). Anyway, this time round, I decided to do everything possible, regardless of cost, to avoid the same problem. But it is just the same. With say 8 devices it loads fine. With 16 it never loads. Fortunately, because the "A" devices do some frame checking on the config stream, at least if the config fails I don't get any devices trying to fry themselves - a favourite with the old design. Small consolation. I spoke extensively to everyone I could get hold of at Xilinx, in 1993 and also since during the design of the 2nd version, and no-one had any clue what the problem might have been, or how to avoid it for next time. It is fairly obvious to me that these devices are extremely sensitive to *something* on the CCLK/DATA lines, but what? Xilinx have no idea. The documentation (which I have read MANY times, forwards/backwards) says no thing about this. And is it obviously impossible to achieve a textbook-perfect waveform on CCLK at every point on a board with 32 144-pin devices. I have a 250MHz scope, which shows nothing out of the ordinary. (FYI - there is a 33rd FPGA on the board, a 3030A, which does some simple timing functions, and this is loaded in parallel with software doing I/O writes to the ISA bus. The serial CCLK/DATA outputs from this are buffered with a HC244, then go via 33R resistors to the 32 3064s in parallel. The 3030 never has any problems loading-up.) Does anyone know any "secrets"? I have done many Xilinx designs but always with just one device, except this design. Any help is much appreciated. I have to deliver this by the 29th! Peter.Article: 3403
I've forwarded the following posting from comp.lsi.cad to comp.arch.fpga. Morteza Saheb Zamani wrote: > > Hi, > > I get a strange error message from the Floorplanner: > > I have a simple 4-bit adder design with a carry-look-ahead > circuit. When I specify a constraint by using Assign icon (give an > area of 7-by-7 for the CLA circuit) it works OK (i.e. it passes the > floorplan check and places and routes). However, if I save this > constraint to a file and read it again, it gives error (it says > "potential error in LOCs or constraints"), and cannot pass the > floorplan check. FPLAN.LOG also says: "Cannot place symbol x on block > y because it is occupied". > > In another try, I removed all the files (except my xnf files and the > cst file. After mapping, reading the constraint file gives the same > error message. > > Does anyone know what the problem is? Please let me know if you would like > to try it and I will send you the .xnf files and the .cst file. > > Regards, > Morteza > > ____________________________________________________________ > Morteza Saheb Zamani E-mail: morteza@vast.unsw.edu.au > VaST Lab, > School of Computer Sc. & Eng. > University of N.S.W. Phone: +61 2 385-4898 > Sydney, 2052, AUSTRALIA FAX: +61 2 385-5995 > ____________________________________________________________ ************************************************************************** Bob Elkind email:eteam@aracnet.com CIS:72022,21 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ******** Video processing, R&D, ASIC, FPGA design consulting *************Article: 3404
jtconnor@trog.dra.hmg.gb wrote: > > Can anyone comment on the usefulnes of mentor's system architect in *real* > designs? We are just about to trial it and would appreciate anyones > feedback. Are there any others which you would recommend (or keep well > clear of?) > > Thanks, > > Jon. Jon, I can tell you that over 800 copies of System Architect have been sold, and that everything from 4,000 gate FPGA designs to over 500K gate ASIC designs have been designed with the tool. Give me a call if you'd like more references. Daniel 503/685-1310Article: 3405
Peter wrote: > It is fairly obvious to me that these devices are extremely sensitive > to *something* on the CCLK/DATA lines, but what? OK, I'll grab at a few straws and mention some things you've probably already thought about. Since Murphy knows you are watching the CCLK and DIN lines like a hawk, have you checked to make sure the Reset and Prog lines don't bounce? A little glitch on reset or Prog could mess things up. Also, with HC driving 32 loads and a long wire, is there a chance your rise/fall times are excessive (don't remember if there is a spec on this, but I've seen very pretty trapezoidal signals that raised he** with logic). Are you sure all INITs are high before starting configuration? Some less probable causes: Make sure CCLK never sits low for more than 5us, the configuration logic is dynamic. (This shouldn't change with device count though). Make sure mode lines are stable around reset. Insultingly simple and very unlikely (these are the ones that get me): Is there glitch on VCC as all devices come out of configuration simultaneously? Thay may have configured correctly but glitched themselves just after finishing. Check PowerDwn pins. If you are providing the clock and data from proprietary hardware, is the CCLK polarity correct? Let us all know if you figure it out. Try to have at least a little fun this weekend! Good luck, ScottArticle: 3406
Dear Friends, Since I posted the "impossible optimal synthesis of FSM", I read some related documents and user's guides. I found that I might have misunderstanding toward VHDL synthesizers. They should be good in synthesizing FSMs with state encoded in one-hot. The reason is that, according to Exemplar's reference manual, Exemplar codes each state name a constant vector. The vector has only one bit '1' and other bits don't care. For example, when I define 5 one-hot states and name them S0, S1, S2, S3, S4. Exemplar codes them "----1","---1-","--1--","-1----","1-----". Since all logic operated on don't care "should be optimized out" by synthesizers, the comparison statement like when state=S0 will end up with a single bit logic rather than a vector-wide logics. I have known more about VHDL synthesizers now. I'd like to hear any comment from you. Best wishes, Regards, Felix K.C. CHEN -- --------------------------------- Felix, Kuan-chih CHEN (³¯ «a §Ó) Associate Project Manager System Product Division D-Link Co., Hsin-chu, Taiwan Email: flxchen@diig.dlink.com.tw Machines and tools are only as good as the people who use it. ---------------------------------Article: 3407
Scott, I should add to my last message that the rising edge of CCLK (the one which clocks-in the DIN data) is absolutely textbook-perfect from 0V to +4V, and this takes about 2-3ns. This is with the HC244 driving via 33R, and is measured on the actual FPGA pin(s). So I suspect the problem is elsewhere entirely. But the most curious thing is that it is virtually the same as on the 1993 board, but the two were very different: 1993: 4-layer (GND plane, no VCC plane), using PLCC84 devices, not much decoupling, 16 3064s on main board and 16 on a daughter board, with metal pillars and cables joining the two. 1996: 6-layer (GND,VCC planes), using TQ144 devices, tons of decoupling, all 32 devices on one side of the board, about 5mm apart. The odd thing I have just found is this: the 3030 "control device" is visibly up and running (it is outputting various clocks which go to the other 32 3064s) some 2ms before D/P gets released. This is even though both /INIT and D/P are wire-ored between all 33 devices! One of these clocks is 16MHz, and maybe this is interfering with the config. I will work on this, but how can a FPGA be up & running while D/P is still held low? With about half the devices at any one time (exactly which ones varies) HDC remains HIGH, as if some were not receiving config data. Peter.Article: 3408
"pa" == Peter Alfke <peter@xilinx.com> writes:
In article <peter-2405961004280001@appsmac-1.xilinx.com> peter@xilinx.com (Peter Alfke) writes:
> 2. I e-mailed Jim what I knew, and I added that Atmel FPGAs have 3-state
> buffers, and do not tolerate random bitstreams. That was a simple helpful
> explanation of an undisputable fact. I would also have explained this
> honestly if Atmel were applicable, and Xilinx were not. I am an engineer,
> not a whore.
I appreciated your helpful answer and clarifying the differences between
the devices from Atmel and Xilinx.
> 3. Jim then posted every response he had got, including personal remarks
> and jokes, to this newsgroup. That was not very smart, but a researcher in
> pristine Trondhjem, a beautiful place in majestic Norway (I¹ve been
> there), may not understand the paranoia and the persecution complexes
> rampant in this overheated incestuous Silicon Valley. Jim, you are
> forgiven, but you did light the match that set the barn on fire.
I feel sorry about blaming about this and that and would certainly not have
posted Peters email when I see the discussion afterward. However, I have to
remind on that I actually wrote in my request:
> Please email me as soon as possible and I will summarize to this newsgroup.
> 4. Martin Mason of Atmel reads that posting, obviously doesn¹t have an
> inkling of the subject being discussed, but rushes to the defense of his
> company and flames me.
I think this reaction was highly over-reacting. How should developers be
able to pick the right devices if none in the business are allowed to tell
their knowledge about others devices.
Anyway, if any of you have become interested in making deviced better
suited for evolution (both the Atmel and Xilinx devices are not THE
evolvable chip) this thread hasn't been for nothing.
-Jim
--
Jim Toerresen # E-mail: jimtoer@idt.unit.no
Dept. of Computer Systems and Telematics # Tel: +47-73594458 (office)
The Norwegian Institute of Technology # Tel: +47-73886676 (home)
N-7034 Trondheim, NORWAY # Fax: +47-73594466 (office)
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% The world is like a book, and if you never %
% leave home you only read one page. %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Article: 3409John Abt wrote: > > a little off the subject, but... > > > As an aside, I am amazed that Xilinx would have made the CCLK edges so > > incredibly critical, given that being able to configure the thing is > > obviously rather important. I know lots of people who won't touch > > Xilinx, they just say (usually without any knowledge of Xilinx parts) > > "configuring them is too dicey". It is this perception which causes > > many people to slave for days/weeks on endless ASIC-type simulations > > designing OTP parts from Actel etc because one gets only one shot at > > it. > > ...this is something that has always puzzled me a bit. Given that > the cost of one OTP part, on a rough average, is probably equal to > about a half hours worth of engineer time, why spend 20 times more > than that to make sure it's right? At some point it's more efficient > to just burn a part or two, or ten, and get the thing done. I do it > all the time. And another thing: this is of course a factor only at > the development stage; why burden production, esp. high volume, > with something that's really a development convenience? (Unless > of course you need the reconfigure function). When's the last time you were able to unsolder a TQ176 or BGA from a board, burn a new part and replace it on the board in 30 mins, especially without destroying the board!? The Xilinx parts (Altera SRAM FPGAs and Motorola/Pilkington parts) also allow you to make changes to existing product to add or change features after you've gone to production, such as when your LCD manufacturer obsoletes a panel and the only suitable replacement has inverted clocks and slightly skewed timing. Why burden production with having to program one-time devices before placing them on the board? In all of my designs the configuration is done from the same Flash EEPROM that runs the system. Only one device has to be programmed to configure all FPGAs and feed the CPU (and that part is programmed on the board by the PCB tester). At my burden rate and production volume, off board programming of TQFP packages is more than $4 (this doesn't include capital expenditures for the programmer and adapter sockets or damaged goods). Some OTP FPGAs (Lattice ISP) can be programmed on the board without much hassle. In safety critical systems I'd go with either anti-fuse (configuration can't be upset) or SRAM technology (configuration can be verified). EPROM based FPGAs (many of which copy the EPROM configuration to SRAM at powerup) are a bit more problematic because the configuration can be upset but not verified. Regards, Scott (A Xilinx User :)Article: 3410
John, The problem really appears only if you are using a fine-pitch SMT part i.e. it cannot be prototyped without some weird socket arrangements, and you are also going straight to a PCB. Often, the second follows from the 1st. My particular board simply could not have been prototyped. There are some 5000 pins. You would spend $1000s on TQ144 zif sockets, then be wire-wrapping it for days, then days/weeks more looking for the wiring errors. And, even with a PTH/ground plane w/wrap board, the prototype (about 2 sq. feet of it) would not prove much relative to the final PCB. If one is using a part which can go into a socket on the *same* PCB footprint (e.g. DIP, or any of the PLCC devices) then the OTP parts are fine. One firm (Altera?) even offers to take back the first 100 programmed parts for a 100% refund! Peter.Article: 3411
Zoltan Kocsi wrote: > > Are there any (not free) tools that one can run on a PC without any > flavour of Windows (leaving DOS or even better Linux) to do FPGA designs ? > Preferably some HDL -> downloadable bitstream tool set. I don't recommend it, but you can use the Xilinx tools of the previous generation (version 5.2), plus OrCad version 4.x. The Xilinx 5.2 tools are pretty solid. You're much better off with the current (Windows-based) release of OrCad's schematic capture (etc.) program. In my humble opinion, of course :=) I'm sure there are other solutions, as well. Good luck to you, Bob Elkind ************************************************************************** Bob Elkind email:eteam@aracnet.com CIS:72022,21 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ******** Video processing, R&D, ASIC, FPGA design consulting *************Article: 3412
-- < Oleg A. Kamaletdinov > < "RASTR" Television research company > < Novgorod > < phone (816)29-166 > < fax (816)24-110 > < rastr@lan.novsu.ac.ru >Article: 3413
> I know lots of people who won't touch Xilinx, they just say > (usually without any knowledge of Xilinx parts) > "configuring them is too dicey". It is this perception which causes > many people to slave for days/weeks on endless ASIC-type simulations > designing OTP parts from Actel etc because one gets only one shot > at it. > Peter. Peter, I am a satisfied Actel user and I just wish to set the record straight... Fully simulating a design before going to silicon is not a bad thing - even if the chip is fully configurable! My main concern in doing an FPGA is cost. Time spent in the lab debugging a half- baked design costs a lot more than doing some simulation ahead of time. Also, I don't feel that I have to simulate a chip to death for 7 months before programming it: if a few minor things get past me, it may cost me a $50-$100(CND) to burn a new chip but that is not prohibitive. After all, this is a one time cost, incurred only during prototyping. Once in production, OTP parts are a lot cheaper to buy than SRAM based chips. And since I don't need in-service reconfigurability, I cannot justify the extra unit cost of the SRAM based chips. So let it be known that there are reasons for using anti-fuse based devices other than ignorance about Xilinx programming procedures! Catherine Gyselinck ---------------------------- MPB Technologies | Speak softly but carry | gcat@dorval.mpbtech.qc.ca | a +6 two-handed sword | tel: (514) 683-1490 ---------------------------- fax: (514) 683-1727Article: 3414
flxchen@diig.dlink.com.tw (Felix K.C. CHEN) wrote: ... > >I do not expect that any Synthesizer can reduce the state operation >from vector to bit-wise. well, thanks the high level description >language that we can avoid the explicit assignment of state bits, >but there is a big bill to pay! > >Any comment will be appreciated. Felix, For at least one synthesizer/optimizer (compass) you can choose the encoding method: Designer Defined, One Hot, or let the system choose. This can be done on a per-machine basis via compiler directive comments in the code. I have looked at the output of the optimizer in some other situations, and it does a reasonably good job at removing redundancies., particularly of the type you mention. I don't know how it would fair with a 17 state machine encoded with 5 bits with the "extra " states considered as don't cares. If I have some time I'll give it a try on Tuesday. Later, JD John E. DeRoo, Marlborough, MA. Chairman's Rule #3: People who j.deroo@ieee.org *don't* play with fire are the http://www.ultranet.com/~deroo/ ones who end up getting burnedArticle: 3415
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schultz@cddis.gsfc.nasa, Dan Schultz wrote: > > In article <319AA34C.7E0BCC04@pobox.com>, Jeffrey Ebert <ebert@pobox.com> wrote: > > > A guy asks for freeware/shareware and you're giving price quotes from US$ > > 500-6000. Sheesh. > > > You still need place and route software to get to an LCA file and something > > like makebits to get to a useable bitstream. Perhaps someone else knows of a > > cheap/free way of doing the back-end stuff. Before you post, remember that > > cheap in this context probably means cheap enough for hobby work. Not cheap > > enough to get your boss to buy it for you. ;-) > > > > Has anybody looked at the Motorola FPGA line? It seems to be a new product > and the design software is available for downloading on the internet, or > they will sell you a CD rom for $13 if you don't want to download 14 megabytes. > They apparently have an evaulation kit to get you started though I haven't > called them to see what it costs. They are at http://design-net.com/fpga > > Dan Schultz > schultz@cddis.gsfc.nasa.gov I've watched the progress of the pilkington fpga's (which are now in the market as motorola MPA devices) since over a year now. It seems that motorola now can realy deliver devices, at least the have them now in their price list and I got an offer from a motorola distributor. The free software is a place and route tool only, without a frontend. it reads edif netlist input. capilano has a demo of their schematic capture an simulation tool which works with the motorola system. I played a little with it and it does work. you cannot save your schemtaic but you can export the netlist and compile it. As soon as i get my samples from motorola I'll try a small design. It should be easy to write a C or C++ program to create simple designs without a schemtaic entry tool. As motorola has some example libraries maybe they give some documentation for free. They export backannotoatin in several formats, including vhdl. I never used the alliance package (free vhdl synthesis + simulation, runs on linux) but maybe the time has come to complement free vhdl with free place and route. btw, prices found on the motorola web site are approx US$ 35 for the MPA1016 (available now ?) and US$ 72 for the MPA1036 (available NOW :=) ) (Unfortunately my distributors prices are about twice as high and minimum quantity is 15 pieces ... ) If some people in germany are interested in samples I'd orginize to collect the 15 pieces) Andreas -------------------------------------------------------- Andreas Kugel Chair of Computer Science V Phone:(49)621-292-5755 University of Mannheim Fax:(49)621-292-5756 A5 D-68131 Mannheim Germany e-mail:kugel@mp-sun1.informatik.uni-mannheim.de --------------------------------------------------------Article: 3417
>>>>> "P" == Peter <ft63@dial.pipex.com> writes:
P> The odd thing I have just found is this: the 3030 "control device" is
P> visibly up and running (it is outputting various clocks which go to
P> the other 32 3064s) some 2ms before D/P gets released. This is even
P> though both /INIT and D/P are wire-ored between all 33 devices! One of
P> these clocks is 16MHz, and maybe this is interfering with the config.
P> I will work on this, but how can a FPGA be up & running while D/P is
P> still held low?
This is odd, and should be looked into. But remember that you can
program the point were D/P changes - Before or After outputs go
active. This is all described in the databook.
You said that the 3030 was the device driving CCLK. Thus - this
device has to start before the other devices, otherwise they will not
be configured (no CCLK).
If you are using a serial PROM of some kind, make really sure it
doesn't start clocking out data before the devices are ready to
receive data. If this happens, you could lose the start of the
bitstream, and the devices would not configure properly.
Hope this can be of help.
--
Torbjorn Bakke (tb@vingmed.no) Tel: +47 33 04 21 32
Article: 3418
Felix K.C. CHEN (flxchen@diig.dlink.com.tw) wrote:
: Dear Friends,
: I might be wrong but I believe that no synthesizer can optimize
: finte state machine (in VHDL) today!
There's one-hot and there's one-hot. You have to be very careful about
what you mean when you use the term one-hot.
I have only experienced synthesis with synopsys. These are my thoughts.
You can have all your state vectors encoded such that only 1 bit is set in any
state, thus:
constant S0 : std_logic_vector(3 downto 0) := "0001";
constant S1 : std_logic_vector(3 downto 0) := "0010";
constant S2 : std_logic_vector(3 downto 0) := "0100";
constant S3 : std_logic_vector(3 downto 0) := "1000";
However, if you use a case statement for the state transitions, as in:
case state_vector is
when S0 => ....
when S1 => ....
end case;
then you are correct in indicating that a synthesizer will decode the entire
state vector. This is not one-hot encoding as far as I am concerned. It is merely
one of many different ways in which the state vectors can be assigned.
With synopsys, it is possible to extract the FSM and then get synopsys to re-synthesys
with suitable directives to indicate that the state-vector should be decoded on a
per-bit basis and not on a per vector basis. This then does give you a true one-hot
encoded state-machine in that only 1 bit is used to decode the state. This methodology
is a pain because requires the FSM to be extracted from the design and resynthised.
I have seen it work but it just strikes me as being inefficient to have to synthesize
twice. Perhaps some others can comment on their experiences of fsm_extract.
It is possible to write the VHDL in such a way that true one-hot encoding will be
synthesized first time. It does have the advantage that you get what you want
first time, but it has the disadvantage of not being flexible in terms of supporting
different state-vector encoding styles.
process
begin
wait until sysclk'EVENT and sysclk='1';
if Nreset = '0' then
state_vector <= "00001";
else
-- Action for S0 --
if state_vector(0) = '1' then
..
end if;
if state_vector(1) = '1' then
..
end if;
...
end process;
Andrew
library usual;
use usual.disclaimers.all;
Article: 3419On 23 May 1996 15:55:08 GMT, husby@fnal.gov (Don Husby) wrote: >david@fpga.demon.co.uk wrote: > I've been using Viewdraw-Office now for a couple of weeks and have the >following humble opinion: They've added more rough edges and taken away >some really useful stuff. Primarily: > -- snip You gave an excellent summary of the product. I can only assume that no one at Viewlogic actually uses it. The text origin problem alone is enough to drive one to drink!! In fact its almost quicker to copy/paste/edit text with the desired orientation than it is to create new text then go back and set the desired orientation. > If enough people complain, especially in public forums, > then perhaps they will listen and make some changes. Again, Viewdraw-Office > would be a wonderful product if they would just put in the effort to clean up > a few things and exercise some reasonable quality control. Maybe you're right I have sent several e-mail's to senior staff members at Viewlogic detailing the deficiencies and cumbersome aspects of their UI and I havn't even had the courtesy of a reply! So perhaps the answer is to bring this into this public forum. -- AlanArticle: 3420
Hi, I'm trying to create a ROM (2x32) with the memgen of Xact 6.0. After inserting parttype 4010pq160-3 and editing the memorydata the output states parttype 4005pg156, width 0 and depth0. And prosim doesn't recognize the created ROM symbol. Anyone experienced with the memgen ? Thanks in advance ! Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3421
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Article: 3422
In article <31A424E2.6756@crossprod.co.uk>
andy.gulliver@crossprod.co.uk "Andy Gulliver" writes:
"David Pashley wrote:
"[cut]
">
"> These are the facts. Please beware of comparing the latest from
"> "Vendor A" with something historical of unspecified product name or
"> version from "Vendor B".
"
"Ah yes, but whilst Viewlogic are shipping PROseries 6.1, Xilinx are
"*still* shipping 6.0 - which is what we are stuck with with our XACT
"system. Xilinx are well aware of the problem, but seem unable/unwilling
"to help beyond suggesting using Windows 3.11 - not very practical in
"most cases :-(
"<snip>
If Xilinx choose to ship a very old Viewlogic product which predates
Windows 95, then, as you say, it's not Viewlogic's fault when it
doesn't work. The new Workview Office products, as other posters
confirm, work well under Windows 95 / NT.
The "rough edges" referred to by recent reviewers here apply to any
newly released product. I imagine that they looked at the first cut
version (7.0) rather than later versions with the rough edges
smoothed. The current release version of the Viewlogic product is, I
believe, 7.11.
Again, I urge posters to state the version number of the s/w they
are discussing.
--
David Pashley
Article: 3423In article <31a61722.25131098@news.dial.pipex.com>, ft63@dial.pipex.com (Peter) wrote: > Hello, > > I have a board (a PC card) with 32 XC3064A (TQ144 package) devices, > loaded serially (CCLK+DATA) and all 32 simultaneously. Each contains > an identical circuit, > > When I originally I did this design 3 years ago, I loaded the 32 > devices in series, i.e. the data file has 32 copies of the data. This > should of course work, but the load-up failed about 90% of the time. > The D/P remained low. > etc Peter, I am sorry that you have had, and apparently still have, problems with configuration. I could not find your e-mail address, and I could not find your name in our hotline database, otherwise I would have contacted you directly. I see that you already got excellent advice from some experienced users. In Xilinx, I am one of the two people who are the final resource for resolving strange hardware problems being reported from the field. I have never heard about your particular design. I have a very simple attitude: The Xilinx configuration process is a deterministic digital operation; it has to work 100% of the time, not 90%, not 99%, not 99.9%, but 100%. I would not be satisfied with anything less, and neither should you. Xilinx has made some 50 million parts, used in - my guess - far more than 100,000 designs. That means billions of successful configurations. If configuration were a game of chance, Xilinx would be out of business. We obviously aren't. I have helped many customers achieve successful and reliable configuration. To the best of my recollection, we have never left a co-operative customer hanging with an unresolved configuration problem, so I feel pretty certain that your design can also be made to configure 100% of the time. I have written three app notes on the subject : Configuration guidelines ( 8 pages) Configuring mixed daisy chains ( 2 pages ) Dynamic Reconfiguration ( 2 pages ). I could fax them to you, or you can call me at 408-879-5091, or e-mail at peter@xilinx.com. By the way, I still don't really understand your clock and data structure. If all 32 configurations are identical, then you can hook all DIN in parallel,make one device the master, all others serial slaves. But you must hook all INITs together. And you must keep CCLK clean ( High ) until the beginning of configuration. And DOUT is the best trouble-shooting point. Don't assume that all simple circuits power up cleanly, don't assume that CPLDs power up instantaneously ( many don't ), so there are many chances for a mistake when you use unconventional methods. Obviously, you must be careful with glitches on CCLK, both on the rising and the falling edge. I have seen more problems with overly fast rise times than with slow ones. Rest assured, your circuit can be made to work. Greetings Peter Alfke, Xilinx ApplicationsArticle: 3424
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