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I am currently designing a data-acquisition system, 10-15k gates. I am designing for Xilinx 5200 family but have recently been recommended Atmel devices, particularly the AT6010. I use Viewlogic, tied to Xilinx, and so would need to spend some cash to convert to Atmel. Has anyone any info on the benefits, or not, of either device. I am particularly interested in Readback / checkback and device sizes. Thanks (responses can be posted here, or e-mail robert@imc4.eej.ulst.ac.uk)Article: 3201
Anyone else busy with implementing PCI interfaces in FPGA's ? Or am I the only newsreader busy with it at the moment ? :( Regards, Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 3202
(...Stuff about FPGAs and CPUs working together deleted...) I agree that a 400 MHz Alpha is able to get a lot of work done in a short time. But the problem is the memory interface. When you start getting cache misses, performance drops dramatically. Lots of folks are optimistic about using FPGAs as coprocessors. I see them complementing instruction set CPUs, particularly doing data-intensive jobs that choke cache-dependent IS CPUs. I don't believe that FPGAs will beat traditional CPUs on their own turf -- at least not for a few years. -- Steve -- 4/24/96Article: 3203
Scott Kroeger <scott.kroeger@mei.com> wrote: > The FPGA belongs on the CPU die. For those who are interested in one version of how this can be accomplished, I suggest you read the paper from Razdan and Smith in Micro-27. http://www.eecs.harvard.edu/~hube/papers/micro94.ps -- - Kee kee@eecs.harvard.eduArticle: 3204
Felix K.C. CHEN wrote: > > Dear friends, > > people always talk about "prototyping ASIC" with FPGA(s). But at least > in my case, due to the uncertainty of market, ASIC solution is not > possible at the moment. I have to find FPGA device whose gate count > is about 20000 (at real utilization) and whose price is relative > low to make the final product competitive. We are happy with AT&T ORCA series. 40k and 25k gates solutions are "quite" expensive, but if your design could fit in a couple of 10k gates or 12k gates, your FPGA cost would be low. Patrick.Article: 3205
I am looking for a way to implement a SIS output in XILINX
implementation.
SIS output in blif, pds format. If anyone knows how to convert these
output to xnf please respond. XACT have a conversion program that is
suppose to convert .pds to .pld format but I haven't had much success
with it and online help at XILINX doesn't have any useful information
on the subject. THANK YOU in advance.
--
Joe aka. Varin Udompanyanan
x(
vjoe@engrhub.ucsb.edu | http://www.engineering.ucsb.edu/~vjoe
:%
GRRrrr...
8b
Article: 3206
>Scott Kroeger (scott.kroeger@mei.com) wrote:
>
>: The FPGA belongs on the CPU die. Once there it gets "free" use of much
>: of the CPU's facilities (registers, cache, memory interface etc).
>: This should allow the FPGA to achieve performance improvements over
>: the CPU for operations too wierd to be contemplated in the normal
>: instruction set. For example, think how easy it would be to
>: rewire an ALU to perform CRC.
Graeme Gill <graeme@wallaby.digideas.com.au> wrote:
>Hmm. Ever thought about how such a chip is going to switch context ?
>(Similar problems confront programable instruction sets.)
> Graeme Gill.
No doubt that much state can be a problem. But with an efficient
configuration encoding, the configuration size doesn't have to be much
greater than the capacity of a typical L1 cache. With reasonable
bandwidth for loading configurations, it won't take much more time to
reload the configuration state than it does to fill up an L1 cache
when a process is brought in, and no one worries about that.
Depending on the exact architecture, there is usually much less
`data' state in the gate array that has to be saved at a context
switch. For example, Razdan & Smith's PRISC architecture had NO
data state in its programmable function unit.
There's lots of other issues too, but I don't think there are any
that can't be resolved. My view of the big picture pretty much
agrees with the others who have posted to this thread ---
a reconfigurable coprocessor will be useful for general purpose
computing when it is on the CPU die, and then it will only
be used for the things that it excels at; there will be other coprocessors
(vector, VLIW, ???) to perform computation that maps better to them.
Side note: the MATRIX architecture from MIT is interesting in that
it should be able to perform computation using any of these paradigms
(coarse-grain FPGA, vector, or VLIW) fairly efficiently.
Plug mode on: for those of you who haven't found it already, the
BRASS (Berkeley Reconfigurable Architectures, Systems, and Software)
Research Group's page is now up at
http://www.cs.berkeley.edu/projects/brass/
There isn't a whole lot there yet, but we'll be adding to it as
work progresses.
--Tim
--
------------------------------------------------------------------------
Tim Callahan 441 Soda Hall, (510) 643-8229
timothyc@cs.Berkeley.EDU http://www.icsi.berkeley.edu/~timothyc/
------------------------------------------------------------------------
Article: 3207> Let me try it again... > > Does anyone know where (or if) I can get ECL or PECL (preferrable) gate > arrays or FPGAs? I'm trying to design a high-speed (100 MHz) crossbar > switch and I need some way to build multiple multi-bit 16-1 MUXs. I've > looked at Lattice's CPLDs (1K, 2K, and 3K families), but I have serious > doubts about their performance. I'm laess concerned with the propagation > delay than I am about the output edge rates. I assume I can skew the clock > for the receiving latch to compensate for the prop. delay (assuming I can > fix it in a range), but I can't very well have a 10 ns period if I have 5ns > (or more) edge rates. Any suggestions? Hi Mike, have you heared of ICUBE ? They sell programmable switch crossbars of different sizes. As far as I can remember they are able to handle data rates up to appr. 100 MHz. Cheers Tom ## Thomas Ebert e-mail: thebert@on-luebeck.de Tel.:+49(0)451 391322 ##Article: 3208
Has anyone tried to use the DEV_CLRn function in Alteras FLEX10k FPGAs? With this function enabled one I/O-pin ought to reset all FFs in the device regardless of whether they are connected in the design to that pin or not. Actually the pin does reset them, but it is driven low from inside the chip - thus resetting the whole design forever - and I could not figure out how to tri-state the pin. The MAX+ SW (even the new V.6.1) reports an error due to an assignment conflict when I e.g. want to declare the pin to be an input. So far I did not get appropriate feedback from Altera though I contacted their app-engs several times. Thanks in advance.Article: 3209
Hi everybody ! I'm interesting for run time reconfiguration of Xilinx fpga. my questions are : - Is it possible with actual Xilinx Family ( XC3000, XC4000) ? - How many time is necessary to reconfigure an XC3090 ? - Is there some references talking about this ? Thank you . e-mail: guermoud@lien.u-nancy.frArticle: 3210
In article <4loha0$5rr@arcturus.ciril.fr>, rabah@lien.u-nancy.fr (Hassan rabah) wrote: > Hi everybody ! > > I'm interesting for run time reconfiguration of Xilinx fpga. my > questions are : > > - Is it possible with actual Xilinx Family ( XC3000, XC4000) ? > - How many time is necessary to reconfigure an XC3090 ? > - Is there some references talking about this ? You can configure and reconfigure the XC3090 in several different modes. The fastest is called Slave Serial, where you provide the clock that shifts in the serial configuration data, 64,200 bits in the case of the XC3090. Max frequency is 10 MHz, so you can get the job done in 6.4 milliseconds. Other modes can be up to 15 times slower. You find the number of serial bits on page 2-120, and the 10 MHz limit on page 2-131 of the Xilinx Data Book. Peter Alfke, Xilinx ApplicationsArticle: 3211
Felix K.C. CHEN wrote: > > Dear Friends, > > I am designing a FPGA whose main function is a multi-channel DMA > engine. As you know that DMA engines consists of many counters. > The counters I need are not simple "incrementers". They are loadable, > count enable and asynchronous clear. > > we all know that VHDL synthesizer from both Synopsys and Exemplar > can infer counter from VHDL operators "+" and "-". But they also > provide users with the alternative of technology independant > component instantiation for counters, called design ware with > Synopsys and Modgen with Exemplar. By chance my company have > them both. > > Because the synthesized result of my design is so large that I > can not help suspect that the inferring style I used (please see > the sample code below) is not efficient. > > I'd like to try the component instanitiation alternative. But > I will have to modify my source code. At least I have to rebuild > the design hierarchy when I extract the counter out of the state > machine. So before I do this engineering, I ask you > for any opinion about these two approaches. > > With component instantiation appraoch, will there be any improvement on > the control signal generating logic, like LOAD CONTROL and COUNT ENABLE? > > Regards, > > Felix K.C. CHEN > > -- the sample code > > process: counter(RESETZ, CLK, state, count, ...) > begin > if (RESETZ='0') then > count <= 0; > elsif (CLK'event and CLK='1') then > case state is > when S1 => > if (condition) then > count <= load_value_1; -- load the counter > end if; > when S2 => > if (condition) then > count <= 0; -- clear the counter, a load too > end if; > when S3 => > if (condition) then > count <= count + "1"; -- count up > end if; > when S4 => > if (condition) then > count <= count + "1"; -- count up > end if; > when S5 => > if (condition) then > count <= count + "1"; -- count up > end if; > when others => > null; > end case; > end if; > end process; Knowing that you will have several counter-like functions, which may likely be controlled differently, I would suggest that you decouple the state machine from the controlled counter. This way you will be able to experiment w/ different implementations of the counter w/o having to rip-up your state machine each time. The instanced DesignWare or modgens are likely to be "optimal" in the sense of a standalone implementation; however, depending on whether you need ALL the function, it may not be optimal in your usage. If so, you might try "ungrouping" the counter within the context of the enclosed state machine and counter module, during compile. -- Synthesis Solutions http://www.ez-synthesis.com vmail: (415) 431-6429Article: 3212
Does anyone have a reference on the annual number of FPGAs shipped (or even revenue) by the top 3 FPGA companies. I assume the order is 1) Xilinx, 2) Altera, 3) Actel. Plenty of other players in the market, but from where I sit, these look like the big three. I've got a reference or two which includes PLDs which brings AMD and lattice up to the #3 & 4 positions ahead of actel. But they don't have much in the way of FPGAs (that I know of). -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable HDL Cores 20 Trafalgar Square http://www.vautomation.com Suite 443 Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 3213
In article <4loha0$5rr@arcturus.ciril.fr>, rabah@lien.u-nancy.fr (Hassan rabah) writes:
|> Hi everybody !
|>
|> I'm interesting for run time reconfiguration of Xilinx fpga. my
|> questions are :
|>
|> - Is it possible with actual Xilinx Family ( XC3000, XC4000) ?
It is possible to configure Xilinx FPGAs at run-time. Since you must
configure the entire FPGA, you must be able to tolerate configuration
times in the order of mili-seconds (10 Mhz config rate with ~64k config
bits). There are applications which make this feasible.
|> - How many time is necessary to reconfigure an XC3090 ?
In order to justify lengthy reconfiguration times, the application must
operate with a single configuration for a considerable length of time
(i.e. it is difficult to justify clock cycle configuration when configuration
takes several orders of magnitide more time). Applications which tolerate this
time include image processing and neural networks (see below).
|> - Is there some references talking about this ?
I have listed a few references I am aware of below.
- Mike
@InProceedings{eldredge-hutchings:94,
author = "J. G. Eldredge and B. L. Hutchings",
title = "Density Enhancement of a Neural Network Using {FPGA}s
and Run-Time Reconfiguration",
key = "app,rtr",
booktitle = "Proceedings of IEEE Workshop on {FPGA}s for Custom
Computing Machines",
editor = "D. A. Buell and K. L. Pocek",
year = "1994",
month = apr,
address = "Napa, CA",
pages = "180--188",
}
@InProceedings{ross-vellacott:93,
author = "D. Ross and O. Vellacott and M. Turner",
title = "An {FPGA}-based Hardware Accelerator for Image
Processing",
key = "system, app, rtr",
booktitle = "More {FPGAs}: Proceedings of the 1993 International
workshop on field-programmable logic and applications",
year = "1993",
month = sep,
address = "Oxford, England",
pages = "299--306",
editor = "W. Moore and W. Luk",
}
@Article{lautzenheiser:86,
author = "D. P. Lautzenheiser",
title = "Using Dynamic Reconfigurable Logic in {A} {XC2064}
Logic Cell Array",
key = "device,rtr,app",
journal = "Electro/86 and Mini/Micro Northeast Conference
Record",
year = "1986",
pages = "26/2/1--10",
month = may,
}
@InProceedings{lysaght:91,
author = "P. Lysaght",
title = "Dynamically Reconfigurable Logic in Undergraduate
Projects",
key = "app,rtr",
booktitle = "{FPGAs}: Proceedings of the 1991 International
workshop on field-programmable logic and applications",
editor = "W. Moore and W. Luk",
publisher = "Abingdon EE and CS Books",
address = "Oxford, England",
month = sep,
year = "1991",
}
--
Michael J. Wirthlin
Brigham Young University - Electrical Engineering Department
Reconfigurable Logic Laboratory (801) 378-7206
Article: 3214CALL FOR PARTICIPATION in the 6th Annual Advanced PLD & FPGA Conference and Exhibition. Tues/Wed 14th-15th May 1996 at the Excelsior Hotel, Heathrow, near London organised by Miller Freeman Technical Limited (see programme below) For registration details: email to ed98@cityscape.co.uk or visit http://dotelectronics.co.uk/ on the world-wide-web or contact Cathy Johnston Electronics Times Miller Freeman Technical Limited 30 Calderwood Street London SE18 6QH Tel: +44 181 316 3288 Fax: +44 181 316 3341 or +44 181 854 8980 PROGRAMME 14th May - Introductory day 2.00 - 5.00pm 'Introduction to PLDs and FPGAs' presentation and workshop session hosted by University of Kent 15th May Advanced PLD & FPGA Day 9.00am Registration & exhibition opens 9.20am Opening remarks 9.30am Keynote - "A users perspective and possibilities for the future' Mike Muller, marketing director Advanced RISC Machines Ltd. STREAM A APPLICATIONS 10.20am 'Image processing in Flex10K devices', Caleb Crome, Altera 10.50am 'A new method of implementing large high-speed multipliers in FPGAs', Tom Smart, Lucent Technologies 11.50am 'a 100Mbit Ehernet controller using time-driven place and route', Andy Biddle, Actel ASIC PROTOTYPING 12.20pm 'ASIC design through FPGA conversion and direct synthesis', Larry Lapides, Antares 2.15pm 'A cost-effective prototyping solution for ASIC design' Henry Sun, Crosspoint Solutions 2.45pm 'Timing and modeling issues when prototyping on FPGAs', Daniel Brasen, Minc-IST DSP & RECONFIGURABILITY 3.45pm 'DSP acceleration using a reconfigurable coprocessor FPGA' Joel Rosenberg, Atmel 4.15pm 'The DSP challenge', Thomas Oelsner, Quicklogic STREAM B ARCHITECTURE 10.20am 'An SRAM-based FPGA architecture' Scott Gould, IBM Microelectronics 10.50am 'Mach 5 - the future of CPLDs' Peter Trott, AMD 11.50am 'XPLA architecture for complex PLDs' Mark Aaldering, Philips Semiconductors 12.20pm 'Retargetting: a natural process step to increase perfromance and cut cost' Ludwig Klingenbeck, Motorola Semiconductors DESIGN ISSUES 2.15pm 'Navigating the FPGA design tool maze through work flow management', Wesley Ryder, Mentor Graphics 2.45pm 'Designing with CPLDs and FPGAs: dealing with diversity' Mark Flomenhoft, Synario Design Automation 3.45pm 'The LPM approach to high-level FPGA design', Jonathon Talbot, Veribest International 4.15pm 'Map, place and route: the key to high density PLD implementation', Bradly Fawcett, Xilinx 4.45pm CONFERENCE ENDS Peter Clarke Program Co-ordinator for 6th Advanced PLD & FPGA ConferenceArticle: 3215
Patrick Drolet wrote: > > Felix K.C. CHEN wrote: > > people always talk about "prototyping ASIC" with FPGA(s). But at least > > in my case, due to the uncertainty of market, ASIC solution is not > > possible at the moment. I have to find FPGA device whose gate count > > is about 20000 (at real utilization) and whose price is relative > > low to make the final product competitive. > We are happy with AT&T ORCA series. 40k and 25k gates solutions are > "quite" expensive, but if your design could fit in a couple of 10k gates > or 12k gates, your FPGA cost would be low. > > Patrick. The Lucent (formerly AT&T) Orca series is currently priced very low, possibly in an effort to gain market share and attention. I think you'll find that you can get the 2C26 in a typical 208QFP package for under $150 through normal distribution. You'll easily attain 20K utilised gates, if your design halfway "FPGA-friendly". Xilinx makes good parts, too... but for the moment Lucent is being very aggressive on pricing. Check with your local distributor or sales rep. Good Luck, Bob Elkind ************************************************************************** Bob Elkind email:eteam@aracnet.com CIS:72022,21 7118 SW Lee Road part-time fax number:503.357.9001 Gaston, OR 97119 cell:503.709.1985 home:503.359.4903 ******** Video processing, R&D, ASIC, FPGA design consulting *************Article: 3216
> > Felix K.C. CHEN wrote: > > > I have to find FPGA device whose gate count > > is about 20000 (at real utilization) and whose price is relative > > low to make the final product competitive. > > > > Don't tell me Altera's Flex10K-50. Its high price and its sole huge > > PGA package (more than 390 pins) stops me. I have tried Actel's > > DX32140 but its gate count is not enough either. They told me > > that Actel's backend tool does not support DX32200 yet. I have > > also tried the Xilinx's XC5200. But the result remained the same. > > I do not care for the operating speed of the final chip, as long > > as the chip can hold my design. > > > > What else FPGA vendors can I tried? > Unfortunately 20K+ gates is still a large expensive FPGA. For instance the Xilinx 4020E is about $200 in slower speed grades and might not be large enough. You might consider the following alternatives. - 2 XC5210 FPGAs @ $60 each and up to 192 pins for interconnect between them. - Reconsider the algorithm, and code portions of into a more sequntial form. This might allow you to trade time for space. Multipliers, barrel shifters and multiplexers are good candidates. - If your design has RAM, Adder/Subtracters or large data path MUXs, the XC4000 FPGAs can be very efficient, since they have hardware assist for these functions. - If speeed really isn't important for all functionality, it is possible to build a small CPU in the FPGA and to program it to implement the functionality sequentially. Maybe you could tell us more about your application? - Brad /========================================<>===========================================\ | Brad Taylor blt@emf.net | \========================================<>===========================================/Article: 3217
Hi everybody ! I need some informations about FPIC or FPID ( field programmable interconnect component or device ). References, Datasheet, leadership etc... Thanks for help. Tchao !Article: 3218
In the aftermath of FCCM, Jan Gray kicked off some discussion of FPGA-coprocessors. As a coupled of posting pointed out, there are now several efforts in various stages of exploring tightly coupled proc+FPGA architectures. I put together the following page as a central starting point for people interested in research in this area. <http://http.cs.berkeley.edu/projects/brass/reproc.html> I'm sure I left a few things out, so send me personal mail and I'll expand it as I become aware of additional, relevant work in the area. Andre'Article: 3219
Can someone tell me where can I find the following IC chips? SMDIC 1) MC/LM 2) 8870 (MITEL/MT/MCD) 3) LM 224 4) MAX250 /MAX251 DIP IC 1) GN137 2) 8870 3) NE561 Large volume order. Thanks. -- yingz@cs.tamu.eduArticle: 3220
Check out ICUBE at http://www.icube.com. Regards...Grason gcurtis@worldnet.att.net guermoud@lien.u-nancy.fr (Hassane Guermoud) wrote: > >Hi everybody ! > > >I need some informations about FPIC or FPID ( field programmable >interconnect component or device ). > >References, Datasheet, leadership etc... > > Thanks for help. > > > Tchao ! > >Article: 3221
Hi,
we think about using the "Synario Universal FPGA Design System" from DATA/IO.
Can anybody, who uses this system, give us some tips/hints ?
Thanks for all infos,
Kurt.
--
_/_/_/_/_/_/_/
_/ Volker Kurt Kamp (kurt@emphasys.de)
_/_/_/_/_/ _/
_/ _/ EMPHASYS Informationstechnik GmbH
_/_/_/ _/ _/ Alt-Moabit 94 - 10559 Berlin - Germany - Europe
_/ _/ _/ Tel: +49.30.399883 FAX: +49.30.3922836
_/ _/ _/ _/
Article: 3222In article <robyn.830313480@reef.cs.jcu.edu.au>, Robyn Cheyne <robyn@cs.jcu.edu.au> wrote: [... search for FPGA boards deleted ...] I maintain a list of such hardware at: "http://www.io.com/~guccione/HW_list.html". There are currently about 50 such boards (mostly research projects) out there. Hope this helps, -- Steve -- 4/29/96Article: 3223
guccione@xilinx.com (Steve Guccione) writes: >(...Stuff about FPGAs and CPUs working together deleted...) >I agree that a 400 MHz Alpha is able to get a lot of work done in a >short time. But the problem is the memory interface. When you start >getting cache misses, performance drops dramatically. Precisely. The most fundamental, and potentially the most important difference between CPUs and FCCMs is the processor-memory model. The sequential Von Neumann CPU model has a single unified memory space with only a single sequence of memory accesses permitted. Implementations of CPUs, memory systems and compilers infer some parallelism beyond that, but the model that programmers must code to is still limited to that sequential, one reference at a time model. FCCMs need not share that limitation. --Mike -- Mike Butts, Portland, Oregon mbutts@netcom.comArticle: 3224
In article 41C67EA6@rice.edu, Michael Filippo <filippo@rice.edu> () writes:
>Let me try it again...
>
>Does anyone know where (or if) I can get ECL or PECL (preferrable) gate arrays
>or FPGAs? I'm trying to design a high-speed (100 MHz) crossbar switch and I need
>some way to build multiple multi-bit 16-1 MUXs. I've looked at Lattice's CPLDs
>(1K, 2K, and 3K families), but I have serious doubts about their performance. I'm
>laess concerned with the propagation delay than I am about the output edge rates. I
>assume I can skew the clock for the receiving latch to compensate for the prop.
>delay (assuming I can fix it in a range), but I can't very well have a 10 ns period
>if I have 5ns (or more) edge rates. Any suggestions?
>
>--
>Mike Filippo
>filippo@rice.edu
>http://www-ce.rice.edu/ce/members/filippo/htdocs/filippo.html
Try looking into a relatively new startup company called Dyna Logic. They offer
some very fast SRAM baased parts with ECL, PECL, and GTL I/O, claiming 200 MHz
system performance and 5K usable gates.
I have a card from ar marketing person you can reach at chiki@dyna.com
************************************************************************
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******* ************* John Vincent
****** **************** Eastman Kodak Company
***** ******************* Equipment & Software Platform Center
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****** **************** Fax: 716-726-7131
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